ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT GENERAL DESCRIPTION FEATURES T h e I C S 8 3 0 2-01 i s a l o w s k e w, 1 - t o - 2 LVCMOS/LVTTL Fanout Buffer w/ComplemenHiPerClockS™ tary Output and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8302-01 has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8302-01 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for o u t p u t o p e r a t i n g s u p p l y m o d e s (V DDO). G u a r a n t e e d output and part-to-part skew characteristics make the I C S 8 3 0 2-01 i d e a l f o r clock distribution applications demanding well defined performance and repeatability. • Complementary LVCMOS / LVTTL output ,&6 • LVCMOS / LVTTL clock input accepts LVCMOS or LVTTL input levels • Maximum output frequency: 250MHz • Output skew: 165ps (maximum) • Part-to-part skew: 800ps (maximum) • Small 8 lead SOIC package saves board space • Full 3.3V or 3.3V core, 2.5V supply modes • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VDDO VDD CLK GND Q CLK 1 2 3 4 8 7 6 5 Q GND VDDO nQ ICS8302-01 nQ 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 8302AM-01 www.icst.com/products/hiperclocks.html 1 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT TABLE 1. PIN DESCRIPTIONS Number Name 1, 6 VDDO Power Type Description Output supply pins. 2 VDD Power Core supply pin. 3 CLK Input 4,7 GND Power Pulldown Power supply ground. LVCMOS / LVTTL clock input. 5 nQ Output Complementary clock output. LVCMOS / LVTTL interface levels. 8 Q Output Clock output. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 VDD, VDDO = 3.465V 22 VDD = 3.465V, VDDO = 2.625V Units pF pF CPD Power Dissipation Capacitance (per output) 16 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 7 Ω 8302AM-01 www.icst.com/products/hiperclocks.html 2 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Power Supply Voltage 3.465 V IDD Power Supply Current 13 mA IDDO Output Supply Current 4 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V 150 µA IIH Input High Current CLK VDD = VIN = 3.465V IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage 50Ω to VDDO/2 2.6 V IOH = -100µA 2.9 VOL Output Low Voltage V 50Ω to VDDO/2 0.5 V IOL = 100µA 0.2 V Maximum Units 250 MHz 2.7 ns TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle Minimum 1.8 Typical 2.18 50 ps ps 20% to 80% 300 800 ps ƒ≤ 133MHz 45 55 % 60 % 133MHz < ƒ ≤ 250MHz 40 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8302AM-01 165 800 www.icst.com/products/hiperclocks.html 3 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 13 mA IDDO Output Supply Current 4 mA TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V 150 µA IIH Input High Current CLK VDD = VIN = 3.465V IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage 50Ω to VDDO/2 1.8 V IOH = -100µA 2.2 VOL Output Low Voltage V 50Ω to VDDO/2 0.5 IOL = 100µA 0.2 V V TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 Minimum Typical 1.9 Maximum Units 250 MHz 2.9 ns tsk(o) Output Skew; NOTE 2, 4 250 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 900 ps tR / tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% 250 650 ps ƒ≤ 133MHz 45 55 % 60 % 133MHz < ƒ ≤ 250MHz 40 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8302AM-01 www.icst.com/products/hiperclocks.html 4 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT PARAMETER MEASUREMENT INFORMATION VDD, VDDO = 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDDO Qx LVCMOS GND = -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT V 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT V DD DDO 2 V DDO 2 Q nQ Qx LVCMOS GND = -1.65V±5% CLK SCOPE VDD Q 2 nQ V DDO 2 V DDO tsk(o) 2 t PD PROPAGATION DELAY PART 1 OUTPUT SKEW V DD Q 2 PART 2 80% V 80% DDO 20% 20% 2 Q Clock Outputs nQ t V DDO R t F 2 tsk(pp) PART-TO-PART SKEW OUTPUT RISE/FALL TIME nQ VDDO VDDO 2 Q 2 t PW t PERIOD odc = t PW t PERIOD odc & tPERIOD 8302AM-01 www.icst.com/products/hiperclocks.html 5 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8302-01 is: 322 8302AM-01 www.icst.com/products/hiperclocks.html 6 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT PACKAGE OUTLINE - SUFFIX M TABLE 6. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e H 4.00 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 8302AM-01 www.icst.com/products/hiperclocks.html 7 REV. A DECEMBER 10, 2002 ICS8302-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package ICS8302AM-01 8302A01 8 lead SOIC ICS8302AM-01T 8302A01 8 lead SOIC on Tape and Reel Count Temperature 96 per tube 2500 0°C to 70°C 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8302AM-01 www.icst.com/products/hiperclocks.html 8 REV. A DECEMBER 10, 2002