ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR GENERAL DESCRIPTION FEATURES The ICS85222-01 is a Dual LVCMOS / LVTTLto-Differential HSTL translator and a member of HiPerClockS™ the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-01 has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. • Two differential HSTL outputs ICS • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full 3.3V and 2.5V operating supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT CLK0 Q0 nQ0 CLK1 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK0 CLK1 GND ICS85222-01 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View 85222AM-01 www.icst.com/products/hiperclocks.html 1 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Description 3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels. 5 GN D Power Power supply ground. 6 CLK1 Input Pullup LVCMOS / LVTTL clock input. 7 CLK0 Input Pullup LVCMOS / LVTTL clock input. Differential output pair. HSTL interface levels. Power Positive supply pin. 8 VDD NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 85222AM-01 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5% OR VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3. 3 3.465 V VDD Positive Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 35 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5% OR VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage CLK0, CLK1 Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage CLK0, CLK1 -0.3 1.3 V IIH Input High Current CLK0, CLK1 5 µA IIL Input Low Current CLK0, CLK1 VDD = VIN = 3.465V VDD = VIN = 2.625V VDD = 3.465, VIN = 0V VDD = 2.625, VIN = 0V -150 µA TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V±5% OR VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 Test Conditions VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum 1 Typical Maximum Units 1.4 V VDD = 3.3V±5% 0 0.4 V VDD = 2.5V±5% 0 0.55 V VDD = 3.3V±5% 0.6 1.4 V VDD = 2.5V±5% 0.45 1.4 V NOTE 1: Outputs terminated with 50Ω to GND. 85222AM-01 www.icst.com/products/hiperclocks.html 3 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 700 Maximum Units 350 MHz 1075 ps 375 ps 800 ps 20% to 80% 150 ƒ ≤ 150MHz 48 52 % 150 < ƒ ≤ 250MHz 46 54 % 250 < ƒ ≤ 350MHz 45 55 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum 700 Typical Maximum Units 350 MHz 1200 ps 475 ps 20% to 80% 150 800 ps ƒ ≤ 150MHz 48 52 % 150 < ƒ ≤ 350MHz 46 54 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85222AM-01 www.icst.com/products/hiperclocks.html 4 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR PARAMETER MEASUREMENT INFORMATION 2.5V ± 5% 3.3V ± 5% V DD Qx SCOPE V DD Qx SCOPE HSTL HSTL nQx nQx GND GND 0V 0V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT PART 1 nQx CLK0, CLK1 VDD Qx 2 PART 2 nQy nQ0, nQ1 Qy Q0, Q1 tPD tsk(pp) PART-TO-PART SKEW PROPAGATION DELAY nQ0, nQ1 80% 80% Q0, Q1 VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 85222AM-01 www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. 85222AM-01 HSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR SCHEMATIC EXAMPLE Figure 2 shows a schematic example of ICS85222-01. In this example, the inputs are driven by 7Ω output LVCMOS drivers with series terminations. The decoupling capacitors should be physically located near the power pin. For ICS85222-01, the unused output need to be terminated. VDD=3.3V Zo = 50 Ohm - U1 Q1 Ro ~ 7 Ohm R5 Zo = 50 Ohm 43 5 6 7 8 GND CLK1 CLK0 VDD nQ1 Q1 nQ0 Q0 4 3 2 1 Zo = 50 Ohm + R1 50 R2 50 LVHSTL Input ICS85222-01 Driv er_LVCMOS VDD=3.3V VDD=3.3V C1 0.1u Zo = 50 Ohm - Q2 Zo = 50 Ohm Ro ~ 7 Ohm R6 Zo = 50 Ohm + 43 R3 50 R4 LVHSTL Input 50 Driv er_LVCMOS FIGURE 2. ICS85222-01 HSTL BUFFER SCHEMATIC EXAMPLE 85222AM-01 www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85222-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85222-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 35mA = 121.3mW Power (outputs)MAX = 82.34mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 82.34mW = 164.68mW Total Power_MAX (3.465V, with all outputs switching) = 121.3mW + 164.68mW = 285.98mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total device power dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.286W * 103.3°C/W = 99.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85222AM-01 www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 3. VDD Q1 VOUT RL 50Ω FIGURE 3. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V OL_MAX L /R ) * (V L -V DD_MAX DD_MAX ) OH_MAX -V ) OL_MAX Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.82mW Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW 85222AM-01 www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85222-01 is: 443 85222AM-01 www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 85222AM-01 www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Package Temperature ICS85222AM-01 5222A01 8 Lead SOIC tube 0°C to 70°C ICS85222AM-01T 5222A01 8 Lead SOIC 2500 tape & reel 0°C to 70°C ICS85222AM-01LF 5222A01L 8 Lead "Lead-Free" SOIC tube 0°C to 70°C ICS85222AM-01LFT 5222A01L 8 Lead "Lead-Free" SOIC 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85222AM-01 www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 15, 2005 ICS85222-01 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR REVISION HISTORY SHEET Rev Table Page 6 T8 11 1 6 8-9 12 A A T8 85222AM-01 Description of Change Added Application Note, "Wiring the Differential Input to Accept Single Ended Levels". Ordering Information Table - added Lead-Free par t number. Added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation. Ordering Information Table - added tape & reel quantity and lead-free note. www.icst.com/products/hiperclocks.html 13 Date 1/11/05 11/15/05 REV. A NOVEMBER 15, 2005