PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853011C is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ HiPerClockS™ ECL Fanout Buffer and a member of the HiPerClockS ™ family of High Perfor mance Clock Solutions from ICS. The ICS853011C is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS853011C ideal for those clock distribution applications demanding well defined perfor mance and repeatability. • 2 differential 2.5V/3.3V LVPECL / ECL outputs ICS • 1 differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 3GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input • Output skew: 5ps (typical) • Part-to-part skew: TBD • Propagation delay: 250ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V • -40°C to 85°C ambient operating temperature • Pin compatible with MC100LVEP11 and SY100EP11U BLOCK DIAGRAM PCLK nPCLK PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc PCLK nPCLK VEE ICS853011C 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View ICS853011C 8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853011CM www.icst.com/products/hiperclocks.html REV. A MARCH 19, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power 6 nPCLK Input 7 PCLK Input 8 VCC Power Description Negative supply pin. Pullup/ Pulldown Pulldown Clock input. LVPECL interface levels. Clock input. Default LOW when left floating. LVPECL interface levels. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor 75 KΩ RPULLUP Input Pullup Resistor 37 KΩ 853011CM Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Inputs, VI (LVPECL mode) 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Negative Supply Voltage, VEE Outputs, IO Continuous Current Surge Current cations only. Functional operation of product at these conditions or any conditions beyond those 50mA 100mA listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) mum rating conditions for extended periods may affect product reliability. (Junction-to-Ambient) for 8 Lead SOIC Package Thermal Impedance, θJA 101.7°C/W (0 m/s) (Junction-to-Ambient) for 8 Lead TSSOP TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage Test Conditions I EE Power Supply Current Minimum Typical Maximum Units 2.375 3.3 3.8 V 18 mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V -40°C 25°C 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 2.275 2.295 2.295 V VOL Output Low Voltage; NOTE 1 1.545 1.52 1.535 V VPP 800 800 800 V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current IIL Input Low Current VCMR Min Typ Max Min Typ Max Min Max Units V µA PCLK µA nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. 853011CM Typ www.icst.com/products/hiperclocks.html 3 µA REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V -40°C Typ 25°C Typ 85°C Typ Symbol Parameter VOH Output High Voltage; NOTE 1 1.475 1.495 1.495 V VOL Output Low Voltage; NOTE 1 0.745 0.72 0.735 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current PCLK Input Low Current nPCLK 800 800 800 V VCMR IIH IIL Min Max Min Max Min Max Units V µA µA µA Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V Symbol -40°C Parameter Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 -1.025 -1.005 -1.005 V VOL Output Low Voltage; NOTE 1 -1.755 -1.78 -1.765 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current Input PCLK 800 800 800 V VCMR IIH IIL V µA µA Low Current nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V -40°C Symbol Parameter fMAX Output Frequency t PD Propagation Delay; NOTE 1 Min tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR/tF Output Rise/Fall Time Typ µA 25°C Max Min Typ 85°C Max Min Typ Max Units 3 3 3 GHz 240 250 260 ps 5 5 5 ps ps 20% to 80% 160 160 160 ps odc Output Duty Cycle f ≤ 1GHz 50 50 50 % All parameters are measured at f ≤ 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853011CM www.icst.com/products/hiperclocks.html 4 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nPCLK LVPECL V Cross Points PP V CMR PCLK nQx VEE V EE -1.8V to -0.375V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nPCLK 80% 80% PCLK VSW I N G Clock Outputs nQ0, nQ1 20% 20% tF tR Q0, Q1 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0, nQ1 Q0, Q1 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 853011CM www.icst.com/products/hiperclocks.html 5 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 853011CM 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 853011CM www.icst.com/products/hiperclocks.html 7 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R2 50 R1 50 CML R3 120 SSTL R4 120 Zo = 60 Ohm Zo = 50 Ohm PCLK PCLK Zo = 60 Ohm nPCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V R4 125 R3 125 Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PCL K/n PC LK R2 1K FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853011CM www.icst.com/products/hiperclocks.html 8 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853011C. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853011C is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 18mA = 68.4mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW Total Power_MAX (3.8V, with all outputs switching) = 68.4mW + 61.88mW = 130.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.130W * 103.3°C/W = 98.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 853011CM 0 1 2 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 9 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX –0.935V ) = 0.935V For logic low, VOUT = V (V =V =V CC_MAX – 1.67V ) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V )= OL_MAX [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853011CM www.icst.com/products/hiperclocks.html 10 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS853011C is: 96 853011CM www.icst.com/products/hiperclocks.html 11 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER FOR 8 LEAD SOIC TABLE 7A. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e H 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 853011CM www.icst.com/products/hiperclocks.html 12 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER FOR 8 LEAD TSSOP TABLE 7B. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.10 A1 0 0.15 A2 0.79 0.97 b 0.22 0.38 c 0.08 0.23 D 3.00 BASIC E 4.90 BASIC E1 3.00 BASIC e 0.65 BASIC e1 1.95 BASIC L 0.40 0.80 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-187 853011CM www.icst.com/products/hiperclocks.html 13 REV. A MARCH 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853011C LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS853011CM 853011C 8 lead SOIC 96 per tube -40°C to 85°C ICS853011CMT 853011C 8 lead SOIC on Tape and Reel 2500 -40°C to 85°C ICS853011CMLF 3011CLF "Lead Free" 8 lead SOIC 96 per tube -40°C to 85°C ICS853011CMLFT 3011CLF "Lead Free" 8 lead SOIC on Tape and Reel 2500 -40°C to 85°C ICS853011CG 011C 8 lead TSSOP 96 per tube -40°C to 85°C ICS853011CGT 011C 8 lead TSSOP on Tape and Reel 2500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853011CM www.icst.com/products/hiperclocks.html 14 REV. A MARCH 19, 2004