ICS91857 Integrated Circuit Systems, Inc. Value SSTL_2 Clock Driver (60MHz - 220MHz) Recommended Application: Zero delay board fan-out memory modules GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND Product Description/Features: • Meets PC3200 specification for DDRI-400 support • Low skew, low jitter PLL clock driver • 1 to 10 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • PD# for power management • Spread Spectrum tolerant inputs • Auto PD when input signal removed Switching Characteristics: • CYCLE - CYCLE jitter (>100MHz):<75ps • OUTPUT - OUTPUT skew: <100ps 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS91857 Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUTC FB_OUTT GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND 48-Pin TSSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP Functionality Block Diagram INPUTS OUTPUTS PLL State AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC GND H L H L H L H Bypassed/off GND H H L H L H L Bypassed/off 2.5V (nom) L L H Z Z Z Z off 2.5V (nom) L H L Z Z Z Z off 2.5V (nom) H L H L H L H on 2.5V (nom) H H L H L H L on 2.5V (nom) X Z Z Z Z off FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 Control <20MHz)(1) PD# Logic CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 FB_INT FB_INC CLK_INC CLK_INT CLKT5 CLKC5 PLL CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 0494C—08/15/05 ICS91857 Pin Descriptions PIN NUMBER 4, 11, 12, 15, 21, 28, 34, 38, 45, PIN NAME TYPE DESCRIPTION VDD PWR Power supply 2.5V up to DDR 333. Power supply 2.6V for DDR-I at 400MHz. 1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 PWR Ground 16 AVDD PWR Analog power supply, 2.5V up to DDR 333. Power supply 2.6V for DDR-I at 400MHz. 17 AGND PWR A n a l o g gr o u n d . 27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 OUT "Tr ue" Clock of differential pair outputs. 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 OUT "Complementar y" clocks of differential pair outputs. 14 CLK_INC IN "Complementar y" reference clock input 13 CLK_INT IN "True" reference clock input 33 FB_OUTC OUT "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. 32 FB_OUTT OUT "True" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. 36 FB_INT IN "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. 35 FB_INC IN "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. 37 PD# IN Power Down. LVCMOS input This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels. ICS91857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC) the 2.5V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INC, CLK_INT). The PLL in the ICS91857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT, FB_INC) provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). The ICS91857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. ICS91857 is characterized for operation from 0°C to 70°C and will meet JEDEC Standard 82-1 and 82-1A for Registered DDR Clock Driver. 0494C—08/15/05 2 ICS91857 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND –0.5 V to VDD + 0.5 V 0°C to +70°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics for DDR200/266/333 - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage A VDD, VDD = 2.5V ± 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current SYMBOL I IH I IL I DD2.5 I DDPD IOH Output Low Current I OL VDD = 2.3V, VOUT = 1.2V I OZ VDD=2.7V, Vout=V DD or GND ±10 mA VIK VDDQ = 2.3V Iin = -18mA -1.2 V High Impedance Output Current Input Clamp Voltage High-level output voltage VOH Low-level output voltage VOL Input Capacitance1 Output Capacitance1 1 CIN COUT CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf @ 200MHz CL = 0pf VDD = 2.3V, VOUT = 1V VDD = min to max, I OH = -1 mA VDDQ = 2.3V, I OH = -12 mA VDD = min to max I OL=1 mA VDDQ = 2.3V I OH=12 mA VI = GND or V DD VOUT = GND or VDD MIN 5 TYP -18 -32 UNITS µA µA mA mA mA 26 35 mA 5 260 100 VDDQ - 0.1 V 1.7 V 3 3 Guaranteed by design at 170MHz, not 100% tested in production. 0494C—08/15/05 3 MAX 0.1 V 0.6 V pF pF ICS91857 Electrical Characteristics for DDRI-400 - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current SYMBOL I IH I IL I DD2.5 IDDPD I OH Output Low Current I OL V DD = 2.3V, VOUT = 1.2V I OZ V DD=2.7V, Vout=VDD or GND ±10 mA VIK V DDQ = 2.3V Iin = -18mA -1.2 V High Impedance Output Current Input Clamp Voltage High-level output voltage VOH Low-level output voltage VOL Input Capacitance1 Output Capacitance1 1 CIN COUT CONDITIONS V I = VDD or GND V I = VDD or GND CL = 0pf @ 200MHz CL = 0pf V DD = 2.3V, VOUT = 1V V DD = min to max, I OH = -1 mA V DDQ = 2.3V, I OH = -12 mA V DD = min to max I OL=1 mA V DDQ = 2.3V I OH=12 mA V I = GND or VDD V OUT = GND or VDD MIN 5 TYP -18 -32 UNITS µA µA mA mA mA 26 35 mA 5 260 100 VDDQ - 0.1 V 1.7 V 3 3 Guaranteed by design at 220MHz, not 100% tested in production. 0494C—08/15/05 4 MAX 0.1 V 0.6 V pF pF ICS91857 Recommended Operating Condition for DDR200/266/333 (see note1) TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated) PARAMETER Supply Voltage SYMBOL VDDQ, AVDD Low level input voltage VIL High level input voltage VIH DC input signal voltage (note 2) Differential input signal voltage (note 3) CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# MIN 2.3 -0.3 VDDQ/2 + 0.18 1.7 TYP MAX UNITS 2.7 V V VDDQ/2 - 0.18 0.7 V V VDDQ + 0.6 V -0.3 VDDQ V 0.36 0.7 VDDQ + 0.6 VDDQ + 0.6 V V VOX VDDQ/2 - 0.15 VDDQ/2 + 0.15 V VIX VDDQ/2 - 0.2 VDDQ/2 + 0.2 V I OH 0.12 mA Low level output current I OL 12 mA Input slew rate Operating free-air temperature SR 1 4 V/ns TA 0 70 °C Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current VID DC - CLKT, FB_INT AC - CLKT, FB_INT Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signal must be crossing. 0494C—08/15/05 5 ICS91857 Recommended Operating Condition for DDRI-400 (see note1) TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V PARAMETER Supply Voltage SYMBOL VDDQ, AVDD Low level input voltage VIL High level input voltage VIH DC input signal voltage (note 2) Differential input signal voltage (note 3) CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# MIN 2.5 -0.3 VDDQ/2 + 0.18 1.7 TYP 2.6 MAX UNITS 2.7 V V VDDQ/2 - 0.18 0.7 V V VDDQ + 0.3 V -0.3 VDDQ V 0.36 0.7 VDDQ + 0.6 VDDQ + 0.6 V V VOX VDDQ/2 - 0.15 VDDQ/2 + 0.15 V VIX VDDQ/2 - 0.2 VDDQ/2 + 0.2 V I OH 12 mA Low level output current I OL -12 mA Input slew rate Operating free-air temperature SR 1 4 V/ns TA 0 70 °C Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current VID DC - CLKT, FB_INT AC - CLKT, FB_INT Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signal must be crossing. 0494C—08/15/05 6 ICS91857 Timing Requirements for DDR200/266/333 TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp 2.5V ± 0.2V @ 25°C 2.5V ± 0.2V @ 25°C dtin MAX UNITS 60 170 MHz 95 170 MHz 40 60 % 100 µs MIN MAX UNITS 60 230 MHz 95 220 MHz 40 60 % 100 µs TSTAB Timing Requirements for DDRI-400 TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V CONDITIONS PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp 2.6V ± 0.1V 2.6V ± 0.1V dtin TSTAB Switching Characteristics for DDR200/266/333 PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Static Phase Offset Output to Output Skew Pulse skew SYMBOL CONDITION MIN TYP MAX UNITS t PLH1 CLK_IN to any output 3.5 ns t PLL1 CLK_IN to any output 3.5 ns 3 3 ns ns ps tEN tdis Tjit (per) t (jit_hper) t (sir_I) t (sl_o) Tcyc -Tcyc PD# to any output PD# to any output 100 - 200 MHz 100 - 200 MHz 100 - 200 MHz t(spo)3 Tskew Tskewp Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. Switching characteristics guaranteed for application frequency range. 3. Static phase offset shifted by design. 0494C—08/15/05 7 -75 -75 1 1 -75 -50 0 75 75 4 2 75 50 100 100 V/ns V/ns ps ps ps ps ICS91857 Switching Characteristics for DDRI-400 PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Static Phase Offset Output to Output Skew Pulse skew SYMBOL CONDITION MIN TYP MAX UNITS t PLH1 CLK_IN to any output 3.5 ns t PLL1 CLK_IN to any output 3.5 ns 3 3 ns ns ps tEN tdis Tjit (per) t (jit_hper) t (sir_I) t (sl_o) Tcyc -Tcyc PD# to any output PD# to any output 100 - 200 MHz 100 - 200 MHz 100 - 200 MHz t(spo)3 Tskew Tskewp Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. Switching characteristics guaranteed for application frequency range. 3. Static phase offset shifted by design. 0494C—08/15/05 8 -50 -75 1 1 -75 -50 0 50 75 4 2 75 50 75 100 V/ns V/ns ps ps ps ps ICS91857 Parameter Measurement Information VDD V(CLKC) R = 60Ω R = 60Ω VDD/2 V(CLKC) ICS91857 GND Figure 1. IBIS Model Output Load VDD/2 C = 14 pF -VDD/2 ICS91857 R = 10Ω Z = 60Ω SCOPE Z = 50Ω R = 50Ω V(TT) R = 10Ω Z = 60Ω Z = 50Ω R = 50Ω V(TT) C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit YX, FBOUTC YX, FBOUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle Jitter 0494C—08/15/05 9 ICS91857 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n å n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX# YX YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter 0494C—08/15/05 10 t ( ) n+1 ICS91857 Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t (hper_n+1) t (hper_n) 1 fo t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tslrr(i) tslrf(i) slrf(o) Figure 8. Input and Output Slew Rates 0494C—08/15/05 11 ICS91857 c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 L E1 E INDEX AREA 1 2 a D A A2 A1 VARIATIONS -Ce N SEATING PLANE b 48 aaa C D mm. MIN MAX 12.40 12.60 D (inch) MIN .488 Ref erence Doc.: JEDEC Publicat ion 95, M O-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (240 mil) (20 mil) Ordering Information ICS91857yGLFT Example: ICS XXXX y G - PPP - LF - T Designation for tape and reel packaging RoHS Compliant (Optional) Pattern Number Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0494C—08/15/05 12 MAX .496 ICS91857 c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.40 BASIC 0.016 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.08 -.003 L E1 E INDEX AREA 1 2 α D A A2 VARIATIONS A1 -Ce N 48 SEATING PLANE b D (inch) D mm. MIN 9.60 MAX 9.80 MIN .378 Reference Do c.: JEDEC P ublicatio n 95, M O-153 aaa C 10-0037 4.40 mm. Body, 0.40 mm. pitch TSSOP (TVSOP) (173 mil) (16 mil) Ordering Information ICS91857yLLFT Example: ICS XXXX y L - PPP - LF -T Designation for tape and reel packaging RoHS Compliant (Optional) Pattern Number Package Type L = TSSOP (TVSOP) Revision Designator (will not correlate with datasheet revision) Device Type 0494C—08/15/05 Prefix ICS = Standard Device 13 MAX .386 ICS91857 Revision History Rev. C Issue Date Description 8/15/2005 Added LF Ordering Information. Page # 12-13 0494C—08/15/05 14