ICS951411 Integrated Circuit Systems, Inc. System Clock Chip for ATI RS400 P4TM-based Systems Recommended Application: ATI RS400 systems using Intel P4TM processors Features/Benefits: • 2- Programmable Clock Request pins for SRC clocks • Supports CK410 or CK409 frequency table mapping • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Output Features: • 6 - Pairs of SRC/PCI-Express clocks • 2 - Pairs of ATIG (SRC/PCI Express*) clocks • 3 - Pairs of Intel P4 clocks • 3 - 14.318 MHz REF clocks • 1 - 48MHz USB clock • 1 - 33 MHz PCI clock seed Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter <125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Pin Configuration REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.000 48.000 48.000 48.000 48.000 48.000 48.000 48.000 Functionality - (CK410# = 1) FS_C1 CPU Byte6 FS_B1 FS_A1 MHz bit5 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 100.00 200.00 133.33 166.67 200.00 400.00 266.67 333.33 SRC MHz PCI MHz REF MHz USB MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 48.000 48.000 48.000 48.000 48.000 48.000 48.000 48.000 1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. X1 X2 VDD48 USB_48MHz GND VTT_PWRGD#/PD SCLK SDATA **FS_C **CLKREQA# **CLKREQB# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS951411 Functionality - (CK410# = 0) CPU SRC PCI FS_C1 FS_B1 FS_A1 MHz MHz MHz 0 266.66 100.00 33.33 0 1 133.33 100.00 33.33 0 0 200.00 100.00 33.33 1 1 166.66 100.00 33.33 0 333.33 100.00 33.33 0 1 100.00 100.00 33.33 1 0 400.00 100.00 33.33 1 RESERVED 1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDREF GND **FS_A/REF0 **FS_B/REF1 **TEST_SEL/REF2 VDDPCI **CK410#/PCICLK0 GNDPCI *CPU_STOP# CPUCLKT0 CPUCLKC0 VDDCPU GNDCPU CPUCLKT1 CPUCLKC1 CPUCLKT2_ITP CPUCLKC2_ITP VDDA GNDA IREF GNDSRC VDDSRC SRCCLKT0 SRCCLKC0 VDDATI GNDATI ATIGCLKT0 ATIGCLKC0 Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor Pins preceeded by '*' have a 120 Kohm Internal Pull Up resistor 56-pin SSOP & TSSOP 0891E—03/07/05 *Other names and brands may be claimed as the property of others. ICS951411 Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE IN OUT PWR OUT PWR 1 2 3 4 5 X1 X2 VDD48 USB_48MHz GND 6 VTT_PWRGD#/PD IN 7 8 9 SCLK SDATA **FS_C IN I/O IN 10 **CLKREQA# IN 11 **CLKREQB# IN 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1 OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR OUT OUT DESCRIPTION Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48.00MHz USB clock Ground pin. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Frequency select latch input pin Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs True clock of differential SRC clock pair. Complementary clock of differential SRC clock pair. 0891E—03/07/05 2 ICS951411 Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME 29 30 31 32 33 34 35 36 ATIGCLKC0 ATIGCLKT0 GNDATI VDDATI SRCCLKC0 SRCCLKT0 VDDSRC GNDSRC 37 IREF 38 39 GNDA VDDA 40 CPUCLKC2_ITP 41 CPUCLKT2_ITP 42 CPUCLKC1 43 CPUCLKT1 44 45 GNDCPU VDDCPU 46 CPUCLKC0 47 CPUCLKT0 48 49 *CPU_STOP# GNDPCI 50 **CK410#/PCICLK0 51 VDDPCI 52 **TEST_SEL/REF2 53 54 55 56 **FS_B/REF1 **FS_A/REF0 GND VDDREF PIN TYPE OUT OUT PWR PWR OUT OUT PWR PWR DESCRIPTION Complementary clock of differential SRC clock pair. True clock of differential SRC clock pair. Ground for ATI Gclocks, nominal 3.3V Power supply ATI Gclocks, nominal 3.3V Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs This pin establishes the reference current for the differential current-mode OUT output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. PWR Ground pin for the CPU outputs PWR Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. IN Stops all CPUCLK, except those set to be free running clocks PWR Ground pin for the PCI outputs FS Table select latch input pin / 3.3V PCI clock output. I/O 0 = CK410 FS Table, 1 = CK409 FS Table PWR Power supply for PCI clocks, nominal 3.3V I/O I/O I/O PWR PWR TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock. 1 = All outputs are CK410 REF/N test mode 0 = All outputs behave normally. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin. Ref, XTAL power supply, nominal 3.3V 0891E—03/07/05 3 ICS951411 Integrated Circuit Systems, Inc. General Description ICS951411 provides a single-chip clocking solution for the ATI RS400-based systems using the latest Intel P4 processors. ICS951411 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and also provides highly accurate SRC clocks for PCI Express support. Two Clock Request pins are provided for Express-CardTM support. Block Diagram REF(2:0) X1 X2 USB_48MHz XTAL OSC. FIXED PLL DIVIDER PCICLK0 ATIGCLK(1:0) MAIN PLL SRCCLK(7:3,0) DIVIDERS CPUCLK(2:0) CK410# FS(C:A) CLKREQA# CLKREQB# CPU_STOP# VTT_PWRGD#/PD SDATA SCLK CONTROL LOGIC IREF Power Groups Pin Number VDD GND 56 55 51 49 45 44 14, 21, 35 15, 20, 26, 36 32 31 39 38 3 5 Description Xtal, REF PCICLK output CPUCLK Outputs SRCCLK outputs ATIGCLK outputs Analog, CPU PLL USB_48MHz output 0891E—03/07/05 4 ICS951411 Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS951411 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0891E—03/07/05 5 Not acknowledge stoP bit ICS951411 Integrated Circuit Systems, Inc. Table1: CPU Frequency Selection Table Bit 4 Bit 3 Bit2 Bit1 Bit0 CPU FS4 CPU FS3 FSC FSB FSA (CK410#) (SS_EN) 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 CPU (MHz) 266.6667 133.3333 200.0000 166.6668 333.3335 100.0000 400.0000 266.6667 133.3333 200.0000 166.6668 333.3335 100.0000 400.0000 100.0000 133.3333 200.0000 166.6668 200.0000 266.6667 400.0000 333.3335 100.0000 133.3333 200.0000 166.6668 200.0000 266.6667 400.0000 333.3335 PCI33 (MHz) Spread % 33.3333 33.3333 33.3333 33.3334 No Spread 33.3334 33.3333 33.3333 Reserved 33.3333 33.3333 33.3333 -0.5% 33.3334 33.3334 33.3333 33.3333 Reserved 33.3333 33.3333 33.3333 33.3334 No Spread 33.3333 33.3333 33.3333 33.3334 33.3333 33.3333 33.3333 33.3334 -0.5% 33.3333 33.3333 33.3333 33.3334 0891E—03/07/05 6 C K 4 1 0 C K 4 0 9 ICS951411 Integrated Circuit Systems, Inc. Table2: SRC & ATIG Frequency Selection Table SRC FS4 SRC Bit2 Bit1 Bit0 (SS_EN) FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SRC(7:3,0), Spread SRC ATIG(1:0) % OverClock (MHz) 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 1.00 1.00 1.00 1.00 1.01 1.01 1.01 1.01 1.02 1.02 1.02 1.02 1.04 1.04 1.04 1.04 1.00 1.00 1.00 1.00 1.01 1.01 1.01 1.01 1.02 1.02 1.02 1.02 1.04 1.04 1.04 1.04 0891E—03/07/05 7 ICS951411 Integrated Circuit Systems, Inc. SMBus Table: Frequency Select Register Byte 0 Pin # Name Bit 7 - FS Source Control Function Type 0 1 PWD Latched Input or SMBus Frequency Select RW Latched Inputs SMBus 0 Bit 6 SS_EN Spread Enable RW OFF ON Bit 5 Reserved Reserved RW Reserved Reserved Bit 4 CK410# CPU Freq Select Bit 4 RW Bit 3 CPU FS3 CPU SS_EN RW See Table 1: CPU Bit 2 CPU FS_C CPU Freq Select Bit 2 RW Frequency Selection Table RW Bit 1 CPU FS_B CPU Freq Select Bit 1 Bit 0 CPU FS_A CPU Freq Select Bit 0 RW NOTE: Byte 0 bit 6 and Byte 0 bit 3 must BOTH be '1' to enable spread for the PCI $ CPU clocks. Byte 5 bit 4 must be set to 1 to enable spread for the SRC & ATIGCLKS. SMBus Table: Output Control Register Byte 1 Pin # Name 50 Bit 7 PCICLK0 41,40 Bit 6 CPUCLK2 4 Bit 5 USB_48MHz 54 Bit 4 REF0 53 Bit 3 REF1 52 Bit 2 REF2 47,46 Bit 1 CPUCLK0 43,42 Bit 0 CPUCLK1 Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable SMBus Table: CLKREQB# Output Control Register Byte 2 0 Pin # Name Control Function Type CLKREQB# Controls Does not 12,13 Bit 7 REQBSRC7 RW SRC7 control CLKREQB# Controls Does not 16,17 Bit 6 REQBSRC6 RW SRC6 control CLKREQB# Controls Does not 18,19 Bit 5 REQBSRC5 RW SRC5 control CLKREQB# Controls Does not 22,23 Bit 4 REQBSRC4 RW SRC4 control CLKREQB# Controls Does not 24,25 Bit 3 REQBSRC3 RW SRC3 control Bit 2 Reserved Reserved RW Reserved Bit 1 Reserved Reserved RW Reserved CLKREQB# Controls Does not 34,33 Bit 0 REQBSRC0 RW SRC0 control NOTE: CPU0_Stop_En (Byte2, bit 2) only exists in devices with REV ID = 2 or higher 0891E—03/07/05 8 0 X Latched 0 Latched Latched Latched 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 1 PWD Controls 0 Controls 0 Controls 0 Controls 0 Controls 0 Reserved Reserved X X Controls 0 ICS951411 Integrated Circuit Systems, Inc. SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register Byte 3 Pin # Name Control Function Type SRCCLK7 RW 12,13 Bit 7 Master Output control. 16,17 SRCCLK6 RW Bit 6 Enables or disables 18,19 SRCCLK5 RW Bit 5 output, regardless of 22,23 SRCCLK4 RW Bit 4 CLKREQ# inputs. 24,25 SRCCLK3 RW Bit 3 34,33 SRCCLK0 RW Bit 2 CLKREQA# Controls 24,25 REQASRC3 RW Bit 1 SRC3 CLKREQA# Controls 34,33 REQASRC0 RW Bit 0 SRC0 SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register Byte 4 Pin # Name Control Function CLKREQA# Controls 12,13 REQASRC7 Bit 7 SRC7 CLKREQA# Controls 16,17 REQASRC6 Bit 6 SRC6 CLKREQA# Controls 18,19 REQASRC5 Bit 5 SRC5 CLKREQA# Controls 22,23 REQASRC4 Bit 4 SRC4 Output Enable 27,28 ATIGCLK1 Bit 3 These outputs cannot be controlled by CLKREQ# 30,29 ATIGCLK0 Bit 2 pins. Bit 1 CPU, SRC, ATIG Differential Output Disable Mode Bit 0 4 USB_48Str Hi-Z or driven when disabled Type RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Does not control Does not control 0 Does not control Does not control Does not control Does not control 1 Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 Controls 0 Controls 0 1 PWD Controls 0 Controls 0 Controls 0 Controls 0 RW Disabled Enabled 1 RW Disabled Enabled 1 RW Driven Hi-Z 0 1X 2X 1 48MHz Strength Control RW Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output. Behavior of the device is undefined under these conditions. SMBus Table: Output Drive and ATIG Frequency Control Register Pin # Name Control Function Type Byte 5 0 1 52 REF2Str REF2 Strength Control RW 1X 2X Bit 7 Free-Run Stoppable 41,40 0 = CPU is free-run CPU2_Stop_En RW Bit 6 Free-Run Stoppable 43,42 CPU1_Stop_En 1 = CPU is stopped by RW Bit 5 SRCFS4 Freq Select Bit 4 RW Bit 4 (SS_EN) (SS_EN) See Table 2 SRC SRCFS3 Freq Select Bit 3 RW Bit 3 Frequency Selection SRCFS2 Freq Select Bit 2 RW Bit 2 SRCFS1 Freq Select Bit 1 RW Bit 1 SRCFS0 Freq Select Bit 0 RW Bit 0 NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher 0891E—03/07/05 9 PWD 1 1 1 0 0 0 0 0 ICS951411 Integrated Circuit Systems, Inc. SMBus Table: Device ID Register Byte 6 Pin # Name Bit 7 DevID 7 Bit 6 DevID 6 Bit 5 DevID 5 Bit 4 DevID 4 Bit 3 DevID 3 Bit 2 DevID 2 Bit 1 DevID 1 Bit 0 DevID 0 SMBus Table: Vendor ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0 SMBus Table: Byte Count Register Byte 8 Pin # Name Bit 7 BC7 Bit 6 BC6 Bit 5 BC5 Bit 4 BC4 Bit 3 BC3 Bit 2 BC2 Bit 1 BC1 Bit 0 BC0 Control Function Device ID MSB Device ID 6 Device ID 5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID LSB Type R R R R R R R R 0 - 1 - PWD 0 0 0 1 0 0 1 1 Control Function Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 Revision ID Starts at 0 hex for A revsion. VENDOR ID (0001 = ICS) Control Function Type 0 1 RW RW RW Writing to this register will Byte Count Programming RW configure how many bytes b(7:0) RW will be read back, default RW is 9 bytes. RW RW Bytes 9 through 21 are reserved Test Clarification Table Comments 1. Power-up w/ TEST_SEL/REF2 > 2.0V to enter test mode. 2. Cycle power to disable test mode 0891E—03/07/05 10 HW TEST_SEL/REF2 HW PIN <0.8V >2.0V OUTPUT NORMAL HI-Z PWD 0 0 0 0 1 0 0 1 ICS951411 Integrated Circuit Systems, Inc. Absolute Max Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V ° C °C °C 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage Input Low Voltage Input High Current VIH VIL IIH 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 2 VSS - 0.3 -5 VIH_FS 3.3 V +/-5% 0.7 VSS - 0.3 TYP MAX VDD + 0.3 UNITS Notes V V uA 1 1 1 -5 uA 1 -200 uA 1 VDD + 0.3 V 1 0.35 V 1 400 70 12 7 5 6 5 mA mA mA MHz nH pF pF pF 1 1 1 3 1 1 1 1 1.8 ms 1,2 33 kHz 1 300 us 1 Tfall_Pd# 5 Trise_Pd# 5 VDD 2.7 5.5 SMBus Voltage @ IPULLUP VOL 0.4 Low-level Output Voltage Current sinking at IPULLUP 4 VOL = 0.4 V (Max VIL - 0.15) to SCLK/SDATA TRI2C 1000 (Min VIH + 0.15) Clock/Data Rise Time (Min VIH + 0.15) to SCLK/SDATA TFI2C 300 (Max VIL - 0.15) Clock/Data Fall Time 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. ns ns V V 1 2 1 1 mA 1 ns 1 ns 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current VIL_FS 3.3 V +/-5% IDD3.3OP Powerdown Current IDD3.3PD Input Frequency Pin Inductance Fi Lpin CIN COUT CINX all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Input Capacitance Clk Stabilization Modulation Frequency Tdrive_PD# TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of 0891E—03/07/05 11 0.8 5 14.31818 30 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES Ω 1 850 1,3 mV -150 150 1150 -300 250 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 1,3 550 mV 1 1 1 140 mV 1 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 700 700 125 125 mV Measurement from differential 45 55 % wavefrom CPU(1:0), VT = 50% tsk3 100 ps Skew CPU(1:0) to CPU2_ITP, tsk4 150 ps Skew VT = 50% Measurement from differential tjcyc-cyc 125 ps Jitter, Cycle to cycle wavefrom (CPU2_ITP) Measurement from differential tjcyc-cyc 85 ps Jitter, Cycle to cycle wavefrom, (CPU(1:0)) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 0891E—03/07/05 12 1 1 1 1 1 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Zo VO = Vx 3000 VHigh VLow Vovs Vuds Statistical measurement on single ended signal Measurement on single ended signal using 660 -150 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time tr Fall Time tf Rise Time Variation Fall Time Variation d-tr d-tf TYP MAX Ω 850 150 1150 -300 250 Variation of crossing over all edges see Tperiod min-max -300 values 100.00MHz nominal 9.9970 9.9970 100.00MHz spread 100.00MHz 9.8720 nominal/spread VOL = 0.175V, 175 VOH = 0.525V VOH = 0.525V 175 VOL = 0.175V UNITS Notes mV mV 1 1,3 1,3 1 1 350 550 mV 1 12 140 mV 1 300 ppm 1,2 10.0030 10.0533 ns ns 2 2 ns 1,2 700 ps 1 700 ps 1 125 125 ps ps 1 1 30 30 Measurement from 45 55 % 1 differential wavefrom VT = 50% tsk3 250 ps 1 Skew Measurement from tjcyc-cyc Jitter, Cycle to cycle 125 ps 1 differential wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 0891E—03/07/05 13 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm Clock period Tperiod Output High Voltage Output Low Voltage VOH VOL see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V -300 29.9910 29.9910 2.4 Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 1 1 0.5 0.5 45 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter 1 2 tr1 tf1 dt1 tjcyc-cyc TYP MAX 300 30.0090 30.1598 0.55 -33 -33 30 38 4 4 2 2 55 250 UNITS Notes ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps 1,2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Electrical Characteristics - 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL see Tperiod min-max values 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH@ MAX = 3.135 V VOL @MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V -100 20.8313 2.4 Output High Current Output Low Current IOH IOL Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle tr1 tf1 dt1 tjcyc-cyc 1 TYP MAX 100 20.8354 38 2 2 ppm ns V V mA mA mA mA V/ns V/ns 1,2 2 1 1 1 1 1 1 1 1 2 2 55 175 ns ns % ps 1 1 1 1 0.55 -33 -33 30 1 1 1 1 45 UNITS Notes Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 2 0891E—03/07/05 14 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL Output High Current IOH Output Low Current IOL Rise Time Fall Time Skew Duty Cycle Jitter tr1 tf1 tsk1 dt1 tjcyc-cyc CONDITIONS MIN see Tperiod min-max values -300 14.318MHz output nominal 69.8270 IOH = -1 mA 2.4 IOL = 1 mA VOH @MIN = 1.0 V, -29 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL 29 @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V VT = 1.5 V 45 VT = 1.5 V 1 TYP MAX 300 69.8550 UNITS Notes 0.4 ppm ns V V 1 1 1 1 -23 mA 1 27 mA 1 2 2 500 55 1000 ns ns ps % ps 1 1,2 2 1,2 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0891E—03/07/05 15 ICS951411 Integrated Circuit Systems, Inc. SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non -coupled 50 ohm trace. 0.5 max L2 length, Route as non -coupled 50 ohm trace. 0.2 max L3 length, Route as non -coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coup led stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Rout e as coupled stripline 100 ohm differential trace. L1 Unit inch inch inch ohm ohm Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Dimension or Value 2 min to 16 max Unit inch 2 1.8 min to 14.4 max inch 2 Dimension or Value 0.25 to 14 max Unit inch 3 0.225 min to 12.6 max inch 3 Figure L2 L4 Rs L1’ L4’ L2’ Rs Fig.1 Figure Rt HSCL Output Buffer Rt L3’ L1 PCI Ex REF_CLK Test Load L3 L2 L4 Rs L1’ Fig.2 L4’ L2’ Rs Rt HSCL Output Buffer L3’ L1 Rt PCI Ex Board Down Device REF_CLK Input L3 L2 L4 Rs L4’ L1’ L2’ Rs Fig.3 Rt HSCL Output Buffer L3’ 0891E—03/07/05 16 Rt L3 PCI Ex Add In Board REF_CLK Input ICS951411 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins The I/O pins designated by (input/output) on the ICS951416 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0891E—03/07/05 17 ICS951411 Integrated Circuit Systems, Inc. c N 56-Lead, 300 mil Body, 25 mil, SSOP L E1 INDEX AREA E 1 2 α h x 45° D A A1 A A1 b c D E E1 e h L N a In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS -C- e SYMBOL SEATING PLANE b .10 (.004) C N 56 D mm. MIN 18.31 D (inch) MAX 18.55 MIN .720 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS951411yFLFT Example: ICS XXXX y F LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0891E—03/07/05 18 MAX .730 ICS951411 Integrated Circuit Systems, Inc. c N L E1 INDEX AREA E 1 2 a D A A2 A1 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 -Ce b SEATING PLANE VARIATIONS N aaa C 56 D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 Reference Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information ICS951411yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0891E—03/07/05 19 MAX .555