TECHNICAL DATA IN5851 PULSE DIALER WITH REDIAL The IN5851 is a monolithic CMOS integrated circuit which uses an inexpensive RC oscillator for its frequency reference and provides all the features required for implementing a pulse dialer with 32 digit redial. • Wide operating voltage range (2.0~6.0V) • Low power dissipation • Use either a standard 2 of 7 matrix keyboard with negative true common or the inexpensive form A-type keyboard • Make/Break ratio can be selected • Redial with * or # • Continuous MUTE • Power up clear circuitry on chip • 10 pps/20 pps can be selected LOGIC DIAGRAM ORDERING INFORMATION IN5851N Plastic TA = -20° to 70° C PIN ASSIGNMENT PIN 1 = VCC PIN 6 = GND 1 IN5851N PIN DESCRIPTION NAME PIN VCC 1 DESCRIPTION Positive supply pin. The voltage on this pin is measured relative to Pin 6 and is supplied from a 150µA current source. This voltage should be regulated to less than 6.0 volts using on external form or regulation. VREF 2 The VREF output provides reference voltage that tracks internal parameters of the IN5851N. VREF provides a negative voltage reference to the VCC supply. Its magnitude will be approximately 0.6 volt higher than the minimum operating voltage of each particular IN5851N. . The typical application would be to connect the VREF pin to the GND pin (Pin 6). The supply to the VCC pin (Pin 1) should then be regulated to 150µA (IOP max). with this amount of supply current, operation of the IN5851N is guaranteed. The internal circuit of the VREF function is shown in Figure 1 with its associated I-V characteristic ___ _____ 3,4,5,13, Row1-Row4, 14,15,16 Col1-Col4 Keyboard inputs. The IN5851N incorporates an innovative keyboard scheme that allows either the standard 2-of-7 keyboard with negative common or the inexpensive single contact (form A) keyboard to be used. A valid key entry is defined by either a single row being connected to a single column or GND being simultaneously presented to both a single row and column. When in the on-hook mode, the row and column inputs are held high and no keyboard inputs are accepted. When off-hook, the keyboard is completely static until the initial valid key input is sensed. The oscillator is then enabled and the rows and columns are scanned alternately (pulled high, then low) to verify the varied input. The input must remain valid for 10msec of debounce time to be accepted. Form A type keyboard 2 of 7 keyboard GND 2 6 Negative supply 2 of 7 keyboard (negative common) Electronic input IN5851 pin is connected to the common part in general applications. RC1-RC3 7,8,9 Oscillator The IN5851N contains on-chip inverters to provide oscillator which will operate with a minimum external components. Following figure shows the on-chip configuration with the necessary external components. Optimum stability occurs with the ration K=RS/R equal to 10 The oscillator period is given by: T=RC(1.386+(3.5KCS)/C-(2K/(K+1)) in (K/(1.5K + 0.5)) Where CS is the stray capacitance on Pin 7. Accuracy and stability will be enhanced with this capacitance minimized. PPS 10 10/20pps Select Connecting this pin to GND (pin 6) will select an output pulse rate of 10pps. Connecting the pin VCC (pin 1) will select an output pulse rate of 20pps. M/B 11 Make/break Select The Make/Break pin controls the Make/Break ratio of the pulse output. The make/Break ratio is controlled by connection VCC or GND to this pin as shown in the following table. ____ Mute 12 Input Make Break VCC (Pin1) 33.4% 66.6% GND(PIn 6) 40% 60% Mute Output The mute output is an open-drain N-Channel transistor designed to drive external bipolar transistor. This circuitry is usually used to mute the receiver during outpulsing. As shown in Fig. 2 the IN5851N mute output turns on (pulls to the VGND-supply) at the beginning of the predigital pause and turns off (goes to an open circuit) following the last break. The delay from the end of the last break until the mute output turns off is mute overlap and is specified as tMO. OH 17 ON-HOOK/TEST This pin detects the state of the hook switch contact “OFF HOOK” corresponds to VSS condition. ÖN HOOK”corresponds to VDD condition. When outpulsing in this mode, which can be up to 300msec, is completed, the circuit is deactivated and will require current only necessary to sustain the memory and power-up-clear detect circuitry (refer to the electrical specifications). 3 IN5851N Upon retuning off-hook, a negative transistion on the mute output will insure the speech network is connected to the line. If the first key entry is either a * or #, the number sequence stored on-chip will be outpulsed. Any other valid key entries will clear the memory and outpulse the new number sequence. ______ PULSE 18 Pulse Output The Pulse output is an open drain N-channel transistor designed to drive external bipolar transistor. These transistor would normally be used to pulse the telephone line by disconnecting and connecting the network. The IN5851N pulse output is an open circuit during make and pulls to the GND supply during break. MAXIMUM RATINGS* Symbol VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) PD Tstg * Parameter Power Dissipation in Still Air Storage Temperature Value Unit -0.3 to +6.2 V -0.3 to VCC +0.3 V 500 mW -40 to +125 °C ** Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating: -10 mW/°C from 65°C to 70°C. 4 IN5851 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) TA Operating Temperature Min Max Unit 2.0 6.0 V 0 VCC V -20 +70 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND, VCC = 2.0 V to 6.0V, TA = -20 to +70°C, FOSC=2.4KHz) Guaranteed Limits Symbol Parameter Test Conditions Min 0.8VCC Typ Max Unit VCC V 0.2VCC V VIH Input High Voltage VIL Input Low Voltage 0 VDR Minimum Memory Retention Voltage 1.0 IOL Output Leakage Current VCC=6.0V , MUTE,PULSE=6.0V IOL1 Minimum Output current ______ (MUTE,PULSE) VO=0.8V,VCC=2.5V 0.5 mA IOL2 Minimum Output current ______ (MUTE,PULSE) VO=0.8V,VCC=3.5V 1.7 mA IOD Operating Current All output under no load, VCC=2.0V ISD Maximum Standby Current VCC=2.5V VIH=2.5V IREF Minimum Reference Current VCC=6.0V V 1 1 µA 150 µA 1 µA µA 5 IN5851N AC ELECTRICAL CHARACTERISTICS (FOSC= 2.4 KHz, VCC=2.0 to 6.0 V, TA=-20 to +70°C ) Symbol TKD TOH TIDR ∆f TMO TPDP TDP M/B 6 Parameter Minimum Valid Key Entry Time On Hook Time Required to Clear Memory (Figure 2) Inter Digital Pause (Figure 2) Frequency Sability Recovery Time, MUTE to PULSE (Figure 2) Maximum Predigital Pause (Figure 2) Maximum Delay Time, Key Input to PULSE (Figure 2) Make/Break Ratio Test Conditions Min. 20 Guaranteed Limit Typ. Max Unit mS 300 mS 800 mS ±10 % 800 mS 1/2 2/3 30 mS 50 mS M/B=VCC M/B=GND IN5851 TIMING DIAGRAMM Figure 2 7