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SLES081A − JUNE 2003 – REVISED MAY 2004
FEATURES
D Multiple Functions:
D On-Chip USB Interface:
− With Full-Speed Transceivers
− Fully Compliant With USB 1.1
Specification
− Certified by USB-IF
− Partially Programmable Descriptors
− Adaptive Isochronous Transfer for
Playback
− Bus-Powered or Self-Powered Operation
D Sampling Rate: 32, 44.1, 48 kHz
D On-Chip Clock Generator:
Single 12-MHz Clock Source
D Single Power Supply:
− Bus-Powered: 5 V, Typical (VBUS)
− Self-Powered: 3.3 V, Typical
D 16-Bit Delta-Sigma Stereo DAC
− Analog Performance at 5 V (Bus),
3.3 V (Self):
− THD+N: 0.006% (RL > 10 kΩ,
Self-Powered)
− THD+N: 0.025% (RL = 32 Ω)
− SNR: 98 dB
− Dynamic Range: 98 dB
− PO: 12 mW (RL = 32 Ω)
− Oversampling Digital Filter
− Pass-Band Ripple: ±0.04 dB
− Stop-Band Attenuation: –50 dB
− Single-Ended Voltage Output
− Analog LPF Included
D
− Up to Eight Human Interface Device (HID)
Interfaces (Depending on Model and
Settings)
− Suspend Flag
− S/PDIF Out With SCMS
− External ROM Interface (PCM2704/6)
− Serial Programming Interface (PCM2705/7)
− I2S Interface (Selectable on PCM2706/7)
Package:
− Lead-Free Product
− 28-Pin SSOP (PCM2704/5)
− 32-Pin TQFP (PCM2706/7)
APPLICATIONS
D USB Headphones
D USB Audio Speaker
D USB CRT/LCD Monitor
D USB Audio Interface Box
D USB-Featured Consumer Audio Product
DESCRIPTION
The PCM2704/5/6/7 is TI’s single-chip USB stereo audio
DAC with USB 1.1 compliant full-speed protocol controller
and S/PDIF. The USB-protocol controller works with no
software code, but USB descriptors can be modified in
some parts (for example, vendor ID/product ID) through
the use of an external ROM (PCM2704/6) SPI
(PCM2705/7) or on request.† The PCM2704/5/6/7
employs SpAct architecture, TI’s unique system that
recovers the audio clock from USB packet data. On-chip
analog PLLs with SpAct enable playback with low clock
jitter.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The modification of the USB descriptor through external ROM or SPI must comply with USB-IF guidelines, and the vendor ID must be your own
ID as assigned by the USB-IF. The descriptor also can be modified by changing a mask; please contact your representative for details.
SpAct is a trademark of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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SLES081A − JUNE 2003 – REVISED MAY 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE CODE
OPERATING
TEMPERATURE
RANGE
PACKAGE
MARKING
PCM2704DB
SSOP-28
28DB
–25°C to 85°C
PCM2704
PCM2705DB
SSOP-28
28DB
–25°C to 85°C
PCM2705
PCM2706PJT
TQFP-32
32PJT
–25°C to 85°C
PCM2706
PCM2707PJT
TQFP-32
32PJT
–25°C to 85°C
PCM2707
ORDERING
NUMBER
TRANSPORT
MEDIA
PCM2704DB
Tube
PCM2704DBR
Tape and reel
PCM2705DB
Tube
PCM2705DBR
Tape and reel
PCM2706PJT
Tray
PCM2706PJTR
Tape and reel
PCM2707PJT
Tray
PCM2707PJTR
Tape and reel
(1) For the most current specification and package information, refer to our Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
Supply voltage
Supply voltage differences
Ground voltage differences
VBUS
VCCP, VCCL, VCCR, VDD
VCCP, VCCL, VCCR, VDD
PGND, AGNDL, AGNDR, DGND, ZGND
HOST
Digital input voltage
D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT,
PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3
–0.3 V to 6.5 V
–0.3 V to 4 V
±0.1 V
±0.1 V
–0.3 V to 6.5 V
–0.3 V to (VDD + 0.3) V < 4 V
VCOM
VOUTR
–0.3 V to (VCCP + 0.3) V < 4 V
VOUTL
Input current (any pins except supplies)
–0.3 V to (VCCL + 0.3) V < 4 V
Analog input voltage
–0.3 V to (VCCR + 0.3) V < 4 V
±10 mA
Ambient temperature under bias
–40°C to 125°C
Storage temperature
–55°C to 150°C
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
150°C
260°C, 5 s
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLES081A − JUNE 2003 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data, unless otherwise noted
PARAMETER
TEST CONDITIONS
PCM2704DB, PCM2705DB,
PCM2706PJT, PCM2707PJT
MIN
TYP
UNIT
MAX
DIGITAL INPUT/OUTPUT
Apply USB revision 1.1,
full-speed
Host interface
Audio data format
USB isochronous data format
INPUT LOGIC
VIH
VIL
VIH(1)
Input logic level
VIL(1)
IIH(2)
IIL(2)
IIH
3.3
0.8
2
5.5
–0.3
Input logic current
0.8
±10
VIN = 3.3 V
VIN = 0 V
Output logic level
VOL
CLOCK FREQUENCY
65
100
µA
±10
IOH = –2 mA
IOL = 2 mA
2.8
IOH = –2 mA
IOL = 2 mA
2.4
Input clock frequency, XTI
VDC
±10
VIN = 3.3 V
VIN = 0 V
IIL
OUTPUT LOGIC
VOH(3)
VOL(3)
VOH
2
–0.3
0.3
VDC
0.4
11.994
fs
Sampling frequency
DAC CHARACTERISTICS
12
12.006
32, 44.1, 48
Resolution
Audio data channel
MHz
kHz
16
Bits
1, 2
Channel
DC ACCURACY
Gain mismatch, channel-to-channel
±2
±8
% of FSR
Gain error
±2
±8
% of FSR
Bipolar zero error
±3
±6
% of FSR
0.006%
0.01%
0.012%
0.02%
DYNAMIC PERFORMANCE(4)
THD+N,
VOUT = 0 dB
Line(5)
RL > 10 kΩ, self-powered
RL > 10 kΩ, bus-powered
Headphone
RL = 32 Ω,
self-/bus-powered
0.025%
THD+N, VOUT = –60 dB
2%
Dynamic range
EIAJ, A-weighted
90
98
dB
S/N ratio
EIAJ, A-weighted
90
98
dB
60
70
Channel separation
dB
(1) HOST
(2) D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI
(3) FUNC0, FUNC1, FUNC2
(4) fIN = 1 kHz, using the System Twot Cascade audio measurement system by Audio Precisiont in the RMS mode with a 20-kHz LPF and 400-Hz
HPF.
(5) THD+N performance varies slightly depending on the effective output load, including dummy load R7, R8 in Figure 31.
System Two and Audio Precision are trademarks of Audio Precision, Inc.
3
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SLES081A − JUNE 2003 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data, unless otherwise noted
PARAMETER
TEST CONDITIONS
PCM2704DB, PCM2705DB,
PCM2706PJT, PCM2707PJT
MIN
TYP
UNIT
MAX
ANALOG OUTPUT
Output voltage
0.55 VCCL, 0.55 VCCR
Center voltage
0.5 VCCP
Load impedance
Line
AC coupling
10
Headphone
AC coupling
16
LPF frequency
response
Vp-p
V
kΩ
32
Ω
–3 dB
140
kHz
f = 20 kHz
–0.1
dB
DIGITAL FILTER PERFORMANCE
Pass band
0.454 fs
Stop band
0.546 fs
Hz
±0.04
Pass-band ripple
Stop-band attenuation
–50
Delay time
Hz
dB
dB
20/fs
s
POWER SUPPLY REQUIREMENTS
VBUS
VCCP, VCCL, VCCR, VDD
Bus-powered
4.35
5
5.25
Self-powered
3
3.3
3.6
Line
DAC operation
23
30
Headphone
35
46
Line/headphone
DAC operation (RL = 32 Ω)
Suspend mode (1)
150
190
Line
DAC operation
76
108
Headphone
116
166
Line/headphone
DAC operation (RL = 32 Ω)
Suspend mode (1)
495
684
Line
DAC operation
115
158
Power dissipation
(bus-powered)
Headphone
175
242
Line/headphone
DAC operation (RL = 32 Ω)
Suspend mode (1)
750
998
µW
Internal power
supply voltage (2)
VCCP, VCCL, VCCR, VDD
Bus-powered
3.35
3.5
VDC
85
°C
Voltage range
Supply current
Power dissipation
(self-powered)
3.2
VDC
mA
µA
mW
µW
mW
TEMPERATURE RANGE
Operating temperature
θJA
Thermal resistance
–25
28-pin SSOP (PCM2704/5)
100
32-pin TQFP (PCM2706/7)
80
(1) Under USB suspend state.
(2) VDD, VCCP, VCCL, VCCR. These pins work as output pins of internal power supply for bus-powered operation.
4
°C/W
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SLES081A − JUNE 2003 – REVISED MAY 2004
PIN ASSIGNMENTS
PCM2704/PCM2705
DB PACKAGE
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTI
SSPND
TEST0
TEST1
HID2/MD
HID1/MC
HID0/MS
HOST
VCCP
PGND
VCOM
AGNDR
VCCR
VOUTR
VBUS
D+
D–
VDD
DGND
FUNC1
FUNC2
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24 23 22 21 20 19 18 17
ZGND
AGNDL
VCCL
VOUTL
VOUTR
VCCR
AGNDR
VCOM
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3
4
5 6 7
PSEL
DT
CK
XTO
XTI
SSPND
TEST
FSEL
8
PGND
VCCP
HOST
FUNC3
FUNC0
HID0/MS
HID1/MC
HID2/MD
XTO
CK
DT
PSEL
DOUT
DGND
VDD
D–
D+
VBUS
ZGND
AGNDL
VCCL
VOUTL
PCM2706/PCM2707
PJT PACKAGE
(TOP VIEW)
5
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SLES081A − JUNE 2003 – REVISED MAY 2004
Terminal Functions (PCM2704DB/PCM2705DB)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGNDL
12
—
Analog ground for headphone amplifier of L-channel
AGNDR
17
—
Analog ground for headphone amplifier of R-channel
CK
2
O
D+
9
I/O
Clock output for external ROM (PCM2704). Must be left open (PCM2705).
USB differential input/output plus (1)
D–
8
I/O
USB differential input/output minus (1)
DGND
6
—
Digital ground
DOUT
5
O
S/PDIF output
DT
3
I/O
HID0/MS
22
I
Data input/output for external ROM(PCM 2704). Must be left open with pullup resistor (PCM2705). (1)
HID key state input (mute), active HIGH (PCM2704). MS input (PCM2705). (3)
HID1/MC
23
I
HID key state input (volume up), active HIGH (PCM2704). MC input (PCM2705). (3)
HID2/MD
24
I
HID key state input (volume down), active HIGH (PCM2704). MD input (PCM2705). (3)
HOST
21
I
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation (LOW: 100 mA, HIGH: 500 mA). (2)
PGND
19
—
PSEL
4
I
Power source select. (LOW: self-power, HIGH: bus-power) (1)
SSPND
27
O
TEST0
26
I
Suspend flag, active LOW (LOW: suspend, HIGH: operational)
Test pin. Must be set HIGH (1)
TEST1
25
I
Test pin. Must be set HIGH (1)
VBUS
VCCL
10
—
13
—
Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
Analog power supply for headphone amplifier of L-channel (4)
VCCP
VCCR
20
—
Analog power supply for DAC, OSC and PLL (4)
16
—
Analog power supply for headphone amplifier of R-channel (4)
VCOM
VDD
18
—
7
—
Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
Digital power supply (4)
VOUTL
VOUTR
14
O
DAC analog output for L-channel
15
O
XTI
28
I
DAC analog output for R-channel
Crystal oscillator input (1)
XTO
1
O
Crystal oscillator output
Analog ground for DAC, OSC and PLL
ZGND
11
—
Ground for internal regulator
(1) LV-TTL level
(2) LV-TTL level, 5-V tolerant
(3) LV-TTL level with internal pulldown
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
6
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SLES081A − JUNE 2003 – REVISED MAY 2004
Terminal Functions (PCM2706PJT/PCM2707PJT)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGNDL
26
—
Analog ground for headphone amplifier of L-channel
AGNDR
31
—
Analog ground for headphone amplifier of R-channel
CK
14
O
D+
23
I/O
Clock output for external ROM (PCM2706). Must be left open (PCM2707).
USB differential input/output plus (1)
D–
22
I/O
USB differential input/output minus (1)
DGND
20
—
Digital ground
DOUT
17
O
S/PDIF output / I2S data output
DT
15
I/O
FSEL
9
I
Data input/output for external ROM (PCM2706). Must be left open with pullup resistor (PCM2707). (1)
Function select (LOW: I2S DATA output, HIGH: S/PDIF output) (1)
FUNC0
5
I/O
FUNC1
19
I/O
FUNC2
18
I/O
FUNC3
4
I
HID key state input (stop), active HIGH (FSEL = 1). I2S system clock output (FSEL = 0). (3)
HID key state input (play/pause), active HIGH (FSEL = 1). I2S data input (FSEL = 0). (3)
HID0/MS
6
I
HID key state input (mute), active HIGH (PCM2706). MS input (PCM2707)(3)
HID1/MC
7
I
HID2/MD
8
I
HID key state input (volume up), active HIGH (PCM2706). MC input (PCM2707)(3)
HID key state input (volume down), active HIGH (PCM2706)/MD input (PCM2707)(3)
HOST
3
I
PGND
1
—
PSEL
16
I
Power source select. (LOW: self-power, HIGH: bus-power) (1)
SSPND
11
O
TEST
10
I
Suspend flag, active LOW (LOW: suspend, HIGH: operational)
Test pin. Must be set HIGH (1)
VBUS
VCCL
24
—
27
—
Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
Analog power supply for headphone amplifier of L-channel (4)
VCCP
VCCR
2
—
Analog power supply for DAC, OSC and PLL (4)
30
—
Analog power supply for headphone amplifier of R-channel (4)
VCOM
VDD
32
—
21
—
Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
Digital power supply (4)
VOUTL
VOUTR
28
O
DAC analog output for L-channel
29
O
XTI
12
I
DAC analog output for R-channel
Crystal oscillator input (1)
XTO
13
O
Crystal oscillator output
HID key state input (next track), active HIGH (FSEL = 1). I2S LR clock output (FSEL = 0). (3)
HID key state input (previous track), active HIGH (FSEL = 1). I2S bit clock output(FSEL = 0). (3)
Host detection during self-powered operation. (connect to VBUS). Max power select during bus-powered
operation. (LOW: 100 mA, HIGH: 500 mA). (2)
Analog ground for DAC, OSC and PLL
ZGND
25
—
Ground for internal regulator
(1) LV-TTL level
(2) LV-TTL level, 5-V tolerant
(3) LV-TTL level with internal pulldown
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
7
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SLES081A − JUNE 2003 – REVISED MAY 2004
BLOCK DIAGRAM (PCM2704DB/PCM2705DB)
VCCP
VCCL
VCCR
VDD
PGND
AGNDL
AGNDR
DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
VBUS
VOUTL
USB
Protocol
Controller
DAC
Control
Endpoint
VOUTR
D+
D–
S/PDIF Encoder
DOUT
FIFO
ISO-Out
Endpoint
HID
Endpoint
PSEL
TEST0
TEST1
PLL (×8)
XTI
12 MHz XTO
† Applies to PCM2704DB
‡ Applies to PCM2705DB
8
XCVR
Analog
PLL
USB SIE
VCOM
96 MHz
Tracker
(SpAct)
EEPROM
Interface†
SPI
Interface‡
CK
DT
HOST
HID0/MS
HID1/MC
HID2/MD
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SLES081A − JUNE 2003 – REVISED MAY 2004
BLOCK DIAGRAM (PCM2706PJT/PCM2707PJT)
VCCP
VCCL
VCCR
VDD
PGND
AGNDL
AGNDR
DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
VBUS
VOUTL
USB
Protocol
Controller
DAC
Control
Endpoint
VOUTR
XCVR
Analog
PLL
USB SIE
VCOM
D+
D–
S/PDIF
Encoder
DOUT
DOUT
LRCK
BCK
SYSCK
DIN
FSEL
FUNC0
FUNC1
FUNC2
FUNC3
I2S I/F
FIFO
ISO-Out
Endpoint
EEPROM
Interface†
CK
DT
HOST
HID3: Next Trackt†
HID4: Previous Trackt†
HID5: Stop†
HID
Endpoint
HID6: Play/Pause†
SPI
Interface‡
HID0/MS
HID1/MC
HID2/MD
PSEL
TEST
PLL (×8)
XTI 12 MHz
96 MHz
Tracker
(SpAct)
XTO
† Applies to PCM2706PJT
‡ Applies to PCM2707PJT
9
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SLES081A − JUNE 2003 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
DAC DIGITAL INTERPOLATION FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0.05
0
0.04
−20
0.03
0.02
Amplitude – dB
Amplitude – dB
−40
−60
−80
0.01
0.00
−0.01
−0.02
−100
−0.03
−120
−0.04
−0.05
0.0
−140
0
1
2
3
4
0.1
0.2
0.3
0.4
f – Frequency [× fS]
f – Frequency [× fS]
Figure 1. Frequency Response
Figure 2. Pass-Band Ripple
0.5
DAC ANALOG LOW-PASS FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
FREQUENCY
0.0
0
−0.5
−20
Amplitude – dB
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
−1.0
−1.5
−2.0
0.01
−40
−60
−80
0.1
1
10
100
1
10
100
f – Frequency – kHz
Figure 3. Pass-Band Characteristics
Figure 4. Stop-Band Characteristics
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data, unless otherwise noted.
10
1k
f – Frequency – kHz
10k
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SLES081A − JUNE 2003 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
0.05
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
0.05
Bus-Powered
VOUT = 0 dB
0.04
0.03
32 Ω
0.02
10 kΩ
0.01
0.00
−50
−25
0
25
50
75
0.03
32 Ω
0.02
0.01
10 kΩ
−25
0
25
50
75
100
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 5
Figure 6
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
0.05
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
0.04
0.00
−50
100
0.05
Bus-Powered
VOUT = 0 dB
0.04
0.03
32 Ω
0.02
10 kΩ
0.01
0.00
4.0
Self-Powered
VOUT = 0 dB
4.5
5.0
VCC – Supply Voltage – V
Figure 7
5.5
Self-Powered
VOUT = 0 dB
0.04
0.03
32 Ω
0.02
0.01
0.00
3.0
10 kΩ
3.1
3.2
3.3
3.4
3.5
3.6
VCC – Supply Voltage – V
Figure 8
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data, unless otherwise noted.
11
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SLES081A − JUNE 2003 – REVISED MAY 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
SAMPLING FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
SAMPLING FREQUENCY
0.05
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
0.05
Bus-Powered
VOUT = 0 dB
0.04
32 Ω
0.03
0.02
10 kΩ
0.01
0.00
Self-Powered
VOUT = 0 dB
0.04
0.03
32 Ω
0.02
0.01
10 kΩ
0.00
30
35
40
45
50
30
50
Figure 10
DYNAMIC RANGE and SNR
vs
FREE-AIR TEMPERATURE
DYNAMIC RANGE and SNR
vs
FREE-AIR TEMPERATURE
105
Self-Powered
Dynamic Range and SNR – dB
103
101
99
Dynamic Range
97
103
101
99
Dynamic Range
97
SNR
SNR
−25
0
25
50
75
100
95
−50
−25
0
25
50
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 11
Figure 12
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data, unless otherwise noted.
12
45
Figure 9
Bus-Powered
95
−50
40
fS – Sampling Frequency – kHz
105
Dynamic Range and SNR – dB
35
fS – Sampling Frequency – kHz
75
100
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SLES081A − JUNE 2003 – REVISED MAY 2004
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
105
105
Self-Powered
103
Dynamic Range and SNR – dB
Dynamic Range and SNR – dB
Bus-Powered
101
99
Dynamic Range
SNR
97
95
4.0
4.5
5.0
103
101
99
Dynamic Range
SNR
97
95
3.0
5.5
3.2
3.3
3.4
3.5
VCC – Supply Voltage – V
Figure 13
Figure 14
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
3.6
105
105
Self-Powered
Bus-Powered
103
Dynamic Range and SNR – dB
Dynamic Range and SNR – dB
3.1
VCC – Supply Voltage – V
101
99
Dynamic Range
97
SNR
103
101
Dynamic Range
99
SNR
97
95
95
30
35
40
45
50
30
35
40
45
fS – Sampling Frequency – kHz
fS – Sampling Frequency – kHz
Figure 15
Figure 16
50
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data, unless otherwise noted.
13
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SLES081A − JUNE 2003 – REVISED MAY 2004
SUSPEND CURRENT
vs
FREE-AIR TEMPERATURE
200
200
150
150
Suspend Current – µA
Suspend Current – µA
SUSPEND CURRENT
vs
SUPPLY VOLTAGE
100
50
50
0
4.0
4.5
5.0
0
−50
5.5
−25
0
25
75
100
100
120
TA – Free-Air Temperature – °C
Figure 17
Figure 18
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
−20
−20
−40
−40
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
0
5
10
15
20
f – Frequency – kHz
Figure 19. Output Spectrum (–60 dB, N = 8192)
0
20
40
60
80
f – Frequency – kHz
Figure 20. Output Spectrum (–60 dB, N = 8192)
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data, unless otherwise noted.
14
50
VBUS – Supply Voltage – V
Amplitude – dB
Amplitude – dB
100
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SLES081A − JUNE 2003 – REVISED MAY 2004
DETAILED DESCRIPTION
CLOCK AND RESET
For both USB function and audio function, the PCM2704/5/6/7 requires a 12-MHz (±500 ppm) clock, which can be
generated by the built-in oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to XTI (pin 28 for PCM2704/5, pin 12 for PCM2706/7) and XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) with one large (1-MΩ) resistor and two small capacitors, the capacitance of which depends on the
specified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin 28 for
PCM2704/5, pin 12 for PCM2706/7). If an external clock is supplied, XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) must be left open. Because no clock disabling pin is provided, it is not recommended to use the external
clock supply. SSPND (pin 27 for PCM2704/5, pin 11 for PCM2706/7) is unable to use clock disabling.
The PCM2704/5/6/7 has an internal power-on reset circuit, and it works automatically when VDD (pin 7 for
PCM2704/5, pin 21 for PCM2706/7) exceeds 2 V typical (1.6 V–2.4 V), which is equivalent to VBUS (pin 10 for
PCM2704/5, pin 24 for PCM2706/7) exceeding 3 V typical for bus-powered applications. About 700 µs is required
until internal reset release.
OPERATION MODE SELECTION
The PCM2704/5/6/7 has the following mode-select pins.
Power Configuration Select/Host Detection
PSEL (pin 4 for PCM2704/5, pin 16 for PCM2706/7) is dedicated to selecting the power source. This selection affects
the configuration descriptor. While in bus-powered operation, maximum power consumption from the VBUS is
determined by HOST (pin 21 for PCM2704/5, pin 3 for PCM2706/7). For self-powered operation, HOST must be
connected to VBUS of the USB bus with a pulldown resistor to detect attach and detach. (To avoid excessive suspend
current, the pulldown should be a high-value resistor.)
Table 1. Power Configuration Select
PSEL
DESCRIPTION
0
Self-powered
1
Bus-powered
HOST
DESCRIPTION
0
Detached from USB (self-powered)/100 mA (bus-powered)
1
Attached to USB (self-powered)/500 mA (bus-powered)
Function Select (PCM2706/7)
FSEL (pin 9) determines the function of FUNC0–FUNC3 (pins 4, 5, 18, and 19) and DOUT (pin17). When the I2S
interface is required, FSEL must be set to LOW. Otherwise, FSEL must be set to HIGH.
Table 2. Function Select
FSEL
DOUT
FUNC0
FUNC1
FUNC2
FUNC3
0
Data out (I2S)
LRCK (I2S)
BCK (I2S)
SYSCK (I2S)
Stop (HID) (1)
Data in (I2S)
1
S/PDIF data
Next track (HID) (1)
(1) Valid on the PCM2706; no function assigned on the PCM2707.
Previous track (HID) (1)
Play/pause (HID) (1)
15
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SLES081A − JUNE 2003 – REVISED MAY 2004
USB INTERFACE
Control data and audio data are transferred to the PCM2704/5/6/7 via D+ (pin 9 for PCM2704/5, pin 23 for
PCM2706/7) and D– (pin 8 for PCM2704/5, pin 22 for PCM2706/7). D+ should be pulled up with a 1.5-kΩ (±5%)
resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup resistor
on D+ while VBUS of the USB port is inactive.
All data to/from the PCM2704/5/6/7 are transferred at full speed. The following information is provided in the device
descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704/6), SPI
(PCM2705/7), or internal mask ROM on request.
Table 3. Device Descriptor
USB revision
1.1 compliant
Device class
0x00 (device defined interface level)
Device subclass
0x00 (not specified)
Device protocol
0x00 (not specified)
Max packet size for endpoint 0
8 bytes
Vendor ID
0x08BB (default value, can be modified)
Product ID
0x2704/0x2705/0x2706/0x2707 (These values correspond to the model number, and the value can be
modified.)
Device release number
1.0 (0x0100)
Number of configurations
1
Vendor strings
“Burr-Brown from TI” (default value, can be modified)
Product strings
“USB Audio DAC” (default value, can be modified)
Serial number
Not supported
The following information is contained in the configuration descriptor. Some parts of the configuration descriptor can
be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or on request.
Table 4. Configuration Descriptor
Interface
Three interfaces
Power attribute
0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can be modified.)
Max power
0x0A, 0x32 or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on PSEL and HOST. This
value can be modified.)
The following information is contained in the string descriptor. Some parts of the string descriptor can be modified
through external ROM (PCM2704/6), SPI (PCM2705/7), or on request.
Table 5. String Descriptor
16
#0
0x0409
#1
Burr-Brown from TI (default value, can be modified)
#2
USB Audio DAC (default value, can be modified)
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Device Configuration
Figure 21 illustrates the USB audio function topology. The PCM2704/5/6/7 has three interfaces. Each interface is
enabled by some alternative settings.
Endpoint #0
Default
Endpoint
FU
Endpoint #2
(IF #1)
IT
TID1
OT
TID2
Audio Streaming
Interface
Analog Out
UID3
Standard Audio Control Interface (IF #0)
Endpoint #5
(IF #2)
HID Interface
PCM2704/5/6/7
Figure 21. USB Audio Function Topology
Interface #0 (Default/Control Interface)
Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes the
standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has three
terminals as follows.
D Input terminal (IT #1) for isochronous-out stream
D Output terminal (OT #2) for audio analog output
D Feature unit (FU #3) for DAC digital attenuator
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel audio
streams constructed of left and right channels. Output terminal #2 is defined as a speaker (terminal type 0x0301).
Feature unit #3 supports the following sound control features.
D Volume control
D Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB in
steps of 1 dB. Changes are made by incrementing or decrementing one step (1 dB) for every 1/fS time interval until
the volume level reaches the requested value. Each channel can be set to a separate value. The master volume
control is not supported. A request to the master volume is stalled and ignored. The built-in digital mute controller
can be manipulated by an audio-class-specific request. A master mute control request is acceptable. A mute control
request to an individual channel is stalled and ignored. The digital volume control does not affect the S/PDIF and I2S
outputs (PCM2706/7).
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SLES081A − JUNE 2003 – REVISED MAY 2004
Interface #1 (Isochronous-Out Interface)
Interface #1 is for the audio-streaming data-out interface. Interface #1 has the following three alternative settings.
Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
ALTERNATIVE
SETTING
DATA FORMAT
00
TRANSFER
MODE
SAMPLING RATE
(kHz)
Zero bandwidth
01
16-bit
stereo
2s complement (PCM)
Adaptive
32, 44.1, 48
02
16-bit
mono
2s complement (PCM)
Adaptive
32, 44.1, 48
Interface #2 (HID Interface)
Interface #2 is the interrupt-data-in interface. Interface #2 comprises the HID consumer control device. Alternative
setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration.
Basic HID operation
Interface #2 can report the following three key statuses for any model. These statuses can be set by the HID0–HID2
pins (PCM2704/6) or the SPI port (PCM2705/7).
D Mute (0xE2)
D Volume up (0xE9)
D Volume down (0xEA)
Extended HID operation (PCM2705/6/7)
By using the FUNC0–FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions can
be reported to the host.
D
D
D
D
Play/Pause (0xCD)
Stop (0xB7)
Previous (0xB6)
Next (0xB5)
Auxiliary HID status report (PCM2705/7)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI command
or external ROM. This definition must be described as on the report descriptor with a three-byte usage ID. AL A/V
Capture (0x0193) is assigned as the default for this status flag.
Endpoints
The PCM2704/5/6/7 has three endpoints as follows.
D Control endpoint (EP #0)
D Isochronous-out audio data-stream endpoint (EP #2)
D HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint is used to control all functions of the PCM2704/5/6/7
by standard USB request and USB audio-class-specific request from the host. The isochronous-out audio data
stream endpoint is an audio sink endpoint, which receives the PCM audio data. The isochronous-out audio data
stream endpoint accepts the adaptive transfer mode. The HID endpoint is an interrupt-in endpoint. The HID endpoint
reports HID status every 10 ms.
The HID endpoint is defined as a consumer control device. The HID function is designed as an independent endpoint
from the isochronous-out endpoint. This means that the effect of HID operation depends on host software. Typically,
the HID function is used to control the primary audio-out device.
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SLES081A − JUNE 2003 – REVISED MAY 2004
DAC
The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-fS second-order multibit noise
shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog low-pass
filter removes the high-frequency components of the noise-shaping signal. DAC outputs are provided through the
headphone amplifier VOUTL and VOUTR can provide 12 mW at 32 Ω as well as 1.8 Vp-p into a 10-kΩ load.
DIGITAL AUDIO INTERFACE – S/PDIF OUTPUT
The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host is encoded to S/PDIF output DOUT
as well as to DAC analog outputs VOUTL and VOUTR. Interface format and timing follows the IEC-60958 standard.
Monaural data is converted to the stereo format at the same data rate. S/PDIF output is not supported in the I2S I/F
enable mode.
Channel Status Information
The channel status information is fixed as consumer application, PCM mode, copyright, digital/digital converter. All
other bits are fixed as 0s except for the sample frequency, which is set automatically according to the data received
through the USB.
Copyright Management
Digital audio data output is always encoded as original with SCMS control. Only one generation of digital duplication
is allowed. The implementation of this feature is optional. Note that it is your responsibility for determining whether
to implement this feature in your product or not.
DIGITAL AUDIO INTERFACE – I2S INTERFACE OUTPUT (PCM2706/7)
The PCM2706 and PCM2707 can support the I2S interface, which is enabled by FSEL (pin 9). In the I2S interface
enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively. They
provide digital output/input data in the16-bit I2S format, which is also accepted by the internal DAC. I2S interface
format and timing are shown in Figure 22 and Figure 23.
1/fS
LRCK
R−Channel
L−Channel
BCK
(64 fS)
DOUT
1
2
3
MSB
DIN
1
2
3
MSB
14 15 16
1
LSB
14 15 16
LSB
2
3
MSB
1
2
3
MSB
14 15 16
1
2
1
2
LSB
14 15 16
LSB
Figure 22. Audio Data Input Format
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SLES081A − JUNE 2003 – REVISED MAY 2004
50% of VDD
LRCK (Output)
t(BCL)
t(BCH)
t(BL)
50% of VDD
BCK (Output)
t(BCY)
t(BD)
t(LD)
DOUT (Output)
50% of VDD
t(DS)
t(DH)
DIN (Input)
50% of VDD
SYMBOL
PARAMETER
MIN
MAX
UNIT
t(BCY)
t(BCH)
BCK pulse cycle time
300
ns
BCK pulse duration, HIGH
100
ns
t(BCL)
t(BL)
BCK pulse duration, LOW
100
LRCK delay time from BCK falling edge
–20
40
ns
t(BD)
t(LD)
DOUT delay time from BCK falling edge
–20
40
ns
DOUT delay time from LRCK edge
–20
40
ns
t(DS)
t(DH)
DIN setup time
20
ns
DIN hold time
20
ns
NOTE:
ns
Load capacitance is 20 pF.
Figure 23. Audio Interface Timing
EXTERNAL ROM DESCRIPTOR (PCM2704/6)
The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin 3 (for PCM2704)/pin 15
(for PCM2706) is assigned as DT (serial data) and pin 2 (for PCM2704)/pin 14 (for PCM2706) is assigned as CK
(serial clock) of the I2C interface when using the external ROM descriptor. Descriptor data is transferred from the
external ROM to the PCM2704/6 through the I2C interface the first time when the device activates after power-on
reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB command
request from the host to the device itself. The descriptor data, which can be in external ROM, are as follows. String
descriptors must be described in ANSI ASCII code (1 byte for each character). String descriptors are automatically
converted to unicode strings for transmission to the host. The device address of the external ROM is fixed as 0xA0.
The data must be stored from address 0x00 and must consist of 57 bytes as described in the following items. Read
operation is performed at a cycle of XTI/384 (approximately 30 kHz).
D
D
D
D
D
D
D
20
Vendor ID (2 bytes)
Product ID (2 bytes)
Device string (16 bytes in ANSI ASCII code)
Vendor string (32 bytes in ANSI ASCII code)
Maximum power (1 byte)
Power attribute (1 byte)
Auxiliary HID usage ID in report descriptor (3 bytes)
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SLES081A − JUNE 2003 – REVISED MAY 2004
DT
CK
S
1−7
8
9
1−8
9
1−8
9
9
Device Address
R/W
ACK
DATA
ACK
DATA
ACK
NACK
Start Condition
P
Stop Condition
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
NACK: Not Acknowledgement if 1
M
M
M
S
S
M
S
M
S
M
M
S
Device address
R/W
ACK
DATA
ACK
DATA
ACK
...
NACK
P
Read Operation
Figure 24. External ROM Read Operation
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SLES081A − JUNE 2003 – REVISED MAY 2004
TIMING DIAGRAM
Repeated Start
Start
Stop
t(D-HD)
t(BUF)
t(D-SU)
t(DT-R)
t(DT-F)
t(P-SU)
DT
t(CK-R)
t(RS-HD)
t(LOW)
CK
t(S-HD)
t(HI)
t(RS-SU)
t(CK-F)
SYMBOL
f(CK)
t(BUF)
t(LOW)
t(HI)
t(RS-SU)
t(S-HD)
t(RS-HD)
t(D-SU)
PARAMETER
MIN
CK clock frequency
UNIT
100
kHz
Bus free time between STOP and START condition
4.7
µs
Low period of the CK clock
4.7
µs
4
µs
Setup time for START/repeated START condition
4.7
µs
Hold time for START/repeated START condition
4
µs
High period of the CK clock
Data setup time
250
t(D-HD)
t(CK-R)
Data hold time
0
900
ns
Rise time of CK signal
20 + 0.1CB
1000
ns
t(CK-F)
t(DT-R)
Fall time of CK signal
20 + 0.1CB
1000
ns
Rise time of DT signal
20 + 0.1CB
1000
ns
t(DT-F)
t(P-SU)
CB
Fall time of DT signal
20 + 0.1CB
1000
VNH
Setup time for STOP condition
Capacitive load for DT and CK line
Noise margin at HIGH level for each connected device (including hysteresis)
ns
400
0.2 VDD
ns
µs
4
Figure 25. External ROM Read Interface Timing Requirements
22
MAX
pF
V
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SLES081A − JUNE 2003 – REVISED MAY 2004
EXTERNAL ROM EXAMPLE
Here is an example of external ROM data, with an explanation of the example following the data.
0xBB, 0x08, 0x04, 0x27,
0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x80,
0x7D,
0x0A, 0x93, 0x01
The data is stored beginning at address 0x00.
Vendor ID: 0x08BB
Device ID: 0x2704
Device string: Product strings. (16 bytes)
Vendor string: Vendor strings are placed here. (32 bytes, 31 visible characters are followed by 1 space)
bmAttribute: 0x80 (Bus-powered)
maxPower: 0x7D (250 mA)
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture)
SERIAL PROGRAMMING INTERFACE (PCM2705/7)
The PCM2705/7 supports the serial programming interface (SPI) to program the descriptor and to set the HID state.
Descriptor data is described in the External ROM Descriptor section.
t(MHH)
MS
50% of VDD
t(MLS)
t(MCL)
t(MCH)
t(MLH)
MC
50% of VDD
t(MCY)
LSB
MD
50% of VDD
t(MDS)
t(MDH)
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNITS
t(MCY)
t(MCL)
MC pulse cycle time
100
ns
MC low-level time
50
ns
t(MCH)
t(MHH)
MC high-level time
50
ns
MS high-level time
100
ns
t(MLS)
t(MLH)
MS falling edge to MC rising edge
20
ns
MS hold time
20
ns
t(MDH)
t(MDS)
MD hold time
15
ns
MD setup time
20
ns
Figure 26. SPI Timing Diagram
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SLES081A − JUNE 2003 – REVISED MAY 2004
(1) Single Write Operation
16-Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
16-Bits x N Frames
MS
MC
MD
MSB
LSB
MSB
LSB
MSB
LSB
N Frames
Figure 27. SPI Write Operation
SPI REGISTER (PCM2705/7)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
ST
0
ADDR
0
D0
D1
D2
D3
D4
D5
D6
D7
D[7:0]
Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7
Reports MUTE HID status to the host (active high)
D6
Reports volume-up HID status to the host (active high)
D5
Reports volume-down HID status to the host (active high)
D4
Reports next-track HID status to the host (active high)
D3
Reports previous-track HID status to the host (active high)
D2
Reports stop HID status to the host (active high)
D1
Reports play/pause HID status to the host (active high)
D0
Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data
ADDR
Starts write operation for internal descriptor reprogramming (active high)
456 bits of ROM data, (described in the External ROM Example section) must be provided when this bit is asserted.
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active when ST is set low.
ST
Determines the function of the lower 8-bit data as follows
0: HID status write
1: Descriptor ROM data write
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SLES081A − JUNE 2003 – REVISED MAY 2004
Functionality of ST and ADDR Bit Combinations
ST
ADDR
FUNCTION
0
0
HID status write
0
1
HID status write and descriptor ROM address read
1
0
Descriptor ROM data write
1
1
Reserved
USB HOST INTERFACE SEQUENCE
Power-On, Attach, and Playback Sequence
The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After a
connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While waiting for
the audio data (idle state), the analog output is set to bipolar zero (BPZ).
When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio data,
into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next subsequent
start-of-frame (SOF) packet.
VDD
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓ
ÓÓ
ÓÓ
Ó
ÓÓ
ÓÓ
ÓÓÓ
ÓÓ
ÓÓÓ
ÓÓÓ
ÓÓ
ÓÓ
ÓÓ
Ó
ÓÓ
ÓÓ
ÓÓÓ
ÓÓ
ÓÓÓ
ÓÓÓ
ÓÓ
ÓÓ
ÓÓ
Ó
ÓÓ
ÓÓ
ÓÓÓ
ÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
3.3 V
(Typ.)
2.0 V (Typ.)
0V
Bus Reset
1st Audio Data
Set Configuration
2nd Audio Data
Bus Idle
D+/D−
SOF
SSPND
SOF
SOF
BPZ
VOUTL
VOUTR
700 µs
Device Setup
1 ms
Internal Reset
Ready for Setup
Ready for Playback
Figure 28. Initial Sequence
25
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SLES081A − JUNE 2003 – REVISED MAY 2004
Play, Stop, and Detach Sequence
When host finishes or aborts the playback, the PCM2704/5/6/7 stops the playing after last audio data has played.
Suspend and Resume Sequence
The PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state for approximately
5 ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin 27 for PCM2704/5, pin 11 for PCM2706/7)
is asserted. The PCM2704/5/6/7 wakes up immediately when detecting the non-idle state on the USB bus.
VBUS
ÓÓÓÓÓ
ÓÓ
ÓÓÓ
ÓÓ
ÓÓÓ
Ó
Ó
ÓÓÓÓÓ
ÓÓÓÓÓ
ÓÓÓ Ó Ó
Audio Data
D+/D–
SOF
Audio Data
SOF
Last Audio Data
SOF
SOF
SOF
VOUTL
VOUTR
Detach
1 ms
D+/D−
SSPND
ÓÓ
ÓÓ
ÓÓ
Figure 29. Play, Stop, and Detach
Idle
5 ms
ÓÓ
ÓÓ
ÓÓ
Suspend
VOUTL
VOUTR
Active
Active
2.5 ms
Figure 30. Suspend and Resume
26
www.ti.com
SLES081A − JUNE 2003 – REVISED MAY 2004
TYPICAL CIRCUIT CONNECTION 1 (EXAMPLE OF USB SPEAKER)
Figure 31 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
X1
C1
C2
R1
PCM2704DB
External ROM
(Optional)
1 XTO
XTI
28
SUSPEND
SCL
2 CK
SSPND
27
SDA
3 DT
TEST0
26
4 PSEL
TEST1
25
5 DOUT
HID2/MD
24
6 DGND
HID1/MC
23
7 VDD
HID0/MS
22
8 D–
HOST
21
9 D+
VCCP
20
10 VBUS
PGND
19
11 ZGND
VCOM
18
AGNDR
17
VCCR
16
VOUTR
15
R9
S/PDIF OUT
VOLUME–
USB ’B’
Connector
R3
D–
R4
D+
VBUS
VOLUME+
C7
R2
C3
GND
12 AGNDL
MUTE
C6
C4
+
C8
C5
13 VCCL
14 VOUTL
C9
+
C13
+
C11
R5
C12
C10
R6 R7
+
+
C14
R8
TPA200X
Power
Amp
Notes:
X1: 12-MHz crystal resonator
C1, C2: 10-pF to 33-pF (depending on load capacitance of crystal resonator)
C3, C4, C5, C6, C7: 1-µF ceramic
C8: 47-µF electrolytic
C9, C10: 100-µF electrolytic (depending on tradeoff between required frequency response and discharge time for resume)
C11, C12: 0.022-µF ceramic
C13, C14: 1-µF electrolytic
R1: 1 MW
R2, R9: 1.5 kW
R3, R4: 22 W
R5, R6: 16 W
R7, R8: 330 W (depending on tradeoff between required THD performance and pop-noise level for suspend)
Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kW ±20%, which is the discharge path for C9 and C10.
External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power source.
Figure 31. Bus-Powered Application
Note that the circuit illustrated above is for information only. Whole-board design should be considered to meet the
USB specification as a USB-compliant product.
27
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SLES081A − JUNE 2003 – REVISED MAY 2004
TYPICAL CIRCUIT CONNECTION 2 (EXAMPLE OF REMOTE HEADPHONE)
Figure 32 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
C9
+
Headphone
+
C6
+
PLAY/PAUSE
NEXT TRACK
MUTE
VOLUME+
28
VOUTR
VOUTL
27
26
25
ZGND
29
VCCL
30
AGNDL
31
VCCR
C5
VCOM
32
C4
AGNDR
C3
C11
C12
R5
R6
R7
R8
R9
PGND
2
VCCP
VBUS 24
D+ 23
3
HOST
D– 22
4
FUNC3
5
FUNC0
6
HID0/MS
FUNC1 19
7
HID1/MC
FUNC2 18
8
HID2/MD
DOUT 17
R10
USB ’B’
Connector
R2
1
VBUS
D+
R3
D–
R4
VDD 21
PCM2706PJT
C10
GND
C8
DGND 20
C7
PREVIOUS TRACK
STOP
FSEL
TEST
SSPND
XTI
XTO
CK
DT
PSEL
VOLUME–
9
10
11
12
13
14
15
16
External ROM
(Optional)
SDA
R11
SUSPEND
SCL
R1
X1
C1
C2
Notes:
X1: 12-MHz crystal resonator
C1, C2: 10-pF to 33-pF (depending on load capacitance of crystal
resonator)
C3, C4, C5, C7, C8: 1-µF ceramic
C6: 47-µF electrolytic
C9, C10: 100-µF electrolytic (depending on required frequency
response)
C11, C12: 0.022-µF ceramic
R1: 1 MW
R2, R11: 1.5 kW
R3, R4: 22 W
R5, R6: 16 W
R7, R8, R9, R10: 3.3 kW
External ROM power can be supplied from VCCP, but any other active
component must not use VCCP, VCCL, VCCR, or VDD as a power source.
Figure 32. Bus-Powered Application
Note that the circuit illustrated above is for information only. Whole board design should be considered to meet the
USB specification as a USB-compliant product.
28
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SLES081A − JUNE 2003 – REVISED MAY 2004
TYPICAL CIRCUIT CONNECTION 3 (EXAMPLE OF DSP SURROUND PROCESSING AMP)
Figure 33 illustrates a typical circuit connection for an I2S- and SPI-enabled self-powered application.
C8
+
Headphone
+
SUSPEND
VCCL
VOUTL
VOUTR
VCCR
AGNDR
R6
R7
C9
R8
R9
R10
R2
1
PGND
VBUS 24
2
VCCP
D+ 23
3
HOST
D– 22
4
FUNC3
VDD 21
PCM2707PJT
DGND 20
FUNC0
6
HID0/MS
FUNC1 19
7
HID1/MC
FUNC2 18
8
HID2/MD
DOUT 17
PSEL
5
9
10
11
12
13
14
15
16
R11
USB ’B’
Connector
25
DT
MD
26
CK
MC
27
XTO
MS
28
XTI
LRCK
29
SSPND
DIN
30
TEST
TAS300X
I2S I/F Audio Device
31
FSEL
C5
VCOM
32
C4
C11
ZGND
C3
AGNDL
C6
+
C10
VBUS
R3
D+
D–
+
R4
R12
GND
C7
BCK
SYSTEM CLOCK
DOUT
R5
R1
X1
C1
Power
C2
3.3 V
GND
C8, C9: 100-µF electrolytic (depending on required frequency
response)
C10, C11: 0.022-µF ceramic
R1, R12: 1 MW
R2, R5: 1.5 kW
R3, R4: 22 W
R6, R7: 16 W
R8, R9, R10, R11: 3.3 kW
SPI host (DSP) must have responsibility to handle D+ pullup if descriptor is programmed by SPI. SPI host must not activate D+ pullup until all internal
registers have been set. D+ pullup must not be activated while detaching from host.
D+must not activate (HIGH: 3.3 V) before programming of the PCM2707 by SPI is completed.
D+must not activate (HIGH: 3.3 V) while the device is detached from the USB.
VBUS of the USB can be used to detect USB bus power status. (Note that VBUS of the USB connector is 5 V.)
Notes:
X1: 12-MHz crystal resonator
C1, C2: 10-pF to 33-pF (depending on load capacitance of crystal
resonator)
C3, C4: 1-µF ceramic
C5: 0.1-µF ceramic and 10-µF electrolytic
C6, C7: 47-µF electrolytic
Figure 33. Self-Powered Application
Note that the circuit illustrated above is for information only. Whole board design should be considered to meet the
USB specification as a USB-compliant product.
29
www.ti.com
SLES081A − JUNE 2003 – REVISED MAY 2004
APPENDIX
OPERATING ENVIRONMENT
For appropriate operation, one of the following operating systems must be running on a host PC equipped with a USB
port certified by the manufacturer. If these conditions are met, the operation of the PCM2704/5/6/7 does not depend
on the operating speed of the CPU. Texas Instruments has tested and confirmed the following listed operating
environments. The PCM2704/5/6/7 may work with other PCs and operating systems also, but proper operation using
them has not been tested and cannot be assured by TI.
Operating System
D Microsoftt Windowst 98SE/Windows Met Japanese/English edition (For Windows 98SE and Windows Me,
the HID function is not fully functional with the default class driver.)
D Microsoft Windows 2000 Professional Japanese/English edition
D Microsoft Windows XPt Home/Professional Japanese/English edition (For Windows XP, use the latest version
D
D
D
of the USB audio driver, which is available on the Windows update site, or apply Service Pack 1. See the Q310507
white paper available from Microsoft.)
Apple Computer Mac OSt 9.1 or later Japanese/English edition
Apple Computer Mac OS X 10.0 or later English edition
Apple Computer Mac OS X 10.1 or later Japanese edition SP (For the Mac OS X 10.0 Japanese edition, plug
and play does not work appropriately for USB audio devices.)
PC: One of These PC-AT Compatible Computers Running a Listed OS (OS Requirement Must Be Met)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Motherboard using Intel 440 BX or ZX chipset (using the USB controller in the chipset)
Motherboard using Intel i810 chipset (using the USB controller in the chipset)
Motherboard using Intel i815 chipset (using the USB controller in the chipset)
Motherboard using Intel i820 chipset (using the USB controller in the chipset)
Motherboard using Intel i845 chipset (using the ICH2 USB controller in the chipset)
Motherboard using Intel i845 chipset (using the ICH4 USB controller in the chipset)
Motherboard using Intel i850 chipset (using the USB controller in the chipset)
Motherboard using Intel i848 chipset (using the ICH5/R USB controller in the chipset)
Motherboard using Intel i865 chipset (using the ICH5/R USB controller in the chipset)
Motherboard using Intel i875 chipset (using the ICH5/R USB controller in the chipset)
Motherboard using Apollot KT133 chipset (using the USB controller in the chipset)
Motherboard using Apollo KT333 chipset (using the USB controller in the chipset)
Motherboard using Apollo Pro plus chipset (using the USB controller in the chipset)
Motherboard using MVP4 or MVP3 chipset (using the USB controller in the chipset)
Motherboard using Aladdin V chipset (using the USB controller in the chipset)
Motherboard using SiS530 or SiS559 chipset (using the USB controller in the chipset)
Motherboard using SiS735 chipset (using the USB controller in the chipset)
NOTE: The PCM2704/5/6/7 has been acknowledged in a USB compliance test. However, the acknowledgement is for the PCM2704/5/6/7 device
only, and does not apply to the customer’s system using the PCM2704/5/6/7.
Intel is a trademark of Intel Corporation.
Mac OS is a trademark of Apple Computer, Inc.
Microsoft, Windows, Windows Me, and Windows XP are trademarks of Microsoft Corporation.
Other trademarks are the property of their respective owners.
30
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
PJT (S-PQFP–N32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
0,20
M
0,20
0,09
Gage Plane
32
0,15
0,05
1
0,25
0°– 7°
7,00 SQ
0,75
0,45
9,00 SQ
1,05
0,95
Seating Plane
0,10
1,20
1,00
4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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