DATADELAY 1516C-25-2.0B

1516
data 3 
delay
devices, inc.
5-TAP DIP/SMD DELAY LINE
TD/TR = 3
(SERIES 1516)
FEATURES
•
•
•
•
•
PACKAGES
5 taps of equal delay increment
Delays to 200ns
Low profile
Epoxy encapsulated
Meets or exceeds MIL-D-23859C
GND
1
8
GND
IN
2
7
T5
T1
3
6
T4
T2
4
5
T3
The 1516-series device is a fixed, single-input, fiveoutput, passive delay line. The signal input (IN) is
reproduced at the outputs (T1-T5) in equal increments.
The delay from IN to T5 (TD) and the characteristic
impedance of the line (Z) are determined by the dash
number. The rise time (TR) of the line is 30% of TD, and
the 3dB bandwidth is given by 1.05 / TD. The device is
available in a 8-pin DIP (1516) or a 8-pin SMD (1516S),
and a wide range of pinouts may be specified.
1516(S)m - xxx - zzz p
MOUNTING HEIGHT CODE
See Table
DELAY TIME
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
IMPEDANCE
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
Part numbers are constructed according to the scheme
shown at right. For example, 1516C-101-500B is a 290
mil DIP, 100ns, 50Ω delay line with pinout code B.
Similarly, 1516SB-151-501 is a 240 mil SMD, 150ns,
500Ω delay line with standard pinout.
PINOUT CODE
See Table
Omit for STD pinout
DELAY SPECIFICATIONS
SERIES SPECIFICATIONS
Dielectric breakdown:
Distortion @ output:
Operating temperature:
Storage temperature:
Temperature coefficient:
50 Vdc
10% max.
-55°C to +125°C
-55°C to +125°C
100 PPM/°C
PINOUT CODES
CODE
STD
A
B
C
D
IN
2
1
1
7
1
T1
3
2
7
2
2
T2
4
3
3
6
7
T3
5
4
6
3
3
T4
6
6
4
5
6
T5
7
7
5
4
4
GND
1,8
5,8
8
1,8
5,8
MOUNTING HEIGHT CODES
CODE
A
B
C
Note:
HEIGHT (MAX)
0.187
0.240
0.290
SMD
No
Yes
Yes
TD
(ns)
5
10
15
20
25
30
40
50
60
75
80
100
110
125
150
180
200
TI
(ns)
1.0
2.0
3.0
4.0
5.0
6.0
8.0
10.0
12.0
15.0
16.0
20.0
22.0
25.0
30.0
36.0
50.0
TR
(ns)
3.0
4.0
5.0
6.0
7.0
10.0
13.0
15.0
20.0
25.0
26.0
30.0
32.0
40.0
50.0
60.0
70.0
Z=50Ω
Ω
N/A
3
3
3
3
3
3
3
3
3
4
4
4
4
N/A
N/A
N/A
ATTENUATION (%) TYPICAL
Z=100Ω
Ω Z=200Ω
Ω Z=300Ω
Ω Z=500Ω
Ω
5
N/A
N/A
N/A
5
5
N/A
N/A
5
5
N/A
N/A
5
5
5
N/A
5
5
5
7
5
5
5
7
5
5
5
7
5
5
7
7
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
8
10
10
7
8
10
10
8
10
12
12
Notes: TI represents nominal tap-to-tap delay increment
Tolerance on TD = ± 5% or ± 2ns, whichever is greater
Tolerance on TI = ± 5% or ± 1ns, whichever is greater
“N/A” indicates that delay is not available at this Z
Codes A and B are not available
for all values of TD
Contact technical staff for details
Doc #97029
2/7/97
DIP
Yes
Yes
Yes
Note: Standard pinout shown
Other pinouts available
PART NUMBER CONSTRUCTION
FUNCTIONAL DESCRIPTION
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•
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•
•
IN
Signal Input
T1-T5 Tap Outputs
GND Ground
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1997 Data Delay Devices
1
1516
FUNCTIONAL DIAGRAM
T1 T2 T3 T4
IN
T5
GND
GND
PACKAGE DIMENSIONS
8
7
6
5
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
1
2
3
4
.280
MAX.
.500 MAX.
See
Table
.015 TYP.
.010±.002
.018
TYP.
.070 MAX.
.350
MAX.
.300±.010
3 Equal spaces
each .100±.010
Non-Accumulative
1516-xx (DIP)
.020
TYP.
.040
TYP.
8
7
6
.010 TYP.
5
.270
TYP.
1
2
3
.100
.300
.520 MAX.
.430
TYP.
4
.110
See
Table
.050
TYP.
1516S-xx (Gull-Wing)
Doc #97029
2/7/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
1516
PASSIVE DELAY LINE TEST SPECIFICATIONS
TEST CONDITIONS
INPUT:
Ambient Temperature:
Input Pulse:
OUTPUT:
Rload:
Cload:
Threshold:
25oC ± 3oC
High = 3.0V typical
Low = 0.0V typical
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
at 10% and 90% levels)
Pulse Width (TD <= 75ns): PWIN = 100ns
Period
(TD <= 75ns): PERIN = 1000ns
Pulse Width (TD > 75ns): PWIN = 2 x TD
Period
(TD > 75ns): PERIN = 10 x TD
10MΩ
10pf
50% (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PERIN
PWIN
TRISE
INPUT
SIGNAL
TFALL
VIH
90%
50%
10%
90%
50%
10%
TRISE
VIL
TFALL
TRISE
OUTPUT
SIGNAL
90%
50%
10%
TFALL
VOH
90%
50%
10%
VOL
Timing Diagram For Testing
OUT
PULSE
GENERATOR
RIN
IN
DEVICE UNDER
TEST (DUT)
TRIG
50 Ω
RIN = ROUT = ZLINE
IN
T1
T2
T3
T4
T5
TRIG
OSCILLOSCOPE
ROUT
Test Setup
Doc #97029
2/7/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3