TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 N+1 and ORing Power Rail Controller with Enable Check for Samples: TPS2419 FEATURES 1 • • • • • • • • • Control External FET for N+1 and ORing Controls Buses From 3 V to 16.5 V External Enable N-Channel MOSFETControl Rapid Device Turnoff Protects Bus Integrity Programmable Turn-Off Threshold Soft Turn on Reduces Bus Transients Industrial Temperature Range: –40°C to 85°C 8-Pin TSSOP and SOIC Packages APPLICATIONS • • • • N+1 Power Supplies Server Blades Telecom Systems High Availability Power Modules Applications for the TPS2419 include a wide range of systems including servers and telecom. These applications often have either N+1 redundant power supplies, redundant power buses, or both. Redundant power sources must have the equivalent of a diode OR to prevent reverse current during faults and hotplug. Accurate voltage sensing and a programmable turn-off threshold allows operation to be tailored for a wide range of implementations and bus characteristics. The TPS2419 brings out an enable pin which allows the system to force the MOSFET off under light-load, high noise conditions. RSVD GND Common Voltage Rail C GATE R2 RSET EN The TPS2419 controller, in conjunction with an external N-channel MOSFET, provides the reverse current protection of an ORing diode with the efficiency of a MOSFET. The TPS2419 can be used to combine multiple power supplies to a common bus in an N+1 configuration, or to combine redundant input power buses. Table 1. Family Features CBYP BYP A R1 Voltage Source Enable DESCRIPTION '2410 '2411 Enable input √ √ Linear gate control √ '2412 '2419 √ √ √ ON/OFF gate control '2413 RSET Turnoff comparator filtering √ √ Voltage monitoring √ √ MOSFET fault monitoring √ √ Status pin √ √ Independent Supply Pin √ √ √ √ √ √ Figure 1. Typical Application 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS2419 SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCT INFORMATION (1) (1) DEVICE TEMPERATURE TPS2419 –40°C to 85°C PACKAGE (1) MOSFET GATE CONTROL MARKING ON/OFF TPS2419 PW (TSSOP-8) D (SO-8) For package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over recommended operating junction temperature range, voltages are referenced to GND (unless otherwise noted) VALUE UNIT –0.3 to 18 V A above C voltage 7.5 V C above A voltage 18 V GATE, BYP voltage (2) –0.3 to 30 V BYP to A voltage –0.3 to 13 V 0.3 V –0.3 to 7 V –0.3 to 5.5 V A, C voltage GATE above BYP voltage RSET (2) voltage EN GATE short to A or C or GND ESD TJ (1) (2) Indefinite Human body model Charged device model Maximum junction temperature 2 kV 500 V Internally limited °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage should not be applied to these pins. DISSIPATION RATINGS PACKAGE qJA – Low k °C/W qJA – High k °C/W POWER RATING High k TA = 85°C (mW) PW (TSSOP) 258 159 250 D (SO) 176 97.5 410 2 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 RECOMMENDED OPERATING CONDITIONS voltages are referenced to GND (unless otherwise noted) MIN A, C Input voltage range (1) A to C Operational voltage EN Input voltage range 0 (2) R(RSET) Resistance range C(BYP) Capacitance Range (2) 800 TJ Operating junction temperature –40 (1) (2) NOM 0 1.5 2200 MAX UNIT 16.5 V 5 V 5 V ∞ kΩ 10k pF 125 °C V(C) must exceed 2.5 V for normal operation and 3 V to meet gate drive specification Voltage should not be applied to these pins. ELECTRICAL CHARACTERISTICS (1) Common conditions (unless otherwise noted) are: [3 V ≤ ( V(A), V(C) ) ≤ 18 V ] , C(BYP) = 2200 pF, R(RSET) = open, EN = 2 V, GATE = open, –40°C ≤ TJ ≤ 125°C, positive currents into pins, typical values are at 25°C, all voltages with respect to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT A, C Supply UVLO A current C current V(C) rising 2.25 2.5 Hysteresis 0.25 | I(A) |, Gate in active region 0.66 | I(A) |, Gate saturated high 0.1 Worst case, gate in active region, V(AC) ≤ 0.1 V 4.25 Gate saturated high, V(AC) ≤ 0.1 V 1 6 1.2 V mA mA EN Threshold voltage V(EN) rising 1.25 Hysteresis Response time Leakage current (source or sink) 1.3 1.35 29 V mV V(AC) = 0.1 V, V(EN)↑ : 1.1 V → 1.4 V, measure period to V(GATE) = 0.25 V 0.65 1 V(AC) = 0.1 V, V(EN)↓: 1.4 V → 1.1 V, measure period to V(GATE) = V(ON) - 0.25 V 0.3 0.6 ms V(EN) = 0.5 V 1 mA 71 mV TURN ON Forward turn-on voltage - VON V(A-C) 58 65 TURN OFF Gate sinks > 10 mA at V(GATE-A) = 2 V Turn-off threshold voltage V(A-C) falling, R(RSET) = open 1 3 5 V(A-C) falling, R(RSET) = 28.7 kΩ -17 -13.25 -10 V(A-C) falling, R(RSET) = 3.24 kΩ -170 -142 -114 Turn-off delay V(A) = 12 V, V(A-C): 20 mV → –20 mV, V(GATE-A) begins to decrease Turn-off time V(A) = 12 V, C(GATE-GND) = 0.01 mF, V(A-C): 20 mV → –20 mV, measure the period to V(GATE) = V(A) (1) mV 70 ns 130 ns Parameters with only typical values are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. 3 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (1) (continued) Common conditions (unless otherwise noted) are: [3 V ≤ ( V(A), V(C) ) ≤ 18 V ] , C(BYP) = 2200 pF, R(RSET) = open, EN = 2 V, GATE = open, –40°C ≤ TJ ≤ 125°C, positive currents into pins, typical values are at 25°C, all voltages with respect to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE Gate positive drive voltage, V(GATE-A) Gate source current V(C) = 3 V, V(A-C) = 200 mV 6 7 8 5 V ≤ VC ≤ 18 V, V(A-C) = 200 mV 9 10.2 11.5 250 290 350 V(GATE) = 8 V 1.75 2.35 V(GATE) = 5 V 1.25 1.75 Period 7.5 12.5 ms V(A-C) = –0.1 V, 3 V ≤ VC ≤ 18 V, 2 V ≤ V(GATE) ≤ 18 V 15 19.5 mA 135 °C 10 °C V(A-C) = 200 mV, V(GATE-A) = 4 V V mA V(A-C) = –0.1 V Turn-off pulsed current, I(GATE) Sustain turn-off current, I(GATE) A MISCELLANEOUS Thermal shutdown temperature Temperature rising, TJ Thermal hysteresis + - FUNCTIONAL BLOCK DIAGRAM VDD 10V Charge Pump and Bias Supply HVUV BYP TURNON COMP. S Q R Q + A + - VON C 0.5V + 3mV - RSET VDD A - TURNOFF en COMP. GATE en + Thermal Shutdown en (135ºC) C 1.3V MULTISTAGE PULLDOWN EN RSVD GND VDD Bias and Control VBIAS en HVUV 4 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 PW and D PACKAGE (TOP VIEW) 1 4 RSET EN RSVD GND BYP A C GATE 8 5 TERMINAL FUNCTIONS TERMINAL NAME NO. RSET 1 EN RSVD I/O DESCRIPTION I Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightly positive V(A-C) turn-off threshold. 2 I Pull EN above 1.3 V to permit normal ORing operation. A low on EN holds GATE low. 3 PWR This pin must be connected to GND. GND 4 PWR Device ground. GATE 5 O Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode. C 6 I Voltage sense input that connects to the simulated diode cathode, and also serves as the bias supply for the gate drive charge pump and internal controls. Connect to the MOSFET drain in the typical configuration. A 7 I Voltage sense input that connects to the simulated diode anode, and also serves as the reference for the charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration. BYP 8 I/O Connect a capacitor from BYP to A to filter the gate drive supply voltage. 5 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 www.ti.com DETAILED DESCRIPTION The following descriptions refer to the pinout and the functional block diagram. A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V(A-C) exceeds 65 mV. A strong GATE pull-down is applied when V(A-C) is less than the programmable turn-off threshold (see RSET). These two thresholds serve as a hysteretic GATE control with the ON/OFF state preserved until the next (opposite) threshold cross. The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, is referenced to A. Some charge pump current appears on A. C is both the cathode voltage sense and the bias supply for the gate-drive charge pump and other internal circuits. This pin must be connected a source that is 3 V or greater when the external MOSFET is to be turned on. A 0.01-mF minimum bypass capacitor to GND is recommended for both A and C inputs. A and C connections to the bypass capacitor and the controlled MOSFET should be short and low impedance. The inputs are protected from excess differential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a small current flows out of C. Configurations which permit C to be more than 6 V lower than A should be avoided. BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits and GATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pF ceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering. Shorting this pin to a voltage below A damages the TPS2419. EN: A voltage greater than 1.3 V on EN permits the TPS2419 to operate in its normal ORing mode. A voltage below the lower threshold forces GATE to remain low, however EN going high will not automatically turn GATE ON. EN going low when GATE is high engages the sustain current pulldown. EN should not be driven higher than its recommended maximum voltage. GATE: Gate controls the external N channel MOSFET gate. GATE is driven positive with respect to A by a driver operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when the turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. The turn-off circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from floating. The gate connection should be kept low impedance to maximize turn-off current. GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. It carries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and also carries significant charge pump currents. RSET: A resistor connected from this pin to GND sets the V(A-C) turn-off comparator threshold. The threshold is slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turn-off voltage to increasing negative values. The TPS2419 must have a negative threshold programmed to avoid an unstable condition at light load. The expression for R(RSET) in terms of the turn-off voltage ( V(OFF)= V(A) - V(C)) follows. æ ö -470.02 ÷ R(RSET) = ç ç V(OFF) - 0.00314 ÷ è ø (1) The units of the numerator are (V × V/A). V(OFF) is positive for V(A) greater than V(C), V(OFF) is less than 3 mV, and R(RSET) is in ohms. RSVD: Connect to ground. 6 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS TURNOFF THRESHOLD vs TEMPERATURE PULSED GATE SINKING CURRENT vs GATE VOLTAGE 3.0 5.0 R(RSET) = Open o TJ = -40 C 4.5 2.5 4.0 o TJ = 25 C I(GATE) − A V(AC) − mV 2.0 3.5 3.0 2.5 TJ = 85oC 1.5 o TJ = 125 C 1.0 2.0 0.5 1.5 1.0 −40 0.0 −20 0 20 40 60 80 100 0 120 2 4 6 8 10 V(GATE - GND) − V o TJ − Junction Temperature − C Figure 2. Figure 3. TURNON DELAY vs V(C) (POWER APPLIED UNTIL GATE IS ACTIVE) I(C) vs V(C) (GATE SATURATED HIGH) 3.0 60 2.5 50 o TJ = -40 C 2.0 o TJ = 25 C o I(VDD) − mA Delay − ms 40 30 TJ = 125 C o TJ = 25 C 1.5 1.0 20 o TJ = -40 C o TJ = 125 C 10 0.5 0.0 0 2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18 VC − V VDD − V Figure 4. Figure 5. 7 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TURN ON VOLTAGE vs TEMPERATURE ENABLETHRESHOLD vs TEMPERATURE 65.5 1.32 65.4 1.31 65.3 EN - Threshold - V VON - mV EN Rising 1.3 65.2 65.1 65 64.9 64.8 1.29 EN Hysteresis ~ 29 mV 1.28 EN Falling 1.27 64.7 1.26 64.6 64.5 -40 -20 0 20 40 60 80 TJ - Temperature - °C 100 1.25 120 -40 -20 Figure 6. 0 20 40 60 80 100 TJ - Junction Temperature - °C 120 Figure 7. Turn on Threshold GATE drives 10 nF to GND VC = 12 V, RSET = 61.9 WW VA-C Turn off Threshold 10 V/DIV 20 mv/DIV EXAMPLE TURNON AND TURNOFF VGATE Time 1ms/DIV Figure 8. 8 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) EXAMPLE TURNOFF 1 A/DIV IGATE GATE drives 10 nF to GND VC = 12 V, RSET = 61.9 WW Turn off Threshold 10 V/DIV 20 mv/DIV VA-C VGATE = VA VGATE 135 ns Time 100ns/DIV Figure 9. 9 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 www.ti.com APPLICATION INFORMATION OVERVIEW The TPS2419 is designed to allow an output ORing in N+1 power supply applications (see Figure 11), and an input-power bus ORing in redundant source applications (see Figure 12). The TPS2419 and external MOSFET emulate a discrete diode to perform this unidirectional power combining function. The advantage to this emulation is lower forward voltage drop and higher efficiency. The TPS2419 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 10. GATE is driven high when V(A-C) exceeds 65 mV, and driven low if V(A-C) falls below the RSET programmed turn-off threshold. Operation of the TPS2419 is demonstrated in Figure 8 where an ac-coupled square wave is applied from A to C. Figure 8 shows the condition where the MOSFET gate is initially at GND, and V(A-C) is less than 65 mV. When the turn-on threshold is exceeded, the TPS2419 turns on the MOSFET gate, and charges it to V(BYP). The gate stays high even though V(A-C) is less than the turn-on threshold. The TPS2419 pulls the gate to GND when V(A-C) falls below the turn-off threshold. V(GATE) System designs should account for the inherent delay between a TPS2419 circuit becoming forward biased, and the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge from ground to its threshold voltage by the 290 mA gate current. If there are no additional sources holding a common ORed rail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output. The ORed input supply will experience a momentary large current draw as the MOSFET turns on, shorting the internal diode and charging the bus capacitance. Gate ON VON Programmable Fast Turn-off Threshold Range 3mV Gate OFF V(AC) Figure 10. TPS2419 Operation The operation of the TPS2419 is summarized in Table 2. Table 2. Operation as a Function of V(AC) TPS2419 (1) V(A-C) ≤ Turnoff Threshold (1) Turnoff Threshold (1) ≤ V(A-C) ≤ 65 mV V(A-C) > 65 mV Gate pulled to GND Depends on previous state (1) (Hysteresis region) GATE pulled high (ON) Turnoff threshold is established by the value of RSET. N+1 POWER SUPPLY – TYPICAL CONNECTION The N+1 power supply configuration shown in Figure 11 is used where multiple power supplies are paralleled for either higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra identical unit in parallel permits the load to continue operation in the event that any one of the N supplies fails. The supplies are ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when it is plugged-in or fails short. Thus, the TPS2419 with an external MOSFET emulates the function of the ORing diode. ORed supplies are usually designed to share power by various means, although the desired operation could implement an active and standby concept. Sharing approaches include both passive, or voltage droop, and active methods. Not all of the output ORing devices may be ON depending on the sharing control method, bus loading, distribution resistances, and tolerances. 10 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 Implementation Concept Power Bus CBYP EN C RSVD GATE GND BYP A DC/DC Converter Input Voltage Power Conversion Block Common Bus DC/DC Converter Figure 11. N+1 Power Supply Example INPUT ORing – TYPICAL CONNECTION Figure 12 shows how redundant buses may be ORed to a common point to achieve higher reliability. It is possible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of tolerance and regulation causes both TPS2419 circuits to see a forward voltage. The ORing MOSFET will disconnect the lower-voltage bus, protecting the remaining bus from potential overload by a fault. Backplane Power Buses Concept Implementation Common Buses C BYP EN GATE A C EN GATE BYP A LOAD GND GND BUS2 BUS1 DC/DC Converter CBYP CBYP Hotswap Plug-In Unit Figure 12. Example ORing of Input Power Buses 11 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 www.ti.com SYSTEM DESIGN AND NOISE ISSUES In noisy system environments, the low impedance of a MOSFET coupled with a default positive turn off threshold voltage might result in unwanted ON/OFF GATE cycling. Ideally the best way to approach the problem is with a clean layout and noise free system design. Since design constraints limit the ability to improve this, the following suggestions can be employed with the TPS2419. • Set the turn off threshold negative using the RSET pin. This is required to operate at light load, but does permit reverse current. • If current monitoring is used in the system, take advantage of the shunt resistor and connect the A and C pins across the shunt and FET. This increases the sense resistance, reducing noise sensitivity by increasing the signal levels while reducing the permitted reverse current. • Disable the device using EN under light load conditions. RECOMMENDED OPERATING RANGE The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A and C, solely to provide some margin for transients on the bus. The TPS2419 will operate properly up to the absolute maximum voltage ratings on A and C. Most power systems experience transient voltages above or below the normal operating level. Short transients, or voltage spikes, may be clamped by the ORing MOSFET to an output capacitor and/or voltage rail depending on the system design. Protection may be required on the input or output if the system design does not inherently limit transient voltages between the TPS2419 absolute maximum ratings (positive or negative). Protection for positive transients that would exceed the absolute maximum limits may be accomplished with a TVS diode (transient voltage suppressor) clamp to ground, or a diode clamp to a safe voltage rail. If a TVS is required, it must protect to the absolute maximum ratings at the worst case clamping current. Protection for negative transients that would drive pins (e.g. C) below the absolute maximum limits may be accomplished with a diode clamp to ground. Limit transient current in or out of the TPS2419 to less than 50 mA. Transients can also be controlled by bus capacitance or composite snubber/clamps such as a zener-blocked large capacitor with a discharge resistor in parallel. MOSFET SELECTION AND R(RSET) MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltage rating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdown voltage. The MOSFET gate rating should exceed be the maximum of the controlled rail voltage or 11.5 V. While rDS(on) is often chosen with the power dissipation, voltage drop, size and cost in mind, there are several other factors to be concerned with in ORing applications. When using a TPS2419 with RSET programmed to a negative voltage, the permitted static reverse current is equal to the turn-off threshold divided by the MOSFET's rDS(on). While this current may actually be desirable in some systems, the amount may be controlled by selection of rDS(on) and RSET. The practical range of rDS(on) for a single MOSFET runs from the low milliohms to 40 mΩ for a single MOSFET. MOSFETs may be paralleled for lower voltage drop (power loss) at high current. Current sharing depends on the resistance match including both the rDS(on), connection resistance, and thermal coupling. The TPS2419 may only be operated without an RSET programming resistor if the loading provides a V(A-C) greater than 3 mV. A negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but permits larger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the turn-off threshold per Equation 2. æ ö -470.02 ÷ R(RSET) = ç ç V(OFF) - 0.00314 ÷ è ø (2) 12 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 To obtain a -10 mV turnoff ( V(A) is less than V(C) by 10 mV ), R(RSET) = (–470.02/ ( –0.01–0.00314) ) ≈ 35.7 kΩ. If a 10 mΩ rDS(on) MOSFET was used, the reverse turnoff current would be calculated as follows. V(THRESHOLD) I(TURN_OFF) = r DS(on) I(TURN_OFF) = -10 mV 10 mW I(TURN_OFF) = - 1 A (3) The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ). The turn-off speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance CISS). Since these capacitances vary a great deal between different vendor parts and technologies, they should be considered when selecting a MOSFET where the fastest turn-off is desired. GATE DRIVE, CHARGE PUMP AND C(BYP) Gate drive of 290 mA typical is generated by an internal charge pump and current limiter. Make sure to use low impedance traces and good bypass on A and C to avoid having the large charge pump currents interfere with voltage sensing. The GATE drive voltage is referenced to V(A) as GATE will only be driven high when V(A) > V(C). The capacitor on BYP (bypass) must be used in order to form a quiet supply for the internal high-speed comparator. Gate Drive Resistance and Output Transients The strong gate (pulsed) pull-down current can turn the ORing MOSFET(s) off in the 100 - 200 ns time frame. While this serves to rapidly stop the reverse current buildup, it has a side effect of inducing a voltage transient on the input bus, the output bus, and ground. One transient source is the GATE turn-off current itself, which excites parasitic L-C tank circuits. A second transient source is the energy stored in power bus inductance driving a voltage surge and ringing as reverse MOSFET current is interrupted. Both of these effects can be reduced by limiting the GATE discharge current with a series resistor in the 10 Ω to 200 Ω range. This both reduces the peak discharge current, and slows the MOSFET turnoff, reducing the di/dt. A careful tradeoff of peak reverse current and the effects of the voltage transient may be required. An example of turnoff speed with and without GATE resistance is illustrated by the circuit of Figure 13. Figure 14 and Figure 15 show GATE, the MOSFET gate, and VC-ac for similar turnoff transients and gate resistors of 0 Ω and 51 Ω. A substancial reduction in noise is shown for a difference of 90ns in actual current termination. These techniques may be used in conjunction with clamping and snubbing techniques discussed in RECOMMENDED OPERATING RANGE. Figure 13 also demonstrates the filtering discussed in the next section. 0.47mF VIN VOUT C 0.47mF RSET 61.9kW GATE GND BYP A EN RGATE2 RGATE1 2200pF 0.47mF “1” M1, M2 CSD16401 Figure 13. Circuit for Gate Resistor Waveforms 13 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 Turn on Threshold www.ti.com VC Output 10 V/DIV 100 mv/DIV AC_Coupled SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 Configuration: 2 x ( CSD16401, TI with 0W gate resistors) MOSFET stops conducting 10 V/DIV VGATE_MOSFET VGATE_2419 Time 50ns/DIV 10 V/DIV 10 V/DIV 100 mv/DIV AC_Coupled Figure 14. Gate Turnoff Waveforms with RGATE = 0Ω VC Output Configuration: 2 x ( CSD16401, TI with 51W in gate) MOSFET stops conducting VGATE_MOSFET VGATE_2419 Time 50ns/DIV Figure 15. Gate Turnoff Waveforms with RGATE = 51Ω 14 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 Input Filtering Voltage transients, converter switching noise and ripple, and ringing due to current interruptions can potentially cause undesired on-off cycling, especially at very light loads. This includes voltage gradients (especially at MHz frequencies) across the ground plane effecting the apparent V(A) and V(C). The effects of these unwanted signals can be reduced by providing input filtering as shown in Figure 16 and Figure 13. There are two potential problems that the filter might have to help with, 1) internally generated switching noise, and 2) fast ringing transients caused by nearby power system events. Case 2 (in Figure 16) filtering is better at suppressing internal switching noise and Case 1 is better for large bus transients in the megahertz range. The "Z" element in CASE 1 is a high-impedance ferrite bead with low resistance to limit the dc voltage error. The L-C filter limits the apparent V(A) voltage swings during high-speed transients. The L-C in series with A also causes a phase delay in sensed steady-state switching noise, creating an apparent additional V(AC). The filter capacitors should be located close to the TPS2419's GND pin and be connected to GND by a solid plane. The A-C capacitor should be located directly across the TPS2419 pins. These values were empirically chosen in a particular test setup and may have to be tuned for different systems. The waveform of Figure 17 shows turnon in the presence of 135 mVpp ripple by the circuit of Figure 13. The ORing circuit was loaded with 10 kΩ parallel to 0.1 µF, and had only a -4.5 mV turnoff threshold. This condition is often difficult to turn on into due to the V(A-C) difference that occurs when the MOSFET diode peak charges the output. The output voltage was monitored with the oscilloscope probe ac-coupled, causing visual artifacts due to the probe settling time. The increase in output ripple is evident as the dynamic impedance of the MOSFET diode is shorted by the channel resistance. Selection of the A and C sense points can also play a role in limiting unwanted turnoff events. Sensing voltages at bus bypass capacitors may benefit operation by limiting the apparent switching and transient noise. The TPS2419 uses C as both a voltage sense and power pin. Placing resistance in this lead will cause a reduction in V(C) due to IxR voltage drop, changing the apparent turnon and turnoff thresholds. CASE 2 CASE 1 FROM “GATE” FROM “GATE” Z = 600W, 0.1W, 2A 0.47mF 0.47mF TO “C” 1W TO “A” 0.47mF TO “A” 0.47mF TO “C” 0.47mF 0.47mF Figure 16. Input Filtering Configurations 15 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com 100 mv/DIV AC_Coupled SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 135mVPP 200 mV/DIV VC Output VA-C VC = 12 V, Load = 10 kW || 0.1mF Note slight (-) offset in differential probe 15V VGATE 10V Time 10ms/DIV Figure 17. Turnon with Noisy Power Rail SUMMARIZED DESIGN PROCEDURE The following is a summarized design procedure: 1. Noise voltage and impedance at the A and C pins should be kept low. A minimum 0.01 mF or more may be required. 2. Select C(BYP) as 2200 pF, X7R, 25-V or 50-V ceramic capacitor. 3. Select the MOSFET based on considerations of voltage drop, power dissipated, voltage ratings, and gate capacitance. See sections: MOSFET Selection and RSET. 4. Select R(RSET) based on which MOSFET was chosen and reverse current considerations – see MOSFET Selection and RSET. 5. Make sure to connect RSVD to ground Layout Considerations 1. The TPS2419, MOSFET, and associated components should be used over a ground plane. 2. The GND connection should be short and wide, with multiple vias to ground. 3. A and C bypass capacitors should be adjacent to the pins with a minimal ground connection length to the plane. 4. The GATE connection should be short and wide (e.g., 0.025" minimum). 5. Route the A and C sense lines away from noisy sources, and avoid large ground bounce between the MOSFET and TPS2419. 6. R(SET) should be kept immediately adjacent to the TPS2419 with short leads. 7. C(BYP) should be kept immediately adjacent to the TPS2419 with short leads. 16 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 TPS2419 www.ti.com SLVS998A – FEBRUARY 2010 – REVISED MARCH 2010 REVISION HISTORY Changes from Original (February 2010) to Revision A Page • Changed the data sheet From: Preview To: Production Data .............................................................................................. 1 • Changed the Overview section - paragraph 2 From: MOSFET gate is initially low, and V(AC) is less than 64 mV. To: MOSFET gate is initially at GND, and V(A-C) is less than 65 mV. ........................................................................................ 10 • Changed the Overview section - paragraph 2, From: The TPS2419 turns on the MOSFET gate, and charges it to V(BYP) once the turn-on threshold is exceeded. To: When the turn-on threshold is exceeded, the TPS2419 turns on the MOSFET gate, and charges it to V(BYP) ........................................................................................................................ 10 • Changed the Overview section - paragraph 3 From: The ORed input supply will experience a momentary large load as the MOSFET turns on, shorting the internal diode and charging the bus capacitance. To: The ORed input supply will experience a momentary large current draw as the MOSFET turns on, shorting the internal diode and charging the bus capacitance. ........................................................................................................................................................... 10 • Changed the RECOMMENDED OPERATING RANGE section, paragraph 1 From: The TPS2419 will operate properly up to the absolute maximum voltage ratings on A, C, and VDD. To: The TPS2419 will operate properly up to the absolute maximum voltage ratings on A and C. ........................................................................................................... 12 17 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2419 PACKAGE OPTION ADDENDUM www.ti.com 24-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2419D ACTIVE SOIC D 8 TPS2419DR ACTIVE SOIC D TPS2419PW ACTIVE TSSOP TPS2419PWR ACTIVE TSSOP 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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