TI SN74ALVCH16501

SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB
is high, the outputs are active. When OEAB is low,
the outputs are in the high-impedance state.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16501 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
FUNCTION TABLE†
INPUTS
OEAB
LEAB
CLKAB
A
OUTPUT
B
Z
L
X
X
X
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
L
H
X
H
B0‡
B0§
† A-to-B data flow is shown; B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§ Output level before the indicated steady-state input
conditions were established
H
2
L
L
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SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
logic symbol†
OEAB
CLKAB
LEAB
1
55
2
27
OEBA
CLKBA
LEBA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
30
28
3
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
1
1
4
1
6D
54
5
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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3
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
logic diagram (positive logic)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
54
B1
1D
C1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
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SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
2
0.35 × VCC
VI
VO
Input voltage
0
Output voltage
0
IOL
∆t/∆v
0.7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High level output current
High-level
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
Low level output current
Low-level
VCC = 2.7 V
VCC = 3 V
Input transition rise or fall rate
V
1.7
Low-level input voltage
IOH
V
0.65 × VCC
VIL
VCC = 1.65 V
VCC = 2.3 V
UNIT
V
0.8
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
IOZ§
ICC
∆ICC
Ci
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2
UNIT
V
0.2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
3.6 V
±5
VI = 0.58 V
VI = 1.07 V
1.65 V
25
1.65 V
–25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
–45
VI = 0.8 V
VI = 2 V
3V
75
3V
–75
V
µA
µA
VI = 0 to 3.6 V‡
3.6 V
±500
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
750
µA
One input at VCC – 0.6 V,
Control inputs
2.3 V
0.45
IOL = 24 mA
VI = VCC or GND
II(hold)
(
)
MAX
VCC–0.2
1.2
1.65 V
IOL = 12 mA
II
TYP†
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
MIN
IO = 0
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
3 V to 3.6 V
3.3 V
4
pF
Cio
A or B ports
3.3 V
8
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup time
Hold time
MAX
¶
VCC = 2.5 V
± 0.2 V
MIN
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
LE high
3.3
3.3
3.3
CLK high or low
¶
3.3
3.3
3.3
Data before CLK↑
¶
2.2
2.1
1.7
CLK high
¶
1.9
1.6
1.5
CLK low
¶
1.3
1.1
1
¶
0.6
0.6
0.7
¶
1.4
1.7
1.4
Data
before LE↓
Data after CLK↑
Data after LE↓
CLK high or low
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UNIT
MAX
150
¶
¶ This information was not available at the time of publication.
6
MAX
VCC = 2.7 V
MHz
ns
ns
ns
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
TO
(OUTPUT)
MIN
†
fmax
A or B
tpd
LE
CLK
B or A
A or B
TYP
VCC = 2.5 V
± 0.2 V
MIN
MAX
150
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
†
1
4.8
4.5
1
3.9
†
1.1
5.7
5.3
1.3
4.6
†
1.2
6.1
5.6
1.4
4.9
ns
ten
tdis
OEAB
B
†
1
5.8
5.3
1
4.6
ns
OEAB
B
†
1.5
6.2
5.7
1.4
5
ns
ten
tdis
OEBA
A
†
1.3
6.3
6
1.1
5
ns
†
1.3
5.3
4.6
1.3
4.2
ns
OEBA
A
† This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
pF
CL = 50 pF,
VCC = 1.8 V
TYP
†
f = 10 MHz
†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
44
54
6
6
UNIT
pF
† This information was not available at the time of publication.
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SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
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SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
Input
1.5 V
1.5 V
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
tPZH
tPHL
1.5 V
VOL
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
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Copyright  2000, Texas Instruments Incorporated