SN54ALS259, SN74ALS259 8-BIT ADDRESSABLE LATCHES SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994 • • • • • • • SN54ALS259 . . . J PACKAGE SN74ALS259 . . . D OR N PACKAGE (TOP VIEW) 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable/Disable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs S0 S1 S2 Q0 Q1 Q2 Q3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLR G D Q7 Q6 Q5 Q4 SN54ALS259 . . . FK PACKAGE (TOP VIEW) S1 S0 NC VCC CLR description These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. 3 S2 Q0 NC Q1 Q2 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 G D NC Q7 Q6 Q3 GND NC Q4 Q5 Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as shown in the function table. In the NC – No internal connection addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. The SN54ALS259 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS259 is characterized for operation from 0°C to 70°C. Function Tables FUNCTION INPUTS CLR G OUTPUT OF ADDRESSED LATCH EACH OTHER OUTPUT FUNCTION Addressable latch H L D QiO H H QiO QiO Memory L L D L 8-line demultiplexer L H L L Clear D = the level at the data input. QiO = the level of Qi (i = Q, 1, . . . 7 as appropriate) before the indicated steady-state input conditions were established. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS259, SN74ALS259 8-BIT ADDRESSABLE LATCHES SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994 Function Tables (Continued) LATCH SELECTION SELECT INPUTS S0 LATCH ADDRESSED S2 S1 L L L 0 L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 logic symbol† S0 S1 S2 1 3 14 G D CLR 0 2 13 15 8M 0 7 2 G8 Z9 Z10 4 9, 0D 10, 0R 5 9, 1D 10, 1R 6 9, 2D 10, 2R 7 9, 3D 10, 3R 9 9, 4D 10, 4R 10 9, 5D 10, 5R 11 9, 6D 10, 6R 12 9, 7D 10, 7R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SN54ALS259, SN74ALS259 8-BIT ADDRESSABLE LATCHES SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994 logic diagram (positive logic) G D 14 4 13 5 S0 7 10 Q3 Q4 Q5 3 11 12 CLR Q2 2 9 S2 Q1 1 6 S1 Q0 Q6 Q7 15 Pin numbers shown are for the D, J, and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS259, SN74ALS259 8-BIT ADDRESSABLE LATCHES SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS259 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS259 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS259 SN74ALS259 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current – 0.4 – 0.4 mA IOL Low-level output current 4 8 mA tw Pulse duration tsu Setup time th Hold time TA Operating free-air temperature High-level input voltage 2 2 G low 20 15 CLR low 10 10 Data before G↑ 20 15 Address before G↑ 20 15 Data after G↑ 0 0 Address after G↑ 0 0 – 55 125 V V V ns ns ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO§ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V SN54ALS259 TYP‡ MAX MIN SN74ALS259 TYP‡ MAX MIN – 1.5 VCC – 2 – 1.5 VCC – 2 0.25 0.4 0.1 – 20 UNIT V V 0.25 0.4 0.35 0.5 0.1 V mA 20 20 µA – 0.1 – 0.1 mA – 112 mA – 112 – 30 ICC VCC = 5.5 V 14 22 14 22 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS259, SN74ALS259 8-BIT ADDRESSABLE LATCHES SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER tPHL tPLH tPHL tPLH tPHL tPLH FROM (INPUT) CLR TO (OUTPUT) Any Q Data Any Q Address Any Q Execute Any Q VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54ALS259 SN74ALS259 MIN MAX MIN MAX 2 15 2 12 4 22 4 19 2 15 2 12 4 26 4 22 2 15 2 12 4 22 4 20 2 13 tPHL 2 16 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns 5 SN54ALS259, SN74ALS259 8-BIT ADDRESSABLE LATCHES SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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