TI SN74ALS2240

SN74ALS2240
OCTAL BUFFER AND LINE DRIVER/MOS DRIVER
WITH 3-STATE OUTPUTS
SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997
D
D
D
DW OR N PACKAGE
(TOP VIEW)
Bidirectional Quadruple-Bus Transceivers
for Driving MOS Devices
I/O Ports Have 25-Ω Series Resistors, So
No External Resistors Are Required
Package Options Include Plastic
Small-Outline (DW) Package and Standard
Plastic (N) 300-mil DIPs
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
description
This octal buffer and line driver/MOS driver is
designed to drive the capacitive inputs of MOS
devices and to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. This device features high fan-out
and improved fan-in.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
The SN74ALS2240 is characterized for operation
from 0°C to 70°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
L
H
L
L
L
H
H
X
Z
logic symbol†
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
EN
2
18
4
16
6
14
8
12
19
1Y1
1Y2
1Y3
1Y4
EN
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALS2240
OCTAL BUFFER AND LINE DRIVER/MOS DRIVER
WITH 3-STATE OUTPUTS
SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997
logic diagram (positive logic)†
1
1OE
1A1
2
18
4
16
1A2
1A3
1A4
1Y1
1Y2
6
14
8
12
1Y3
1Y4
19
2OE
2A1
2A2
2A3
2A4
11
9
2Y1
13
7
15
5
17
3
2Y2
2Y3
2Y4
† All output resistors are 25 Ω.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 70°C
Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51, except for through hole packages, which use a trace length
of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALS2240
OCTAL BUFFER AND LINE DRIVER/MOS DRIVER
WITH 3-STATE OUTPUTS
SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997
recommended operating conditions
VCC
VIH
Supply voltage
VIL
TA
Low-level input voltage
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
Operating free-air temperature
UNIT
V
V
0
0.8
V
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
VOL
VCC = 4
4.5
5V
IOL = 1 mA
IOL = 12 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
IOH
IOL
VCC = 4.5 V,
VCC = 4.5 V,
ICC
VCC = 5.5 V
TYP†
MAX
UNIT
– 1.2
V
VCC – 2
V
0.15
0.5
0.35
0.8
20
– 30
V
µA
– 20
µA
0.1
mA
20
µA
– 0.1
mA
– 112
mA
–15
mA
15
mA
Outputs high
6
11
Outputs low
13
23
Outputs disabled
12
20
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§
UNIT
MIN
MAX
2
10
2
10
Y
5
17
ns
OE
Y
7
20
ns
tPHZ
OE
Y
2
10
ns
tPLZ
OE
Y
4
15
ns
tPLH
tPHL
A
Y
tPZH
OE
tPZL
ns
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ALS2240
OCTAL BUFFER AND LINE DRIVER/MOS DRIVER
WITH 3-STATE OUTPUTS
SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
3.5 V
tPHZ
VOL
0.3 V
0.3 V
[0 V
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
Input
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
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• DALLAS, TEXAS 75265
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