TI SN74ABT5402A

SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
D
D
D
D
D
D
SN54ABT5402A . . . JT PACKAGE
SN74ABT5402A . . . DW PACKAGE
(TOP VIEW)
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
Typical VOLV (Output Undershoot) < 0.5 V at
VCC = 5 V, TA = 25°C
Package Options Include Plastic
Small-Outline (DW) Package and Ceramic
Chip Carriers (FK) and DIPs (JT)
Y1
Y2
Y3
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
OE1
description
These 12-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
D1
D2
D3
D4
D5
D6
D7
VCC
D8
D9
D10
D11
D12
OE2
D4
D5
D6
D7
VCC
D8
D9
SN54ABT5402A . . . FK PACKAGE
(TOP VIEW)
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all 12 outputs are in the
high-impedance state.
4
D3
D2
D1
Y1
Y2
Y3
Y4
The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
19
11
12 13 14 15 16 17 18
D10
D11
D12
OE2
OE1
Y12
Y11
Y5
Y6
GND
Y7
Y8
Y9
Y10
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
5
The SN54ABT5402A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT5402A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE1
OE2
D
OUTPUT
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
logic symbol†
14
OE1
OE2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
logic diagram (positive logic)
&
OE1
28
27
OE2
EN
15
1
1
2
26
3
25
4
24
5
23
6
22
8
20
9
19
10
18
11
17
12
16
13
D1
14
15
28
1
Y1
Y1
Y2
Y3
To Eleven Other Channels
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT5402A
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT5402A
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
–55
0
V
V
0.8
VCC
–12
UNIT
VCC
–12
V
V
mA
12
12
mA
10
10
ns/V
85
°C
125
–40
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
–1.2
SN74ABT5402A
MIN
II = –18 mA
IOH = –1 mA
3.35
3.7
3.3
3.35
VCC = 5 V,
IOH = –1 mA
IOH = –3 mA
3.85
4.2
3.8
3.85
3
3.1
IOH = –12 mA
IOL = 8 mA
2.6
VCC = 4
4.5
5V
Vhys
II
TA = 25°C
SN54ABT5402A
TYP†
MAX
MIN
MAX
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4
4.5
5V
VOL
MIN
–1.2
MAX
–1.2
V
V
2.6
0.8
0.65
IOL = 12 mA
0.8
100
V
mV
±1
VCC = 5.5 V, VI = VCC or GND
VCC = 5.5 V,
VO = 2.7 V
IOZH
IOZL
UNIT
±1
±1
µA
10
10
10
µA
–10
–10
–10
µA
±100
µA
50
µA
VCC = 5.5 V,
VCC = 0,
VO = 0.5 V
VI or VO ≤ 4.5 V
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
IO
IOS‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.5 V
VO = 0
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
Outputs high
5
50
50
50
µA
ICC
Outputs low
39
48
48
48
mA
1
50
50
50
µA
1.5
1.5
1.5
0.05
0.05
0.05
1.5
1.5
1.5
Ioff
Data inputs
∆ICC§
Control
inputs
Ci
Co
±100
50
–25
–45
–50
Outputs disabled
VCC = 5.5 V, One
Outputs enabled
input at 3.4 V,,
Other inputs at
Outputs disabled
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
50
–100
–25
–100
–25
–100
mA
–200
–50
–200
–50
–200
mA
mA
3
pF
8
pF
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT5402A
MIN
TYP
MAX
MIN
MAX
MIN
MAX
2
4.5
5.2
2
6.3
2
6.2
1.5
3.7
5
1.5
5.7
1.5
5.6
2.5
5.7
7.6
2.5
8.8
2.5
8.7
2
4.4
6.3
2
7.6
2
7.5
1.5
3.6
4.4
1.5
5.5
1.5
5.2
1.5
4.2
5.4
1.5
7.4
1.5
6.9
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
SN74ABT5402A
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tsu
th
3V
Data Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
1.5 V
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  1998, Texas Instruments Incorporated