LSI/CSI UL ® LS7211N-7212N LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 July 2009 PROGRAMMABLE DIGITAL DELAY TIMER A 0 0 1 1 B 0 1 0 1 MODE One-Shot (OS) Delayed Operate (DO) Delayed Release (DR) Dual Delay (DD) B 2 17 WB0 V DD (+V) 3 16 WB1 RC/CLOCK 4 RCS/CLKS 5 PSCLS 6 RESET 7 12 WB5 V SS (-V) 8 11 WB6 9 10 WB7 OUT 15 WB2 14 WB3 13 WB4 A 1 B 2 17 WB0 V DD (+V) 3 16 WB1 XTLI/CLOCK 4 15 WB2 XTLO 5 PSCLS 6 RESET 7 12 WB5 V SS (-V) 8 11 WB6 OUT 9 10 WB7 18 TRIG LS7212N TABLE 1. MODE SELECTION 1 LS7211N I/O DESCRIPTION: MODE SELECT Inputs A & B (Pins 1 & 2) The 4 operating modes are selected by Inputs A and B according to Table 1 18 TRIG A LSI DESCRIPTION: The LS7211N and LS7212N are CMOS integrated circuits for generating digitally programmable delays. The delay is controlled by 8 binary weighted inputs, WB0 - WB7, in conjunction with an applied clock or oscillator frequency. The programmed time delay manifests itself in the Delay Output (OUT) as a function of the Operating Mode selected by the Mode Select inputs A and B: One-Shot, Delayed Operate, Delayed Release or Dual Delay. The time delay is initiated by a transition of the Trigger Input (TRIG). PIN ASSIGNMENT - TOP VIEW LSI FEATURES: • 8-bit programmable delay from microseconds to days • On chip oscillator (RC or Crystal) or external clock time base • Selectable prescaler for real time delay generation based on 50Hz/60Hz time base or 32,768Hz watch crystal • Four operating modes • Reset input for delay abort • Low quiescent and operating current • Direct relay drive • +3V to +18V operation (VDD - VSS) • LS7211N, LS7212N (DIP); LS7211N-S, LS7212N-S (SOIC) - See Figure 1 - 14 WB3 13 WB4 FIGURE 1 Each input has an internal pull-up resistor of about 500kΩ. One-Shot Mode (OS) A positive transition at the TRIG input causes OUT to switch low without delay and starts the delay timer. At the end of the programmed delay timeout, OUT switches high. If a delay timeout is in progress when a positive transition occurs at the TRIG input, the delay timer will be restarted. A negative transition at the TRIG input has no effect. Delayed Operate Mode (DO) A positive transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches low. A negative transition at the TRIG input causes OUT to switch high without delay. OUT is high when TRIG is low. 7211N-07209-1 Delayed Release Mode (DR) A negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches high. A postive transition at the TRIG input causes OUT to switch low without delay. OUT is low when TRIG is high. Dual Delay Mode (DD) A positive or negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches to the logic state which is the inverse of the TRIG input. If a delay timeout is in progress when a transition occurs at the TRIG input, the delay timer is restarted. TIMER RESET Input (RESET, Pin 7) When RESET input switches high, any timeout in progress is aborted and OUT switches high without delay. With RESET high, OUT remains high. When RESET switches low with TRIG low in any mode, OUT remains high. When RESET switches low with TRIG high in Delayed Operate and Dual Delay modes, the delay timer is started and OUT switches low at the end of the delay timeout. When RESET switches low with TRIG high in Delayed Release mode, OUT switches low without delay. When RESET LS7211N TIME BASE Input (RC/CLOCK, Pin 4) For LS7211N, the basic timing signal is applied at the RC/ switches low with TRIG high in One-Shot mode, OUT reCLOCK input. The clock can be provided from either an ex- mains high. RESET input has an internal pull-down resistor ternal source or generated by an internal oscillator by con- of about 500kΩ, and is buffered by a Schmitt Trigger to provide input hysteresis. necting an R-C network to this input. The frequency of oscillation is given by ƒ 1/RC. Chip-toVSS (-V, Pin 8) chip oscillation tolerance is ± 5% for a fixed value of RC. Supply voltage negative terminal or GND. The minimum resistance, R MIN = 4000Ω, VDD = + 4V = 1200Ω, VDD = +10V DELAY Output (OUT, Pin 9) = 600Ω, VDD = +18V Except in One-Shot mode, OUT switches with or without The external clock mode is selected by applying a logic low delay (depending on mode) in inverse relation to the logic to the RCS/CLKS input (Pin 5); the internal oscillator mode is level of the TRIG input. In One-Shot mode, a timed low level is produced at OUT, in response to a positive transiselected by applying a high level to the RCS/CLKS input. tion of the TRIG input. LS7212N TIME BASE Input (XTLI/CLOCK, Pin 4) For LS7212N, the basic timing clock is applied to the XLTI/ WEIGHTING BIT Inputs (WB7 to WB0, Pins 10 - 17) CLOCK input from either an external clock source or gener- Inputs WB0 through WB7 are binary weighted delay bits ated by an internal crystal oscillator by connecting a crystal used to program the delay according to the following relations: between XTLI/CLOCK input and the XTLO output (Pin 5). TRIGGER Input (TRIG, Pin 18) A transition at the TRIG input causes OUT to switch with or without delay, depending on the selected mode. The TRIG input to OUT transition relation is always opposite in polarity, with the exception of One-Shot mode. (See Mode definitions above.) TRIG input has an internal pull-down resistor of about 500k Ω and is buffered by a Schmitt trigger to provide input hysteresis. One-Shot Mode: Pulse width = SW LS7211N TIME BASE SELECT Input (RCS/CLKS, Pin 5) ƒ For LS7211N, the external clock operation at Pin 4 is selected by applying a logic low to the RCS/CLKS input. The internal oscillator option with RC timer at Pin 4 is selected by All other Modes: Delay = SW + 0.5 ƒ applying a logic high at the RCS/CLKS input. RCS/CLKS inWhere: put has an internal pull-down resistor of about 500kΩ. S = Prescale factor (See Table 2) ƒ = Time base frequency at Pin 4 LS7212N TIME BASE Output (XTLO, Pin 5) For LS7212N, when a crystal is used for generating the time W = WB0 + WB1 + ....... WB7 base oscillation, the crystal is connected between XTLI/ The weighting factor W is calculated by substituting in the CLOCK and XTLO pins. equation above for W, the weighted values for all the WB inputs that are at logic high. The weighted values for the PRESCALER SELECT Input (PSCLS, Pin 6) The PSCLS input is a 3-state input, which selects one of WB inputs are shown in Table 3. Each WB input has an internal pull-down resistor of about 500kΩ. three prescale factors according to Table 2. TABLE 2. PRESCALE FACTOR SELECTION PSCLS Input Logic Level Float VSS VDD S (Prescale Factor ) LS7211N LS7212N 1 1 3,000 32,768 3,600 32,768x60 Using prescale factors of 3000 and 3600, delays in units of minutes can be produced from 50Hz and 60Hz line sources. Prescale factors of 32,768 and 32,768 x 60 can be used to generate accurate delays in units of seconds and minutes, respectively, from a 32kHz watch crystal. 7211N-062209-2 TABLE 3. BIT WEIGHTS BITS WB0 WB1 WB2 WB3 WB4 WB5 WB6 WB7 VDD (+V, Pin 3) Supply voltage positive terminal. VALUE 1 2 4 8 16 32 64 128 ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VSS) SYMBOL VALUE DC Supply Voltage VDD +19 Voltage (Any Pin) VIN VSS - 0.3 to VDD + 0.3 Operating Temperature TA -20 to +85 Storage Temperature TSTG -65 to +150 UNIT V V °C °C ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) Characteristic SYMBOL Supply Voltage VDD Supply Current IDD Input Voltages: Reset, Trigger Low VTL Reset, Trigger High VTH Reset, Trigger Hysteresis All other inputs, Low VIL All other inputs, High VIH Input Currents: PSCLS Low IPL PSCLS High IPH A, B Low IML A, B High All other inputs, Low IMH IIL All other inputs, High IIH Output Current: OUT Sink IOSNK OUT Source IOSRC 7211N-072009-3 3.0 10.0 18.0 Min 3.0 - -20°C Max 18.0 66 252 540 Min 3.0 - +25°C Max 18.0 55 210 450 Min 3.0 - +85°C Max 18.0 44 168 360 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 2.2 6.1 9.7 0.7 2.2 3.9 1.9 6.5 13.3 0.8 2.3 3.9 1.1 4.5 10.6 - 2.1 6.0 10.5 0.7 2.2 3.9 1.9 6.5 13.3 0.75 2.2 3.8 1.1 4.5 10.6 - 2.0 5.9 11.0 0.7 2.2 3.9 1.9 6.5 13.3 0.7 2.1 3.7 1.1 4.5 10.6 - V V V V V V V V V V V V V V V 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 - 3.2 31 84 9.8 31 85 6.0 59 157 100 100 33 120 121 - 2.5 24 65 7.5 24 65 5.0 48 128 100 100 27 105 107 - 1.9 18 49 5.8 18.2 49 4.0 38 98 200 200 23 81 82 µA µA µA µA µA µA µA µA µA nA nA µA µA µA 3.0 10.0 18.0 3.0 10.0 18.0 13.2 26 30.7 4.1 7.2 8.2 - 10.1 19.7 23.6 3.2 5.5 6.3 - 7.0 15 17 2.1 4.1 4.6 - mA mA mA mA mA mA VDD Unit V µA µA µA Condition with the clock off and all inputs floating. - Input at VSS Input at VDD Input at VSS Input at VDD Input at VSS Input at VDD Vo = +0.5V Vo = VDD - 0.5V ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) (Con’t) Characteristic SYMBOL Switching Characteristics (See Fig. 3) RC Oscillator Frequency fosc External Clock or Crystal Oscillator Frequency fext fext TRIG Set-Up Time A, B Set-Up Time WB0 - WB7 Set-Up Time t1 t2 t3 Clock to Out Delay t4 VDD 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 Max Min Max Min Max - 1.8 4.5 8.0 2.6 5.3 5.9 7.2 16.0 15.9 - 1.4 3.4 4.0 2.0 4.0 4.5 5.5 12.8 13.0 - 1.05 2.6 3.0 1.52 3.0 3.5 4.2 9.7 9.1 MHz MHz MHz MHz MHz MHz MHz MHz MHz 39 0 0 - 284 98 87 50 0 0 - 375 130 115 66 0 0 - 495 172 152 ns ns ns ns ns ns - 3.0 10.0 18.0 Unit Min Condition For prescale factor S = 1 or 3,000 or 3,600 S = 32,768 or 32,768 x 60 CL = 50pF +V 500k A 1 MODE REG +V 500k B 2 EDGE DETECT TRIG 18 CONTROL LOGIC LATCH 9 BUF OUT 500k RESET 7 CLOCK/RC/XTLI 500k 4 CLOCK LATCH/TIMER 8 10-17 500k MUX OSC PRESCALER XTLO (LS7212N) 5 RCS/CLKS (LS7211N) 5 500k +V +V 1M PSCLS 6 -V (Gnd) 3-STATE DECODER 1M FIGURE 2. LS7211N / LS7212N BLOCK DIAGRAM 7211N-072009-4 (8) 3 VDD 8 VSS WB7-WB0 t0 Clock t1 t1 TRIG t2 A = 0, B = 1, Delayed Operate A, B Programmed Delay t3 t4 WB0-WB7 OUT Immediate Release Note 1. TRIG input is clocked in by the negative edge of external clock. Note 2. Inputs A, B and WB0 - WB7 are sampled only at a TRIG input transition and ignored at all other times. Note 3. OUT is switched by the positive edge of the external clock. FIGURE 3. INPUT/OUTPUT TIMING TRIG F RESET OUT(OS) C OUT(DO) OUT(DR) D OUT(DD) G A B H E A. Turn-on delay in DO and DD modes; Pulse-width in OS mode. B. Turn-off delay in DR and DD modes. C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because TRIG switches back low before turn-on delay has timed out. D. Turn-off delay in DR mode. E. Turn-on delay in DO and DD modes; pulse-width in OS mode. F. No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels. G. Time-outs aborted and OUT forces high by RESET. H. After the removal of RESET, OUT switches to the inverse polarity of TRIG immediately (DR) or after the timeout (DO, DD). No effect in OS. FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET 7211N-061906-5 +V 470k 3 VDD +V 5 25pF 5 CRYSTAL XTLO 10M RCS/CLKS LS7211N LS7212N 4 4 XTLI CLOCK 25pF 10k ƒ 4 0.1µF 4 RC CLOCK LS7212N LS7211N FIGURE 6. MULTI-TIMER WITH SINGLE CRYSTAL TIME-BASE +V V SS 3 8 ƒ= V DD 1 -6 10 x 10 x 0.1 x 10 = 1kHz LS7211N 3 1M 4 120VAC CLOCK 200pF FIGURE 5. RC- Oscillator Connection V SS 8 FIGURE 7. DRIVING CLOCK INPUT FROM THE AC LINE +V 3 V DD * * 8 10-17 2 1, 2 3 * * WB0-WB7 A, B LS7211N 18 TRIGGER 4 ƒ TRIG 8 2 10-17 WB0-WB7 1, 2 A, B LS7211N OUT 9 CLOCK 18 4 TRIG OUT CLOCK Vss 8 * Connect for desired delay and mode FIGURE 8. DELAY EXTENSION BY CASCADING 7211N-062209-6 V DD Vss 8 9 OUT 1 2 TRIGGER IN 18 4 25pF ƒ 25pF 470k +V S1 +V A V DD B WB0 TRIG WB1 XTLI WB2 WB3 10M 5 6 WB4 XTLO WB5 WB6 PSCLS WB7 +V 7 8 OUTPUT 9 LS7212N RESET 3 17 1s/1m 16 2s/2m 15 4s/4m 14 8s/8m 13 16s/16m 12 32s/32m 11 64s/64m 10 128s/128m s = seconds m = minutes Vss OUT NOTE : Crystal Frequency, ƒ = 32,768Hz Switch: S1 low: Delay increment = 1s; Maximum Delay = 255s S1 high: Delay increment = 1m; Maximum Delay = 255m FIGURE 9. PROGRAMMABLE ACCURATE REAL-TIME DELAY GENERATION The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7211N-052606-7 +V 3 1 2 V DD A B WB0 WB1 WB2 4 ƒi +V 7 CLOCK LS7212N 9 WB4 RESET WB5 TRIG WB6 18 ƒo WB3 OUT WB7 17 16 15 14 13 12 11 10 Vss 8 CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1 In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can be obtained according to the equation: ƒo = ƒi W+2 where W (weighting factor) = 0 to 255 The ƒo pulse width is non-symmetrical (non-50% duty -cycle) CASE 2. MODE = DD; PRESCALE FACTOR, S = 1 In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can be obtained according to the equation: ƒo = ƒi 2 (W + 1) where W (weighting factor) = 0 to 255 The ƒo pulse widths are symmetrical with 50% duty -cycle EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2 ƒi ƒo Case 1, Mode = DO; ÷4 ƒo Case 2, Mode = DD; ÷6 FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER 7211N-052606-8