TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 D D D D D 262 144 by 8 bit s 131 072 by 16 bits Array-Blocking Architecture – One 16K-Byte Protected Boot Block – Two 8K-Byte Parameter Blocks – One 96K-Byte Main Block – One 128K-Byte Main Block – Top or Bottom Boot Locations ’28F200Axy Offers a User-Defined 8-Bit (Byte) or 16-Bit (Word) Organization ’28F002Axy Offers Only the 8-Bit (Byte) Organization Maximum Access / Minimum Cycle Time – Commercial and Extended 10% or 3.3-V VCC 0.3 V 5-V VCC 5V 3.3 V ’28F002Axy/200Axy60 60 ns 110 ns ’28F002Axy/200Axy70 70 ns 130 ns ’28F002Axy/200Axy80 80 ns 150 ns – Automotive 5-V VCC 10% ’28F200Axy70 70 ns ’28F200Axy80 80 ns ’28F200Axy90 90 ns (x = S, E, F, Z, or M Depending on VCC/VPP Voltage Configuration) (y = T for Top or B for Bottom Boot-Block Configuration) 100 000- and 10 000-Program/ Erase-Cycle Versions Three Temperature Ranges – Commercial . . . 0°C to 70°C – Extended . . . – 40°C to 85°C – Automotive . . . – 40°C to 125°C Industry Standard Packages Offered in – 40-pin Thin Small-Outline Package (TSOP) – 44-pin Plastic Small-Outline Package (PSOP) – 48-pin TSOP Low Power Dissipation ( VCC = 5.5 V ) – Active Read . . . 330 mW ( Byte-Read) – Active Write . . . 248 mW ( Byte-Write) – Active Read . . . 330 mW ( Word-Read) – Active Write . . . 248 mW ( Word-Write) – Block-Erase . . . 165 mW – Standby . . . 0.72 mW (CMOS-Input Levels) DBJ PACKAGE ( TOP VIEW ) Organization . . . " VPP DU/WP NC A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 " " D D D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15/A –1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC PIN NOMENCLATURE A0 – A16 A17 BYTE DQ0 – DQ14 DQ15/A –1 E G NC RP VCC VPP VSS W DU/WP D D D D D Address Inputs Address Input (40-Pin Package Only) Byte-Enable Data In / Out Data In / Out (Word-Wide Mode), Low-Order Address (Byte-Wide Mode) Chip-Enable Output-Enable No Internal Connection Reset / Deep Power-Down Power Supply Power Supply for Program / Erase Ground Write-Enable Do Not Use for AMy or AZy/Write-Protect Fully Automated On-Chip Erase and Word / Byte Program Operations Write-Protection for Boot Block Industry Standard Command-State Machine (CSM) – Erase Suspend/Resume – Algorithm-Selection Identifier Five Different Combinations of Supply Voltages Offered All Inputs / Outputs TTL-Compatible Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 40-PIN DCD PACKAGE ( TOP VIEW ) A16 A15 A14 A13 A12 A11 A9 A8 W RP VPP DU/WP NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 G VSS E A0 48-PIN DCD PACKAGE (TOP VIEW) A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP VPP DU/WP NC NC NC A7 A6 A5 A4 A3 A2 A1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 A16 BYTE VSS DQ15 / A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 Table of Contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 device symbol nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 programming operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 automatic power-saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block-memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 reset / deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . 15 boot-block data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 power supply detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 parameter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 common electrical parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 command-state machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . . . 8 TMS28F002ASy and TMS28F200ASy . . . . . . . . . . . . . . . . . . . . . . 22 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TMS28F002AEy and TMS28F200AEy . . . . . . . . . . . . . . . . . . . . . . 32 command definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TMS28F002AMy and TMS28F200AMy . . . . . . . . . . . . . . . . . . . . . 42 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TMS28F002AFy and TMS28F200AFy . . . . . . . . . . . . . . . . . . . . . . 50 byte-wide or word-wide mode selection . . . . . . . . . . . . . . . . . . 11 TMS28F002AZy and TMS28F200AZy . . . . . . . . . . . . . . . . . . . . . . 60 command-state-machine operations . . . . . . . . . . . . . . . . . . . . 13 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . 70 clear status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NO TAG description The TMS28F200Axy is a 262 144 by 8-bit / 131 072 by-16 bit (2 097 152-bit), boot-block flash memory that can be electrically block-erased and reprogrammed. The TMS28F200Axy is organized in a blocked architecture consisting of: D D D D One 16K-byte protected boot block Two 8K-byte parameter blocks One 96K-byte main block One 128K-byte main block The device can be ordered in five different voltage configurations (see Table 1). Operation as a 256K-byte (8-bit) or a 128K-word (16-bit) organization is user-definable. The TMS28F002Axy is offered in a 256K-byte organization only. The operation for this device is the same as the TMS28F200Axy and is offered in the same voltage configurations. TMS28F002Axy can be substituted for the byte-wide TMS28F200Axy, with the latter being the generic name for this device family. Embedded program and block-erase functions are fully automated by the on-chip write-state machine (WSM), thereby simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM status can be monitored by an on-chip status register to determine the progress of program / erase tasks. The device features user-selectable block-erasure. The configurations are as follow: D D The TMS28F002ASy and the TMS28F200ASy configurations have the auto-select feature that allows alternative read and program / erase voltages. Memory reads can be performed using 3.3-V VCC for optimum power consumption or at 5-V VCC, for device performance. Erasing or programming the device can be accomplished with 5-V VPP, which eliminates having to use a 12-V source and / or in-system voltage converters. Alternatively, 12-V VPP operation exists for systems that already have a 12-V power supply, which provides faster programming and erasing times. These configurations are offered in two different temperature ranges: 0°C to 70°C and – 40°C to 85°C. The TMS28F002AEy and the TMS28F200AEy configurations offer the auto-select feature of the TMS28F200ASy with an extended VCC to a low 2.7-V to 3.6-V range (3-V nominal). Memory reads can be performed using a 3-V VCC, allowing for more efficient power consumption than the ’ASy device. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 D D D The TMS28F002AMy and TMS28F200AMy configurations offer a 3-V or 5-V memory read with a 12-V program and erase. These configurations are intended for low 3.3-V reads and the fast programming offered with the12-V VPP and 5-V VCC. These configurations are offered in two different temperature ranges: 0°C to 70°C and – 40°C to 85°C. The TMS28F002AFy and TMS28F200AFy configurations offer a 5-V memory read with a 5-V or 12-V program and erase. These configurations are intended for systems using a single 5-V power supply. The configurations are offered in three temperature ranges: 0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C. The TMS28F002AZy and TMS28F200AZy configurations offer a 5-V memory read with a 12-V program and a 12-V erase for fast programming and erasing times. These configurations are offered in three temperature ranges: 0°C to 70°C,– 40°C to 85°C, and – 40°C to 125°C. All configurations of the TMS28F200Axy are offered in the 44-pin plastic small-outline package (PSOP) and the 48-pin thin small-outline package (TSOP). The TMS28F002Axy is offered in a 40-pin TSOP only. Both the 40-pin and 48-pin TSOP are offered for the 0°C to 70°C and – 40°C to 85°C temperature ranges only. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 device symbol nomenclature TMS28F200AS T 60 C DBJ L Temperature Range Designator L = 0°C to 70°C E = – 40°C to 85°C Q = – 40°C to 125°C Program/Erase Endurance C = 100 000 Cycles B = 10 000 Cycles Boot-Block Location Indicator T = Top Location B = Bottom Location S E M F Z Package Designator DBJ = 44-Pin PSOP DCD= 40-Pin TSOP (F002 only) DCD= 48-Pin TSOP (F200 only) Speed Designator 60 = 60 ns 70 = 70 ns 80 = 80 ns 90 = 90 ns = (3.3 V ± 0.3 V or 5 V ± 10%) VCC and (5 V ± 10% or 12 V ± 5%) VPP =(2.7 V to 3.6 V or 5 V ± 10%) VCC and (5 V ± 10% or 12 V ± 5%) VPP = (3.3 V ± 0.3 V or 5 V ± 10%) VCC and 12 V ± 5% VPP = 5 V ± 10% VCC and (5 V ± 10% or 12 V ± 5%) VPP = 5 V ± 10% VCC and 12 V ± 5% VPP Organization 200 = 128K x 16-bits or 256K x 8 bits 002 = 256K x 8 bits Table 1. VCC -/ VPP-Voltage Configurations† DEVICE CONFIGURATION READ VOLTAGE (VCC) PROGRAM/ERASE VOLTAGE (VPP) OPERATING FREE-AIR TEMPERATURE (TA) ACCESS SPEEDS 5 V (3.3 V) VCC TMS28F200ASy 3.3 V ± 0.3 V or 5 V ± 10 % 5 V ± 10% or 12 V ± 5 % 0°C to 70°C 60(110), 70(130), 80(150) ns – 40°C to 85°C 60(110), 70(130), 80(150) ns TMS28F200AEy 2.7 V to 3.6 V or 5 V ± 10 % 5 V ± 10% or 12 V ± 5 % 0°C to 70°C 60(110), 70(130), 80(150) ns – 40°C to 85°C 60(110), 70(130), 80(150) ns TMS28F200AMy 3.3 V ± 0.3 V or 5 V ± 10 % 12 V ± 5 % TMS28F200AFy TMS28F200AZy 5 V ± 10 % 5 V ± 10 % 5 V ± 10% or 12 V ± 5 % 12 V ± 5 % 0°C to 70°C 60(110), 70(130), 80(150) ns – 40°C to 85°C 60(110), 70(130), 80(150) ns 0°C to 70°C 60, 70, 80 ns – 40°C to 85°C 60, 70, 80 ns – 40°C to 125°C‡ 70, 80, 90 ns 0°C to 70°C 60, 70, 80 ns – 40°C to 85°C 60, 70, 80 ns – 40°C to 125°C‡ 70, 80, 90 ns † All configurations are available in the TMS28F002Axy (8-bit only) and top or bottom boot. ‡ Only the 44-pin PSOP is offered in the – 40°C to 125°C temperature range. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 functional block diagram DQ8 – DQ15/A –1† DQ0 – DQ7 8 8 8 DQ15/A –1 Input Buffer Output Buffer Output Buffer Input Buffer Input Buffer Data Register Identification Register Output Multiplexer Status Register A0 – 17 A16 Input Buffer PowerReduction Control Data Comparator I/O Logic E W G RP WP Command State Machine Write State Machine BYTE† Program/ Erase Voltage Switch VPP Address Latch Y Decoder Address Counter X Decoder Y Gating / Sensing 16K-Byte Boot Block 8K-Byte 8K-Byte Parameter Parameter Block Block 96K-Byte Main Block 128K-Byte Main Block † Not used on ’F002 model architecture The TMS28F200Axy uses a blocked architecture to allow independent erasure of selected memory blocks. The block to be erased is selected by using any valid address within that block. block-memory maps The TMS28F200Axy is available with the block architecture mapped in either of two configurations: the boot block located at the top or at the bottom of the memory array, as required by different microprocessors. The TMS28F200AxB (bottom boot block ) is mapped with the 16K-byte boot block located at the low-order address range (00000h to 01FFFh). The TMS28F200AxT (top boot block ) is inverted with respect to the TMS28F200AxB with the boot block located at the high-order address range (1E000h to 1FFFFh). Both of these address ranges are for word-wide mode. The TMS28F002Axy is mapped as the 8-bit configuration of the TMS28F200Axy, except that the least signficant bit (LSB) is A0 instead of A–1. Figure 1 and Figure 2 show the memory maps for these configurations. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 block memory maps (continued) 16-bit Configuration Address Range Boot Block 16K Addresses Boot Block 8K Addresses 1FFFFh Parameter Block 8K Addresses Parameter Block 4K Addresses Parameter Block 8K Addresses Parameter Block 4K Addresses Main Block 96K Addresses Main Block 48K Addresses Main Block 128K Addresses Main Block 64K Addresses Address Range 8-Bit Configuration 3FFFFh 3C000h 3BFFFh 3A000h 39FFFh 38000h 37FFFh 20000h 1FFFFh 00000h DQ15/A –1 Is LSB Address 1E000h 1DFFFh 1D000h 1CFFFh 1C000h 1BFFFh 10000h 0FFFFh 00000h A0 Is LSB Address NOTE A: The TMS28F002AxT is mapped the same way as the 8-bit configuration of the TMS28F200AxT and the LSB is A0. Figure 1. TMS28F200AxT ( Top Boot Block ) Memory Map (See Note A) Address Range 8-Bit Configuration 3FFFFh 20000h 1FFFFh 08000h 07FFFh 06000h 05FFFh 04000h 03FFFh 00000h 16-Bit Configuration Main Block 128K Addresses Main Block 64K Addresses Main Block 96K Addresses Main Block 48K Addresses Parameter Block 8K Addresses Parameter Block 4K Addresses Parameter Block 8K Addresses Parameter Block 4K Addresses Boot Block 16K Addresses Boot Block 8K Addresses DQ15/A –1 Is LSB Address Address Range 1FFFFh 10000h 0FFFFh 04000h 03FFFh 03000h 02FFFh 02000h 01FFFh 00000h A0 Is LSB Address NOTE A: The TMS28F002AxB is mapped the same way as the 8-bit configuration of the TMS28F200AxB and the LSB is A0. Figure 2. TMS28F200AxB (Bottom-Boot Block ) Memory Map (See Note A) boot-block data protection The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data in this block can be secured by using different combinations of the reset / deep power-down pin (RP), the write-protect pin (WP), and VPP supply levels. Table 2 shows a listing of these combinations. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 parameter block Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data. Alternatively, the parameter blocks can be used for additional boot-block or main-block data. If a parameter block is used to store additional boot-block data, caution must be exercised because the parameter block does not have the boot-block data-protection safety feature. main block Primary memory on the TMS28F200Axy is located in two main blocks. One of the blocks has storage capacity for 128K bytes and the other block has storage capacity for 96K bytes. data protection Data is secured or unsecured by using different combinations of the reset / deep power-down pin (RP), the write-protect pin (WP), and VPP supply levels. Table 2 shows a listing of these combinations. There are two configurations to secure the entire memory against the inadvertent alteration of data. The VPP supply pin can be held below the VPP lock-out voltage level (VPPLK) or the reset / deep power-down pin (RP) can be pulled to a logic-low level. If RP is held low, the device resets—which means that it powers down, and therefore, cannot be read. Typically this pin is tied to the system reset for additional protection during system power up. The boot-block sector has an additional security feature through the WP pin on the ’ASy, ’AEy, and ’AFy devices. When the RP pin is at a logic-high level, the WP pin controls whether the boot-block sector is protected. When WP is held at the logic-low level, the boot block is protected. When WP is held at the logic-high level, the boot block is unprotected, along with the rest of the other sectors. Alternatively, the entire memory for all voltage configurations can be unprotected by pulling the RP pin to VHH (12 V). Table 2. Data-Protection Combinations ’ASy, ’AEy, or ’AFy DATA-PROTECTION PROVIDED All blocks locked All blocks locked (reset) All blocks unlocked ’AMy or ’AZy VPP VIL RP WP† X X VIL VHH VIH > VPPLK RP WP† X VPP VIL X X X X VIL X X VIH VHH VHH X Only boot block locked > VPPLK VIH VIL VHH VIH X † For TMS28F200AZy and TMS28F200AMy (12-V VPP) products, the WP pin is disabled and can be left floating. To unlock blocks, RP must be at VHH. command-state machine (CSM) Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface between the external microprocessor and the internal write state machine (WSM). The available commands are listed in Table 3 and the descriptions of these commands are listed in Table 4. When a program or erase command is issued to the CSM, the WSM controls the internal sequences and the CSM only responds to status reads. After the WSM completes its task, the write status bit (WSM) (SB7) is set to a logic-high level, allowing the CSM to respond to the full command set again. operation Device operations are selected by entering standard JEDEC 8-bit command codes with conventional microprocessor timing into an on-chip CSM through I/O pins DQ0 – DQ7. When the device is powered up, internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. Table 3 lists the CSM codes for all modes of operation. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 operation (continued) The on-chip status register allows the progress of various operations to be monitored. The status register is interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data on I/O pins DQ0 – DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7. Table 3. Command-State Machine Codes for Device Mode Selection COMMAND CODE ON DQ0 – DQ7† 00h 10h 20h 40h 50h 70h 90h B0h D0h FFh DEVICE MODE Invalid / Reserved Alternate Program Setup Block-Erase Setup Program Setup Clear Status Register Read Status Register Algorithm Selection Erase-Suspend Erase-Resume/Block-Erase Confirm Read Array † DQ0 is the least significant bit. DQ8 – DQ15 can be any valid 2-state level. command definition Once a specific command code has been entered, the WSM executes an internal algorithm generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles. Following the read-algorithm-selection-code command, two read cycles are required to access the manufacturer-equivalent code and the device-equivalent code. The codes are shown in Table 6, Table 7, and Table 8. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 command definition (continued) Table 4. Command Definitions FIRST BUS CYCLE BUS CYCLES REQUIRED OPERATION Read Array 1 Write Read Algorithm-Selection Code 2 Read Status Register 2 Clear Status Register 1 COMMAND SECOND BUS CYCLE CSM INPUT OPERATION ADDRESS DATA IN / OUT X FFh Read X Data Out Write X 90h Read A0 M/D Write X 70h Read X SRB Write X 50h 40h or 10h Write PA PD ADDRESS Read Operations Program Mode Program Setup / Program (byte / word) 2 Write PA Erase Operations Block-Erase Setup/ Block-Erase Confirm 2 Write BEA 20h Write BEA D0h Erase-Suspend/ Erase-Resume 2 Write X B0h Write X D0h Legend: BEA M/D PA PD SRB X Block-erase address. Any address selected within a block selects that block for erase. Manufacturer-equivalent/ device-equivalent code Address to be programmed Data to be programmed at PA Status-register data byte that can be found on DQ0 – DQ7 Don’t care status register The status register allows determination of whether the state of a program/erase operation is pending or complete. The status register is monitored by writing a read-status command to the CSM and reading the resulting status code on I/O pins DQ0 – DQ7. This is valid for operation in either the byte-wide or word-wide mode. When writing to the CSM in word-wide mode, the high-order I/O pins (DQ8 – DQ15) can be set to any valid 2-state level. When reading the status bits during a word-wide read operation, the high-order I/Os (DQ8– DQ15) are set to 00h internally, so the user needs to interpret only the low-order I/O pins (D0 – DQ7). After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register input change during a status-register read. To ensure that the status-register output contains updated status data, E or G must be toggled for each subsequent status read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the status-register bits and their functions. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 status register (continued) Table 5. Status-Register Bit Definitions and Functions STATUS BIT FUNCTION Write-state-machine status (WSMS) SB7 DATA COMMENTS 1 = Ready y 0 = Busy If SB7 = 0 (busy), the WSM has not completed an erase or programming operation. If SB7 = 1 (ready), other polling operations can be performed. Until this occurs, the other status valid If the WSM status bit shows busy (0), (0) the user bits are not valid. must toggle E or G periodically to determine when the WSM has completed an operation (SB7 = 1) since SB7 is not automatically updated at the completion of a WSM task. SB6 Erase-suspend status (ESS) 1 = Erase suspended 0 = Erase in progress or completed When an erase-suspend command is issued, the WSM halts execution and sets the ESS bit high (SB6 = 1), indicating that the erase operation has been suspended. The WSM status bit also is set high (SB7 = 1), indicating that the erase-suspend operation has been completed successfully. The ESS bit remains at a logic-high level until an erase-resume command is input to the CSM (code D0h ). SB5 Erase status (ES) 1 = Block-erase error 0 = Block-erase good SB5 = 0 indicates that a successful block-erasure has occurred. SB5 = 1 indicates that an erase error has occurred. In this case, the WSM has completed the maximum allowed erase pulses determined by the internal algorithm, but this was insufficient to completely erase the device. SB4 Program status (PS) 1 = Byte/word-program error 0 = Byte/word-program good SB4 = 0 indicates successful programming has occurred at the addressed block location. SB4 = 1 indicates that the WSM was unable to program the addressed block location correctly. SB3 VPP status (VPPS) 1 = Program abort: VPP range error 0 = VPP good SB3 provides information on the status of VPP during programming. If VPP is lower than VPPL after a program or erase command has been issued, SB3 is set to a 1, indicating that the programming operation is aborted. If VPP is between VPPH and VPPL, SB3 is not set. SB2 – SB0 Reserved SB2 – SB0 are masked out when reading the status register. byte-wide or word-wide mode selection The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8 – DQ15, and a lower-half that outputs data through DQ0 – DQ7. Device operation in either byte-wide or word-wide mode is user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device is in the word-wide mode and data is written to or read from I/O pins DQ0 – DQ15. When BYTE is at a logic-low level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0 – DQ7. In the byte-wide mode, I/O pins DQ8 – DQ14 are placed in the high-impedance state and DQ15/A –1 becomes the low-order address pin and selects either the upper- or lower-half of the array. Array data from the upper half (DQ8 – DQ15) and the lower half (DQ0 – DQ7) are multiplexed to appear on DQ0 – DQ7. Table 6, Table 7, and Table 8 summarize operation modes. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 byte-wide or word-wide mode selection (continued) Table 6. Operation Modes for Word-Wide Mode (BYTE = VIH) (see Note 1) MODE WP E G RP W A9 A0 X VIL VIL VIH VIH X X VPP X X VIL VIL VIH VIH VID VIL X Read Algorithm-selection mode DQ0 – DQ15 Data out Manufacturer-equivalent code 0089h Device-equivalent code 2274h (top boot block) X VIL VIL VIH VIH VID VIH X Output disable X VIH X VIH VIH VIH X X X Hi-Z X VIL VIH X X Standby X X X Hi-Z X VIL VIH or VHH X X X X Hi-Z X VPPL or VPPH Reset / deep power-down X VIL or VIH Write (see Note 2) VIL VIH VIL X Device-equivalent code 2275h (bottom boot block) Data in NOTES: 1. X = don’t care 2. When writing commands to the ’28F200Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations). Table 7. Operation Modes for Byte-Wide Mode (BYTE = VIL ) (see Note 1) MODE WP E G RP W A9 A0 VPP DQ15 / A –1 DQ8 – DQ14 Read lower byte X VIL VIL VIH VIH VIH VIH X X Data out X X X VIL VIH Hi-Z X VIL VIL X Read upper byte Hi-Z Data out X VIL VIL VIH VIH VID VIL X X Hi-Z Manufacturer-equivalent code 89h Algorithm-selection g mode DQ0 – DQ7 Device-equivalent q code 74h (top boot block) X VIL VIL VIH VIH VID VIH X X Hi Z Hi-Z Output disable X VIH X VIH VIH VIH X X X X Hi-Z Hi-Z X VIL VIH X Standby X X X X Hi-Z Hi-Z Reset / deep power-down X X X VIL X X X X X Hi-Z Hi-Z VIL or VIH VIL VIH VIH or VHH VIL X X VPPL or VPPH X Hi-Z Data in Write (see Note 2) Device-equivalent code 75h (bottom boot block) NOTES: 1. X = don’t care 2. When writing commands to the ’28F200Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations). 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 byte-wide or word-wide mode selection (continued) Table 8. Operation Modes for ’28F002Axy (see Note 1) MODE Read WP E G RP W A9 A0 X VIL VIL VIH VIH X X VPP X X VIL VIL VIH VIH VID VIL X Algorithm-selection mode DQ0 – DQ7 Data out Manufacturer-equivalent code 89h Device-equivalent code 7Ch (top boot block) X VIL VIL VIH VIH VID VIH X Output disable X VIH X VIH VIH VIH X X X Hi-Z X VIL VIH X X Standby X X X Hi-Z X VIL VIH or VHH X X X X Hi-Z X VPPL or VPPH Reset / deep power-down Write (see Note 3) X VIL or VIH VIL VIH VIL X Device-equivalent code 7Dh (bottom boot block) Data in NOTES: 1. X = don’t care 3. When writing commands to the ’28F002Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations). command-state-machine operations The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on DQ0– DQ7 (see Table 3 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences and the CSM responds only to status reads. During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range. For data protection, it is recommended that RP be held at a logic-low level during a CPU reset. clear status register The internal circuitry can set only the VPP status (SB3), the program status bit (SB4), and the erase status bit (SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to clear these status bits and synchronize to internal operations. When the status bits are cleared, the device returns to the read-array mode. read operations There are three read operations available: read array, read algorithm-selection code, and read status register. D read array The array level is read by entering the command code FFh on DQ0 – DQ7. Control pins E and G must be at a logic-low level ( VIL ) and W and RP must be at a logic-high level ( VIH ) to read data from the array. Data is available on DQ0 – DQ15 (word-wide mode) or DQ0 – DQ7 (byte-wide mode ). Any valid address within any of the blocks selects that block and allows data to be read from the block. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 read operations (continued) D read algorithm-selection code Algorithm-selection codes are read by entering command code 90h on DQ0 – DQ7. Two bus cycles are required for this operation: the first to enter the command code and a second to read the device-equivalent code. Control pins E and G must be at a logic-low level ( VIL ), and W and RP must be at a logic-high level ( VIH). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on DQ0– DQ7 with A0 at a logic-low level ( VIL ). The device-equivalent code is obtained when A0 is set to a logic-high level ( VIH). Alternatively, the manufacturer- and device-equivalent codes can be read by applying VID (nominally 12 V ) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are “don’t cares” (see Table 4, Table 6, Table 7, and Table 8). D read status register The status register is read by entering the command code 70h on DQ0 – DQ7. Control pins E and G must be at a logic-low level ( VIL ) and W and RP must be at a logic-high level ( VIH ). Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. In a given read cycle, status register contents are updated on the falling edge of E or G, whichever occurs last within the cycle. programming operations There are two CSM commands for programming: program setup and alternate program setup (see Table 3 ). After the desired command code is entered, the WSM takes over and correctly sequences the device to complete the program operation. During this time, the CSM responds only to status reads until the program operation has been completed, after which all commands to the CSM become valid again. Once a program command has been issued, the WSM normally cannot be interrupted until the program algorithm is completed (see Figure 3 and Figure 4). Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain in the appropriate VPP voltage range, as shown in the recommended operating conditions table for the product. Note that different combinations of RP, WP and VPP pin voltage levels ensure that data in certain blocks are secure, and, therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared during a program operation. If 1s are programmed, the memory cell contents do not change and no error occurs. A program-setup command can be aborted by writing FFh ( in byte-wide mode) or FFFFh ( in word-wide mode) during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads. When the SB7 is set to a logic-high level, signifying the nonprogram operation is terminated, all commands to the CSM become valid again. erase operations There are two erase operations that can be performed by the TMS28F002Axy and TMS28F200Axy devices: block-erase and erase-suspend / erase-resume. An erase operation must be used to initialize all bits in an array block to 1s. After block-erase-confirm is issued, the CSM responds only to status reads or erase-suspend commands until the WSM completes its task. D block erasure Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is accomplished only by blocks; data at single-address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Note that different combinations of RP, WP, and VPP pin voltage levels ensure that data in certain blocks are secure and, therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A two-command erase sequence protects against accidental erasure of memory contents. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 erase operations (continued) Erase-setup and erase-confirm commands are latched on the rising edge of E or W, whichever occurs first. Block addresses are latched during the block-erase-confirm command on the rising edge of E or W (see Figure 14 and Figure 15). When the block-erase-confirm command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is performed to ensure that all bits are erased correctly. Monitoring of the erase operation is possible through the status register (see the “read status register” paragraph in the “read operations” subsection). D erase-suspend/erase-resume During the execution of an erase operation, the erase-suspend command (B0h ) can be entered to direct the WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the read-array, read-status-register, and erase-resume commands. During the erase-suspend operation, array data should be read from a block other than the one being erased. To resume the erase operation, an erase-resume command (D0h ) must be issued to cause the CSM to clear the suspend state previously set (see Figure 5 and Figure 6). automatic power-saving mode Substantial power savings are realized during periods when the array is not being read and the device is in the active mode. During this time, the device switches to the automatic power-saving (APS) mode. When the device switches to this mode, ICC is typically reduced from 40 mA to 1 mA (IOUT = 0 mA). The low level of power is maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control pins toggle within approximately a 200-ns time-out period. At least one transition on E must occur after power up to activate this mode. reset/ deep power-down mode Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, a much lower ICC value or power is achievable. This is important in portable applications where extended battery life is of major concern. A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum of td(RP) is required before data is valid, and a minimum of trec(RPHE) and trec(RPHW) in deep power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM is reset and the status register is cleared, effectively eliminating accidental programming to the array during system reset. After restoration of power, the device does not recognize any operation command until RP is returned to a VIH or VHH level. Should RP go low during a program or erase operation, the device powers down and, therefore, becomes nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the operation be performed again after power restoration. power supply detection RP must be connected to the system reset / power down signal to ensure that proper synchronization is maintained between the CPU and the flash memory operating modes. The default state after power up and exit from deep power-down mode is read array. RP also is used to indicate that the power supply is stable so that the operating supply voltage can be established (3 V, 3.3 V, or 5 V). Figure 10 shows the proper power-up sequence. To reset the operating supply voltage, the device must be completely powered off (VCC = 0 V) before the new supply voltage is detected. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 Start BUS OPERATION Issue Program-Setup Command and Byte Address Issue Byte Address/Data COMMAND Write Write program setup Data = 40h or 10h Addr = Address of byte to be programmed Write Write data Data = Byte to be programmed Addr = Address of byte to be programmed Read Status-Register Bits SB7 = 1 ? Read Status-register data. Toggle G or E to update status register Standby Check SB7 1 = Ready, 0 = Busy No Yes Full Status-Register Check (optional) COMMENTS Repeat for subsequent bytes. Write FFh after the last byte-programming operation to reset the device to read-array mode. See Note A Byte-Program Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits SB3 = 0 ? No BUS OPERATION VPP Range Error Standby Byte-Program Failed Standby COMMAND Yes SB4 = 0 ? No COMMENTS Check SB3 1 = Detect VPP low (see Note B) Check SB4 1 = Byte-program error (see Note C) Yes Byte-Program Passed NOTES: A. Full status-register check can be done after each byte or after a sequence of bytes. B. SB3 must be cleared before attempting additional program / erase operations. C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts. Figure 3. Automated Byte-Programming Flow Chart 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 BUS OPERATION Start Read Status-Register Bits Write program setup Data = 40h or 10h Addr = Address of word to be programmed Write Write data Data = Word to be programmed Addr = Address of word to be programmed Read Status-register data. Toggle G or E to update status register. Standby Check SB7 1 = Ready, 0 = Busy No SB7 = 1 ? COMMENTS Write Issue Program-Setup Command and Word Address Issue Word Address/Data COMMAND Repeat for subsequent words. Write FFh after the last word-programming operation to reset the device to read-array mode. Yes Full Status-Register Check (optional) See Note A Word-Program Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits SB3 = 0 ? BUS OPERATION No No COMMENTS Standby Check SB3 1 = Detect VPP low (see Note B) Standby Check SB4 1 = Word-program error (see Note C) VPP-Range Error Yes SB4 = 0 ? COMMAND Word-Program Failed Yes Word-Program Passed NOTES: A. Full status-register check can be done after each word or after a sequence of words. B. SB3 must be cleared before attempting additional program / erase operations. C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts. Figure 4. Automated Word-Programming Flow Chart POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 BUS OPERATION Start COMMAND COMMENTS Write Write erase setup Data = 20h Block Addr = Address within block to be erased Write Erase Data = D0h Block Addr = Address within block to be erased Issue Erase-Setup Command and Block Address Issue Block-Erase-Confirm Command and Block Address Read Status-Register Bits No SB7 = 1 ? No Erase Suspend ? EraseSuspend Loop Status-register data. Toggle G or E to update status register Standby Check SB7 1 = Ready, 0 = Busy Yes Yes Full Status-Register Check (optional) Read See Note A Repeat for subsequent blocks. Write FFh after the last block-erase operation to reset the device to read-array mode Block-Erase Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits SB3 = 0 ? BUS OPERATION No SB4 = 1, SB5 = 1 ? No Yes SB5 = 0 ? No Command Sequence Error COMMENTS Standby Check SB3 1 = Detect VPP low (see Note B) Standby Check SB4 and SB5 1 = Block-erase error Standby Check SB5 1 = Block-erase error (see Note C) VPP Range Error Yes COMMAND Block-Erase Failed Yes Block-Erase Passed NOTES: A. Full status-register check can be done after each block or after a sequence of blocks. B. SB3 must be cleared before attempting additional program / erase operations. C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked. Figure 5. Automated Block-Erase Flow Chart 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 BUS OPERATION Start Write Issue Erase-Suspend Command Read Status-Register Bits No SB7 = 1 ? COMMAND Erasesuspend Status-register data. Toggle G or E to update status register. Standby Check SB7 1 = Ready Standby Check SB6 1 = Suspended Read memory Read Write Erase Completed Yes Data = FFh Read data from block other than that being erased. No SB6 = 1 ? Data = B0h Read Write Yes COMMENTS Eraseresume Data = D0h Issue Memory-Read Command No Finished Reading ? Yes Issue Erase-Resume Command Erase Continued See Note A NOTE A: See block-erase flow chart for complete erasure procedure. Figure 6. Erase-Suspend / Erase-Resume Flow Chart POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 common electrical parameter absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V Supply voltage range, VPP (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V RP, A9 (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V Output voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V Operating free-air temperature range, TA , during read/erase/program: L suffix . . . . . . . . . . . . . . 0°C to 70°C E suffix . . . . . . . . . . . . – 40°C to 85°C Q suffix . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 4. All voltage values are with respect to VSS. 5. The voltage on any input or output can undershoot to – 2 V for periods less than 20 ns. See Figure 8. 6. The voltage on any input or output can overshoot to 7 V for periods less than 20 ns. See Figure 9. IOL VZ CL (see Note A) Output Under Test VIH VOH VOL VIL VOLTAGE WAVEFORMS IOH NOTES: A. CL includes probes and fixture capacitance B. AC test conditions are driven at VIH and VIL. Timing measurements are made at VOH and VOL levels on both inputs and outputs. See Table 9 for values based on VCC operating range. C. Each device should have a 0.1-µF ceramic capacitor connected to VCC and VSS as closely as possible to the device pins. Figure 7. Load Circuit and Voltage Waveforms 20 ns 20 ns +0.8 V –0.6 V –2.0 V 20 ns Figure 8. Maximum Negative Overshoot Waveform 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 common electrical parameter (continued) 20 ns 7V VCC + 0.5 V 2.0 V 20 ns 20 ns Figure 9. Maximum Positive Overshoot Waveform Table 9. AC Test Conditions VCCRANGE IOL (mA) IOH (mA) VZ† (V) VOL (V) VOH (V) VIL (V) VIH (V) CL (pF) tf (ns) tr (ns) 5 V ± 10% 2.1 – 0.4 1.8 0.8 2.0 0.45 2.4 100 < 10 < 10 3.3 V ± 0.3 V 0.5 – 0.5 1.5 1.5 1.5 0.0 3.0 50 < 10 < 10 2.7 to 3.6 V 0.1 – 0.1 1.35 1.35 1.35 0.0 2.7 50 < 10 < 10 † VZ is the value to which an output at high impedance will float. VZ is calculated by the following equation: VZ = VOH – IOH (VOH – VOL)/ (IOH – IOL). capacitance over recommended ranges of supply voltage and operating free-air temperature PARAMETER Ci Input capacitance Co Output capacitance TEST CONDITIONS POST OFFICE BOX 1443 MIN MAX UNIT f = 1 MHz, VI = 0V 8 pF VO = 0 V, f = 1 MHz 12 pF • HOUSTON, TEXAS 77251–1443 21 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 TMS28F002ASy and TMS28F200ASy The TMS28F002ASy and the TMS28F200ASy configurations have the auto-select feature that allows alternative read and program / erase voltages. Memory reads can be performed using VCC = 3.3 V for optimum power consumption or at VCC = 5 V, for device performance. Erasing or programming the device can be accomplished with 5-V VPP, which eliminates having to use a 12-V source and / or in-system voltage converters. Alternatively, 12-V VPP operation exists for systems that already have a 12-V power supply, which provides faster programming and erasing times. These configurations are offered in two different temperature ranges: 0°C to 70°C and – 40°C to 85°C. recommended operating conditions for TMS28F002ASy and TMS28F200ASy VCC Supply voltage 3.3-V VCC range During write/read/erase/erase suspend During read only ( VPPL ) VPP VIH Supply voltage High-level g dc input voltage During write/erase/erase suspend VIL Low-level dc input voltage 3 3.3 3.6 5 5.5 VPPL 5-V VPP range 0 4.5 5 5.5 12-V VPP range 11.4 12 12.6 CMOS TTL 5 V VCC range 5-V CMOS VLKO VHH VCC lock-out voltage from write/erase (see Note 7) RP unlock voltage VPPLK VPP lock-out voltage from write/erase TA free air temperature during read/erase/program Operating free-air V VCC + 0.3 VCC + 0.2 VCC – 0.2 – 0.5 TTL V VCC + 0.5 VCC + 0.2 VCC – 0.2 2 CMOS UNIT 6.5 2 TTL 3 3 V VCC range 3.3-V MAX 4.5 CMOS 5 V VCC range 5-V NOM 5-V VCC range TTL 3 3 V VCC range 3.3-V MIN 0.8 VSS – 0.2 – 0.3 VSS + 0.2 0.8 VSS – 0.2 2 VSS + 0.2 11.4 V V V 13 V 0 12 1.5 V L suffix 0 70 °C E suffix – 40 85 °C NOTE 7: Minimum value at TA = 25°C. word/byte typical write and block-erase performance for TMS28F002ASy and TMS28F200ASy (see Notes 8 and 9) 5-V VPP RANGE PARAMETER 3.3-V VCC RANGE MIN TYP 12-V VPP RANGE 5-V VCC RANGE MAX MIN TYP 3.3-V VCC RANGE MAX MIN TYP 5-V VCC RANGE MAX MIN TYP MAX Main block erase time 2.4 1.9 1.3 1.1 14 Main block byte-program time 1.7 1.4 1.6 1.2 4.2 1.1 0.9 0.8 0.6 2.1 0.84 0.8 0.44 0.34 7 Main block word-program time Parameter/ boot-block erase time NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions 9. Excludes system-level overhead (all times in seconds) 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage and operating free-air temperature using test conditions given in Table 9 (unless otherwise noted) PARAMETER VOH High level dc output voltage High-level VOL VID Low-level dc output voltage TEST CONDITIONS TTL CMOS VCC = VCC MIN, IOH = – 2.5 mA VCC = VCC MIN, IOH = – 100 µA Input current (leakage), except for A9 when A9 = VID (see Note 10) VCC = VCC MAX, VI = 0 V to VCC MAX, RP = VHH IID IRP A9 selection code current IO IPPS VPP standby current (standby) IPPL VPP supply y current ((reset / deep power-down mode) RP = VSS ± 0.2 0 2 V, V VPP ≤ VCC IPP1 VPP supply current (active read) VPP ≥ VCC IPP3 UNIT V VCC – 0.4 VCC = VCC MIN, IOL = 5.8 mA During read algorithm-selection mode IPP2 MAX 2.4 A9 selection code voltage II MIN 0.45 V 12.6 V ±1 µA A9 = VID 500 µA RP boot-block unlock current RP = VHH 500 µA Output current (leakage) VCC = VCC MAX, VO = 0 V to VCC MAX 3.3-V VCC range VPP ≤ VCC 5-V VCC range ±10 µA 3.3-V VCC range 5 5-V VCC range 5 y current ((active byte-write) y ) VPP supply (see Notes 11 and 12) ( VPP supplyy current (active word-write)) (see Notes 11 and 12) Programming in progress Programming in progress 11.4 15 10 3.3-V VCC range 200 5-V VCC range 200 5-V VPP range, 3.3-V VCC range 30 5-V VPP range, 5-V VCC range 25 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 20 5-V VPP range, 3.3-V VCC range 30 5-V VPP range, 5-V VCC range 25 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 20 µA µA µA mA mA NOTES: 10. DQ15/A–1 is tested for output leakage only. 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) (continued) PARAMETER IPP4 IPP5 ICCS ICCL TEST CONDITIONS y current ((block-erase)) VPP supply (see Notes 11 and 12) Block erase in progress Block-erase ( ) VPP supplyy current (erase-suspend) (see Notes 11 and 12) 30 5-V VPP range, 5-V VCC range 20 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 15 5-V VPP range, 3.3-V VCC range 200 5-V VPP range, 5-V VCC range 200 12-V VPP range, 3.3-V VCC range 200 12-V VPP range, 5-V VCC range 200 1.5 mA 2 mA mA µA 3.3-V VCC range CMOS input level CMOS-input VCC = VCC MAX,, E = RP = VCC 0.2 3.3-V VCC range 110 µA 5-V VCC range 130 µA VCC supply y current (standby) VCC supply y current ((reset / deep power-down mode) y current VCC supply (active read) ( y ) VCC supplyy current (active byte-write) (see Notes 11 and 12) " RP = VSS ± 0.2 02V 5-V VCC range 0°C to 70°C 8 – 40°C to 85°C 8 E = VSS, G = VIH, IOUT = 0 mA, f = 5 MHz, 3.3-V VCC range 30 E = VSS, G = VIH, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 65 E = VSS, G = VCC, IOUT = 0 mA, f = 5 MHz, 3.3-V VCC range 30 E = VSS, G = VCC, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 60 VCC = VCC MAX, Programming in progress NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 24 UNIT VCC = VCC MAX,, E = RP = VIH CMOS input level CMOS-input ICC2 MAX TTL input level TTL-input TTL input level TTL-input ICC1 Block erase suspended Block-erase MIN 5-V VPP range, 3.3-V VCC range POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 µA mA mA 5-V VPP range, 3.3-V VCC range 30 5-V VPP range, 5-V VCC range 50 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 45 mA TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) (continued) PARAMETER ICC3 ICC4 ICC5 TEST CONDITIONS ( VCC supplyy current (active word-write)) (see Notes 11 and 12) ( ) VCC supplyy current (block-erase) (see Notes 11 and 12) VCC = VCC MAX,, Programming in progress VCC = VCC MAX,, Block-erase in progress VCC supplyy current (erase-suspend) ( ) (see Notes 11 and 12) VCC = VCC MAX,, E = VIH, Block-erase suspended MIN MAX 5-V VPP range, 3.3-V VCC range 30 5-V VPP range, 5-V VCC range 50 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 45 5-V VPP range, 3.3-V VCC range 30 5-V VPP range, 5-V VCC range 35 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 30 3.3-V VCC range 5-V VCC range UNIT mA mA 8 10 mA NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN 3.3-V VCC RANGE MAX MIN MAX ’28F002ASy 80 ’28F200ASy 80 5-V VCC RANGE MIN 3.3-V VCC RANGE MAX MIN MAX UNIT 5-V VCC RANGE MIN MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) tPL5V tPL3V ta(DV) Access time from address valid to data valid for VCC = 5 V ± 10% tAVQV 110 60 130 70 150 80 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% tPHQV 800 450 800 450 800 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH 0 0 2 th(RP3) Hold time, VCC at 3 V (MIN) to RP high t3VPH 2 NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. 0 0 0 0 ns 2 2 2 2 2 µs 2 2 2 2 2 µs Template Release Date: 7–11–94 PARAMETER ’28F002ASy 70 ’28F200ASy 70 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES ’28F002ASy 60 ’28F200ASy 60 SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 26 power-up and reset switching characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7) switching characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7) read operations ’28F002ASy 60 ’28F200ASy 60 PARAMETER ALT ALT. SYMBOL 3.3-V VCC RANGE MIN ta(A) Access time from A0 – A16 (see Note 15) ’28F002ASy 70 ’28F200ASy 70 5-V VCC RANGE MAX MIN 3.3-V VCC RANGE MAX MIN ’28F002ASy 80 ’28F200ASy 80 5-V VCC RANGE MAX MIN 3.3-V VCC RANGE MAX MIN UNIT 5-V VCC RANGE MAX MIN MAX 110 60 130 70 150 80 ns 110 60 130 70 150 80 ns 65 35 80 40 90 40 ns 110 60 130 70 150 80 ns Access time from E tc(R) Cycle time, read tELQV tGLQV tAVAV td(E) Delay time, E low to low-impedance output tELQX 0 0 0 0 0 0 ns td(G) Delay time, G low to low-impedance output tGLQX 0 0 0 0 0 0 ns tdis(E) Disable time, E to high-impedance output tEHQZ 55 25 70 30 80 30 ns tdis(G) Disable time, G to high-impedance output tGHQZ 45 25 55 30 60 30 ns th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 5 5 5 ns td(RP) Delay time, RP high to output tPHQV 800 450 800 450 800 450 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in high-impedance state tFLQZ 45 25 55 30 60 30 ns tFHQV 110 60 130 70 150 80 ns Access time from G ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide 0 0 0 0 0 0 ns 27 SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 ta(E) ta(G) TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tAVQV ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tc( W ) Cycle time, write tc( W )OP Cycle time, duration of programming operation tc( W )ERB 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002ASy80 ’28F200ASy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 110 60 130 70 150 80 ns tWHQV1 6 6 6 6 6 6 µs Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th(E) Hold time, DQ valid tPHBR tWHAX 200 100 200 100 200 100 ns 0 0 0 0 0 0 ns 0 0 0 0 0 0 ns Hold time, E tWHDX tWHEH 0 0 0 0 0 0 ns th( VPP) Hold time, VPP from valid status register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status register bit tQVPH 0 0 0 0 0 0 ns th(WP) Hold time, WP from valid status register bit tWHPL 0 0 0 0 0 0 ns tsu(WP) Setup time, WP before write operation tELPH 90 50 105 50 120 50 ns tAVWH tDVWH 90 50 105 50 120 50 ns 90 50 105 50 120 50 ns tsu(A) tsu(D) Hold time, A0 – A16 (see Note 15) tAVAV MAX ’28F002ASy70 ’28F200ASy70 Setup time, A0 – A16 (see Note 15) Setup time, DQ NOTE 15: A–1 – A16 for byte-wide Template Release Date: 7–11–94 ’28F002ASy 60 ’28F200ASy 60 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES write/erase operations — W-controlled writes SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 28 timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and extended temperature ranges) timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and extended temperature ranges) (continued) write/erase operations — W-controlled writes (continued) ’28F002ASy 60 ’28F200ASy 60 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tsu(E) Setup time, E before write operation tsu(RP) Setup time, RP at VHH to W going high tELWL MAX ’28F002ASy70 ’28F200ASy70 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002ASy80 ’28F200ASy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX 0 0 0 0 0 0 ns tPHHWH 200 100 200 100 200 100 ns 200 100 200 100 200 100 ns Setup time, VPP to W going high Pulse duration, W low tVPWH tWLWH 90 50 105 50 120 50 ns tw( WH) Pulse duration, W high tWHWL 20 10 25 20 30 30 ns trec(RPHW) Recovery time, RP high to W going low tPHWL 800 450 800 450 800 450 ns NOTE 15: A–1 – A16 for byte-wide SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 29 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tsu( VPP)1 tw( W ) ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tc( E ) Cycle time, write tc(E)OP Cycle time, duration of programming operation tc(E)ERB 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002ASy80 ’28F200ASy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 110 60 130 70 150 80 ns tEHQV1 6 6 6 6 6 6 µs Cycle time, erase operation (boot block) tEHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERP Cycle time, erase operation (parameter block) tEHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERM Cycle time, erase operation (main block) tEHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th( W ) Hold time, DQ valid Hold time, A0 – A16 (see Note 15) tAVAV MAX ’28F002ASy70 ’28F200ASy70 tPHBR tEHAX 200 100 200 100 200 100 ns 0 0 0 0 0 0 ns 0 0 0 0 0 0 ns Hold time, W tEHDX tEHWH 0 0 0 0 0 0 ns th (VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 0 0 0 ns th(WP) Hold time, WP from valid status register bit tWHPL 0 0 0 0 0 0 ns tsu(WP) Setup time, WP before write operation tELPH 90 50 105 50 120 50 ns tAVEH tDVEH tWLEL 90 50 105 50 120 50 ns 90 50 105 50 120 50 ns 0 0 0 0 0 0 ns tPHHEH 200 100 200 100 200 100 ns tVPEH tELEH 200 100 200 100 200 100 ns 90 50 105 50 120 50 ns tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu( W ) Setup time, W before write operation tsu(RP) Setup time, RP at VHH to E going high tsu( VPP)2 tw(E) Setup time, DQ Setup time, VPP to E going high Pulse duration, E low NOTE 15: A–1 – A16 for byte-wide Template Release Date: 7–11–94 ’28F002ASy 60 ’28F200ASy 60 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES write/erase operations — E-controlled writes SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 30 timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and extended temperature ranges) timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and extended temperature ranges) (continued) write/erase operations — E-controlled writes (continued) ’28F002ASy 60 ’28F200ASy 60 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN MAX ’28F002ASy70 ’28F200ASy70 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002ASy80 ’28F200ASy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX tw( EH) Pulse duration, E high tEHEL 20 10 25 20 30 30 ns trec(RPHE) Recovery time, RP high to E going low tPHEL 800 450 800 450 800 450 ns NOTE 15: A–1 – A16 for byte-wide SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 31 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 TMS28F002AEy and TMS28F200AEy The TMS28F002AEy and the TMS28F200AEy configurations offer the auto-select feature of the TMS28F200ASy with an extended VCC to a low 2.7-V to 3.6-V range (3-V nominal). Memory reads can be performed using a VCC = 3 V, allowing for more efficient power consumption than the AS device. recommended operating conditions for TMS28F002AEy and TMS28F200AEy VCC Supply voltage During write/read/erase/erase-suspend write/read/erase/erase suspend During read only ( VPPL ) VPP VIH Supply voltage High-level g dc input voltage write/erase/erase suspend During write/erase/erase-suspend Low-level dc input voltage NOM MAX 3-V VCC range 2.7 3 3.6 5-V VCC range 4.5 5 5.5 VPPL 5-V VPP range 0 4.5 5 5.5 12-V VPP range 11.4 12 12.6 TTL 3 V VCC range 3-V CMOS CMOS TTL 5 V VCC range 5-V CMOS VLKO VHH VCC lock-out voltage from write/erase (see Note 7) RP unlock voltage VPPLK VPP lock-out voltage from write/erase TA free air temperature during read/erase/program Operating free-air V VCC + 0.3 VCC + 0.2 VCC – 0.2 – 0.5 TTL 3 V VCC range 3-V V VCC + 0.5 VCC + 0.2 VCC – 0.2 2 TTL UNIT 6.5 2 CMOS 5 V VCC range 5-V VIL MIN 0.8 VSS – 0.2 – 0.3 VSS + 0.2 0.8 VSS – 0.2 2 VSS + 0.2 11.4 V V V 13 V 0 12 1.5 V L suffix 0 70 °C E suffix – 40 85 °C NOTE 7: Minimum value at TA = 25°C. word/byte typical write and block-erase performance for TMS28F002AEy and TMS28F200AEy (see Notes 8 and 9) 5-V VPP RANGE 3-V VCC RANGE PARAMETER MIN 5-V VCC RANGE MAX MIN TYP 3-V VCC RANGE MAX TYP MAX 2.4 1.9 1.3 1.1 14 Main block byte-program time 1.7 1.4 1.6 1.2 4.2 Main block word-program time 1.1 0.9 0.8 0.6 2.1 0.84 0.8 0.44 0.34 7 NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions. 9. Excludes system-level overhead (all times in seconds) 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MIN TYP 5-V VCC RANGE Main block erase time Parameter/ boot block-erase time TYP 12-V VPP RANGE MAX MIN TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) PARAMETER VOH High level dc output voltage High-level VOL VID Low-level dc output voltage TEST CONDITIONS TTL CMOS VCC = VCC MIN, IOH = – 2.5 mA VCC = VCC MIN, IOH = – 100 µA MAX 2.4 11.4 UNIT V VCC – 0.4 VCC = VCC MIN, IOL = 5.8 mA During read algorithm-selection mode A9 selection code voltage MIN 0.45 V 12.6 V ±1 µA Input current (leakage), except for A9 when A9 = VID (see Note 10) VCC = VCC MAX,VI = 0 V to VCC MAX, RP = VHH IID IRP A9 selection code current A9 = VID 500 µA RP boot-block unlock current RP = VHH 500 µA IO Output current (leakage) ±10 µA IPPS VPP standby current (standby) VCC = VCC MAX,VO = 0 V to VCC MAX 3-V VCC range VPP ≤ VCC 5-V VCC range IPPL VPP supply y current ((reset / deep power-down mode) RP = VSS ± 0.2 0 2 V, V VPP ≤ VCC 3-V VCC range 5 5-V VCC range 5 IPP1 VPP supply current (active read) VPP ≥ VCC 3-V VCC range 200 5-V VCC range 200 5-V VPP range, 3-V VCC range 30 5-V VPP range, 5-V VCC range 25 12-V VPP range, 3-V VCC range 25 12-V VPP range, 5-V VCC range 20 5-V VPP range, 3-V VCC range 30 5-V VPP range, 5-V VCC range 25 II IPP2 IPP3 y current ((active byte-write) y ) VPP supply (see Notes 11 and 12) ( VPP supplyy current (active word-write)) (see Notes 11 and 12) Programming in progress Programming in progress 12-V VPP range, 3-V VCC range 12-V VPP range, 5-V VCC range 15 10 µA µA µA mA mA 25 20 NOTES: 10. DQ15/A–1 is tested for output leakage only. 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) (continued) PARAMETER IPP4 IPP5 TEST CONDITIONS y current ((block-erase)) VPP supply (see Notes 11 and 12) Block erase in progress Block-erase ( ) VPP supplyy current (erase-suspend) (see Notes 11 and 12) Block erase suspended Block-erase TTL input level TTL-input ICCS VCC supply y current (standby) CMOS input level CMOS-input ICCL VCC supply y current ((reset / deep power-down mode) TTL input level TTL-input ICC1 y current VCC supply (active read) CMOS input level CMOS-input ICC2 ( y ) VCC supplyy current (active byte-write) (see Notes 11 and 12) VCC = VCCMAX,, E = RP = VIH RP = VSS ± 0.2 02V MAX 5-V VPP range, 5-V VCC range 20 12-V VPP range, 3-V VCC range 25 12-V VPP range, 5-V VCC range 15 5-V VPP range, 3-V VCC range 200 5-V VPP range, 5-V VCC range 200 12-V VPP range, 3-V VCC range 200 12-V VPP range, 5-V VCC range 200 3-V VCC range 1.5 mA 5-V VCC range 2 mA 3-V VCC range 110 µA 5-V VCC range 130 µA mA µA 0°C to 70°C 8 – 40°C to 85°C 8 30 E = VIL, G = VIH, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 65 E = VSS, G = VCC, IOUT = 0 mA, f = 5 MHz, 3-V VCC range 30 E = VSS, G = VCC, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 60 VCC = VCCMAX, Programming in progress POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT 30 E = VIL, G = VIH, IOUT = 0 mA, f = 5 MHz, 3-V VCC range NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 34 MIN 5-V VPP range, 3-V VCC range µA mA mA 5-V VPP range, 3-V VCC range 30 5-V VPP range, 5-V VCC range 50 12-V VPP range, 3-V VCC range 12-V VPP range, 5-V VCC range mA 25 45 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) (continued) PARAMETER ICC3 ICC4 ICC5 TEST CONDITIONS ( VCC supplyy current (active word-write)) (see Notes 11 and 12) ( ) VCC supplyy current (block-erase) (see Notes 11 and 12) VCC = VCC MAX,, Programming in progress VCC = VCC MAX,, Block-erase in progress VCC supplyy current (erase-suspend) ( ) (see Notes 11 and 12) VCC = VCC MAX,, E = VIH, Block-erase suspended MIN MAX 5-V VPP range, 3-V VCC range 30 5-V VPP range, 5-V VCC range 50 12-V VPP range, 3-V VCC range 25 12-V VPP range, 5-V VCC range 45 5-V VPP range, 3-V VCC range 30 5-V VPP range, 5-V VCC range 35 12-V VPP range, 3-V VCC range 25 12-V VPP range, 5-V VCC range 30 UNIT mA mA 3-V VCC range 8 5-V VCC range 10 mA NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 ALT ALT. SYMBOL 3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN 3-V VCC RANGE MAX MIN MAX ’28F002AEy 80 ’28F200AEy 80 5-V VCC RANGE MIN 3-V VCC RANGE MAX MIN MAX UNIT 5-V VCC RANGE MIN MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) tPL5V tPL3V ta(DV) Access time from address valid to data valid for VCC = 5 V ± 10% (see Note 14) tAVQV 110 60 130 70 150 80 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% (see Note 14) tPHQV 800 450 800 450 800 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH 0 0 2 th(RP3) Hold time, VCC at 3 V (MIN) to RP high t3VPH 2 NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. 0 0 0 0 ns 2 2 2 2 2 µs 2 2 2 2 2 µs Template Release Date: 7–11–94 PARAMETER ’28F002AEy 70 ’28F200AEy 70 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES ’28F002AEy 60 ’28F200AEy 60 SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 36 power-up and reset switching characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7) switching characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7) read operations ’28F002AEy 60 ’28F200AEy 60 PARAMETER ALT ALT. SYMBOL 3.3-V VCC RANGE MIN ta(A) Access time from A0 – A16 (see Note 15) ’28F002AEy 70 ’28F200AEy 70 5-V VCC RANGE MAX MIN 3.3-V VCC RANGE MAX MIN ’28F002AEy 80 ’28F200AEy 80 5-V VCC RANGE MAX MIN 3.3-V VCC RANGE MAX MIN UNIT 5-V VCC RANGE MAX MIN MAX 110 60 130 70 150 80 ns 110 60 130 70 150 80 ns 65 35 80 40 90 40 ns 110 60 130 70 150 80 ns Access time from E tc(R) Cycle time, read tELQV tGLQV tAVAV td(E) Delay time, E low to low-impedance output tELQX 0 0 0 0 0 0 ns td(G) Delay time, G low to low-impedance output tGLQX 0 0 0 0 0 0 ns tdis(E) Disable time, E to high-impedance output tEHQZ 55 25 70 30 80 30 ns tdis(G) Disable time, G to high-impedance output tGHQZ 45 25 55 30 60 30 ns th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 5 5 5 ns td(RP) Output delay time from RP high tPHQV 800 450 800 450 800 450 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in high-impedance state tFLQZ 45 25 55 30 60 30 ns tFHQV 110 60 130 70 150 80 ns Access time from G ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide 0 0 0 0 0 0 ns 37 SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 ta(E) ta(G) TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tAVQV ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tc( W ) Cycle time, write tc( W )OP Cycle time, duration of programming operation tc( W )ERB 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AEy80 ’28F200AEy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 110 60 130 70 150 80 ns tWHQV1 6 6 6 6 6 6 µs Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th(E) Hold time, DQ valid tPHBR tWHAX 200 100 200 100 200 100 ns 0 0 0 0 0 0 ns 0 0 0 0 0 0 ns Hold time, E tWHDX tWHEH 0 0 0 0 0 0 ns th( VPP) Hold time, VPP from valid status register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status register bit tQVPH 0 0 0 0 0 0 ns th(WP) Hold time, WP from valid status register bit tWHPL 0 0 0 0 0 0 ns tsu(WP) Setup time, WP before write operation tELPH 90 50 105 50 120 50 ns tAVWH tDVWH 90 50 105 50 120 50 ns 90 50 105 50 120 50 ns tsu(A) tsu(D) Hold time, A0 – A16 (see Note 15) tAVAV MAX ’28F002AEy70 ’28F200AEy70 Setup time, A0 – A16 (see Note 15) Setup time, DQ NOTE 15: A–1 – A16 for byte-wide Template Release Date: 7–11–94 ’28F002AEy 60 ’28F200AEy 60 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES write/erase operations — W-controlled writes SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 38 timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) (continued) write/erase operations — W-controlled writes (continued) ’28F002AEy 60 ’28F200AEy 60 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tsu(E) Setup time, E before write operation tsu(RP) Setup time, RP at VHH to W going high tELWL MAX ’28F002AEy70 ’28F200AEy70 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AEy80 ’28F200AEy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX 0 0 0 0 0 0 ns tPHHWH 200 100 200 100 200 100 ns 200 100 200 100 200 100 ns Setup time, VPP to W going high Pulse duration, W low tVPWH tWLWH 90 50 105 50 120 50 ns tw( WH) Pulse duration, W high tWHWL 20 10 25 20 30 30 ns trec(RPHW) Recovery time, RP high to W going low tPHWL 800 450 800 450 800 450 ns NOTE 15: A–1 – A16 for byte-wide SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 39 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tsu( VPP)1 tw( W ) ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tc( E ) Cycle time, write tc(E)OP Cycle time, duration of programming operation tc(E)ERB 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AEy80 ’28F200AEy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 110 60 130 70 150 80 ns tEHQV1 6 6 6 6 6 6 µs Cycle time, erase operation (boot block) tEHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERP Cycle time, erase operation (parameter block) tEHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERM Cycle time, erase operation (main block) tEHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th( W ) Hold time, DQ valid Hold time, A0 – A16 (see Note 15) tAVAV MAX ’28F002AEy70 ’28F200AEy70 tPHBR tEHAX 200 100 200 100 200 100 ns 0 0 0 0 0 0 ns 0 0 0 0 0 0 ns Hold time, W tEHDX tEHWH 0 0 0 0 0 0 ns th (VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 0 0 0 ns th(WP) Hold time, WP from valid status register bit tWHPL 0 0 0 0 0 0 ns tsu(WP) Setup time, WP before write operation tELPH 90 50 105 50 120 50 ns tAVEH tDVEH tWLEL 90 50 105 50 120 50 ns 90 50 105 50 120 50 ns 0 0 0 0 0 0 ns tPHHEH 200 100 200 100 200 100 ns tVPEH tELEH 200 100 200 100 200 100 ns 90 50 105 50 120 50 ns tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu( W ) Setup time, W before write operation tsu(RP) Setup time, RP at VHH to E going high tsu( VPP)2 tw(E) Setup time, DQ Setup time, VPP to E going high Pulse duration, E low NOTE 15: A–1 – A16 for byte-wide Template Release Date: 7–11–94 ’28F002AEy 60 ’28F200AEy 60 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES write/erase operations — E-controlled writes SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 40 timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) (continued) timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) (continued) write/erase operations — E-controlled writes (continued) ’28F002AEy 60 ’28F200AEy 60 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN MAX ’28F002AEy70 ’28F200AEy70 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AEy80 ’28F200AEy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX tw( EH) Pulse duration, E high tEHEL 20 10 25 20 30 30 ns trec(RPHE) Recovery time, RP high to E going low tPHEL 800 450 800 450 800 450 ns NOTE 15: A–1 – A16 for byte-wide SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 41 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 TMS28F002AMy and TMS28F200AMy The TMS28F002AMy and TMS28F200AMy configurations offer a 3-V or 5-V memory read with a 12-V program and erase. These configurations are intended for low 3.3-V reads and the fast programming offered with the 12-V VPP and 5-V VCC. The configurations are offered in two different temperature ranges: 0°C to 70°C and – 40°C to 85°C. recommended operating conditions for TMS28F002AMy and TMS28F200AMy VCC Supply voltage VPP Supply voltage VIH High-level g dc input voltage During write/read/erase/erase-suspend write/read/erase/erase suspend During read only ( VPPL ) Low-level dc input voltage During write/erase/erase-suspend TTL 3 3 V VCC range 3.3-V CMOS TTL CMOS TTL 3 3 V VCC range 3.3-V CMOS TTL 5 V VCC range 5-V VLKO VHH VCC lock-out voltage from write/erase RP unlock voltage VPPLK VPP lock-out voltage from write/erase TA 5-V VCC range VPPL 12-V VPP range 5 V VCC range 5-V VIL 3.3-V VCC range CMOS MIN NOM MAX 3 3.3 3.6 4.5 5 5.5 0 V 6.5 11.4 12 2 V 12.6 VCC + 0.5 VCC + 0.2 VCC – 0.2 2 VCC + 0.3 VCC + 0.2 VCC – 0.2 – 0.5 V 0.8 VSS – 0.2 – 0.3 VSS + 0.2 0.8 VSS – 0.2 2 VSS + 0.2 V V 11.4 Operating free-air free air temperature during read/erase/program UNIT 12 13 V 0 1.5 V L suffix 0 70 °C E suffix – 40 85 °C NOTE 7:. Minimum value at TA = 25°C. word/byte typical write and block-erase performance for TMS28F002AMy and TMS28F200AMy (see Notes 8 and 9) 12-V VPP RANGE 3.3-V VCC RANGE PARAMETER MIN TYP 5-V VCC RANGE MAX TYP MAX Main block erase time 1.3 1.1 14 Main block byte-program time 1.6 1.2 4.2 Main block word-program time 0.8 0.6 2.1 Parameter/ boot block-erase time 0.44 0.34 7 NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions. 9. Excludes system-level overhead (all times in seconds). 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High level dc output voltage High-level VOL VID Low-level dc output voltage VCC = VCCMIN, IOH = – 2.5 mA VCC = VCCMIN, IOH = – 100 µA VCC = VCCMIN, IOL = 5.8 mA A9 selection code voltage During read algorithm-selection mode Input current (leakage), except for A9 when A9 = VID (see Note 10) VCC = VCCMAX,VI = 0 V to VCCMAX, RP = VHH IID IRP A9 selection code current IO IPPS VPP standby current (standby) IPPL VPP supply y current ((reset / deep power-down mode) RP = VSS ± 0.2 0 2 V, V VPP ≤ VCC IPP1 VPP supply current (active read) VPP ≥ VCC IPP2 VPP supply y current ((active byte-write) y ) (see Notes 11 and 12) II IPP3 TTL CMOS MIN MAX 2.4 UNIT V VCC – 0.4 0.45 V 12.6 V ±1 µA A9 = VID 500 µA RP boot-block unlock current RP = VHH 500 µA Output current (leakage) VCC = VCCMAX,VO = 0 V to VCCMAX 3.3-V VCC range VPP ≤ VCC 5-V VCC range ±10 µA 3.3-V VCC range 5 5-V VCC range 5 VPP supplyy current (active ( word-write)) (see Notes 11 and 12) Programming in progress Programming in progress 11.4 15 10 3.3-V VCC range 200 5-V VCC range 200 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 20 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 20 µA µA µA mA mA NOTES: 10. DQ15/A–1 is tested for output leakage only. 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) (continued) PARAMETER IPP4 IPP5 TEST CONDITIONS VPP supply y current ((block-erase)) (see Notes 11 and 12) Block erase in progress Block-erase VPP supplyy current (erase-suspend) ( ) (see Notes 11 and 12) Block erase suspended Block-erase TTL input level TTL-input ICCS VCC supply y current (standby) CMOS input level CMOS-input ICCL VCC supply y current ((reset / deep power-down mode) TTL input level TTL-input ICC1 VCC supply y current (active read) CMOS input level CMOS-input ICC2 ICC3 ICC4 ICC5 VCC = VCCmax,, E = RP = VIH 02V RP = VSS ± 0.2 MAX 12-V VPP range, 5-V VCC range 15 12-V VPP range, 3.3-V VCC range 200 12-V VPP range, 5-V VCC range 200 3.3-V VCC range 1.5 mA 2 mA 3.3-V VCC range 110 µA 5-V VCC range 130 µA 5-V VCC range mA µA 0°C to 70°C 8 – 40°C to 85°C 8 30 E = VIL, G = VIH, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 65 E = VSS, G = VCC, IOUT = 0 mA, f = 5 MHz, 3.3-V VCC range 30 E = VSS, G = VCC, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 60 ( y ) VCC supplyy current (active byte-write) (see Notes 11 and 12) VCC = VCCMAX,, Programming in progress ( VCC supplyy current (active word-write)) (see Notes 11 and 12) VCC = VCCMAX,, Programming in progress VCC supplyy current (block-erase) ( ) (see Notes 11 and 12) VCC = VCCMAX,, Block-erase in progress VCC supplyy current (erase-suspend) ( ) (see Notes 11 and 12) VCC = VCCMAX,E , = VIH, Block-erase suspended POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT 25 E = VIL, G = VIH, IOUT = 0 mA, f = 5 MHz, 3.3-V VCC range NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 44 MIN 12-V VPP range, 3.3-V VCC range µA mA mA 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 45 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 45 12-V VPP range, 3.3-V VCC range 25 12-V VPP range, 5-V VCC range 30 3.3-V VCC range 8 5-V VCC range mA mA mA 10 mA power-up and reset switching characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7) ’28F002AMy 60 ’28F200AMy 60 PARAMETER ALT ALT. SYMBOL 3.3-V VCC RANGE MIN MAX ’28F002AMy 70 ’28F200AMy 70 5-V VCC RANGE MIN 3.3-V VCC RANGE MAX MIN MAX ’28F002AMy 80 ’28F200AMy 80 5-V VCC RANGE MIN 3.3 V VCC RANGE MAX MIN MAX UNIT 5-V VCC RANGE MIN MAX tPL5V tPL3V ta(DV) Access time from address valid to data valid for VCC = 5 V ± 10% tAVQV 110 60 130 70 150 80 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% tPHQV 800 450 800 450 800 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH 0 0 2 th(RP3) Hold time, VCC at 3 V (MIN) to RP high t3VPH 2 NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. 0 0 0 0 ns 2 2 2 2 2 µs 2 2 2 2 2 µs SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 45 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) PARAMETER ALT ALT. SYMBOL 3.3-V VCC RANGE MIN ta(A) Access time from A0 – A16 (see Note 15) ’28F002AMy 70 ’28F200AMy 70 5-V VCC RANGE MAX MIN 3.3-V VCC RANGE MAX MIN ’28F002AMy 80 ’28F200AMy 80 5-V VCC RANGE MAX MIN 3.3-V VCC RANGE MAX MIN UNIT 5-V VCC RANGE MAX MIN MAX tAVQV 110 60 130 70 150 80 ns 110 60 130 70 150 80 ns 65 35 80 40 90 40 ns 110 60 130 70 150 80 ns POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ta(E) ta(G) Access time from E tc(R) Cycle time, read tELQV tGLQV tAVAV td(E) Delay time, E low to low-impedance output tELQX 0 0 0 0 0 0 ns td(G) Delay time, G low to low-impedance output tGLQX 0 0 0 0 0 0 ns tdis(E) Disable time, E to high-impedance output tEHQZ 55 25 70 30 80 30 ns tdis(G) Disable time, G to high-impedance output tGHQZ 45 25 55 30 60 30 ns th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 5 5 5 ns td(RP) Output delay time from RP high tPHQV 800 450 800 450 800 450 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in high-impedance state tFLQZ 45 25 55 30 60 30 ns tFHQV 110 60 130 70 150 80 ns Access time from G ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide 0 0 0 0 0 0 ns Template Release Date: 7–11–94 ’28F002AMy 60 ’28F200AMy 60 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES read operations SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 46 switching characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7) timing requirements for TMS28F002AMy and TMS28F200AMy (commercial and extended temperature ranges) write/erase operations — W-controlled writes ’28F002AMy 60 ’28F200AMy 60 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tc( W ) Cycle time, write tc( W )OP Cycle time, duration of programming operation tc( W )ERB MAX 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AMy80 ’28F200AMy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX 60 130 70 150 80 ns tWHQV1 6 6 6 6 6 6 µs Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s Delay time, boot-block relock th(D) th(E) 0 0 0 0 0 ns 0 0 0 0 0 0 ns Hold time, E tWHEH 0 0 0 0 0 0 ns th( VPP) Hold time, VPP from valid status register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status register bit tQVPH 0 0 0 0 0 0 ns 90 50 105 50 120 50 ns 90 50 105 50 120 50 ns 0 0 0 0 0 0 ns tPHHWH 200 100 200 100 200 100 ns 200 100 200 100 200 100 ns 90 50 105 50 120 50 ns 20 10 25 20 30 30 ns 800 450 800 450 800 450 ns tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) Setup time, DQ tAVWH tDVWH tsu(E) Setup time, E before write operation tELWL tsu(RP) Setup time, RP at VHH to W going high tsu( VPP)1 tw( W ) Setup time, VPP to W going high tw( WH) Pulse duration, W high tVPWH tWLWH tWHWL trec(RPHW) Recovery time, RP high to W going low tPHWL Pulse duration, W low NOTE 15: A–1 – A16 for byte-wide 200 100 200 100 200 100 ns 47 SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 0 Hold time, DQ valid tPHBR tWHAX tWHDX Hold time, A0 – A16 (see Note 15) TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 110 td(RPR) th(A) tAVAV ’28F002AMy70 ’28F200AMy70 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tc( E ) Cycle time, write tc(E)OP Cycle time, duration of programming operation tc(E)ERB MAX 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AMy80 ’28F200AMy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 110 60 130 70 150 80 ns tEHQV1 6 6 6 6 6 6 µs Cycle time, erase operation (boot block) tEHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERP Cycle time, erase operation (parameter block) tEHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERM Cycle time, erase operation (main block) tEHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th( W ) Hold time, DQ valid Hold time, A0 – A16 (see Note 15) tAVAV ’28F002AMy70 ’28F200AMy70 tPHBR tEHAX 200 100 200 100 200 100 ns 0 0 0 0 0 0 ns 0 0 0 0 0 0 ns Hold time, W tEHDX tEHWH 0 0 0 0 0 0 ns th (VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 0 0 0 ns tAVEH tDVEH tWLEL 90 50 105 50 120 50 ns 90 50 105 50 120 50 ns 0 0 0 0 0 0 ns tPHHEH 200 100 200 100 200 100 ns tVPEH 200 100 200 100 200 100 ns tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu( W ) Setup time, W before write operation tsu(RP) Setup time, RP at VHH to E going high Setup time, DQ tsu( VPP)2 Setup time, VPP to E going high NOTE 15: A–1 – A16 for byte-wide Template Release Date: 7–11–94 ’28F002AMy 60 ’28F200AMy 60 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES write/erase operations — E-controlled writes SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 48 timing requirements for TMS28F002AMy and TMS28F200AMy (commercial and extended temperature ranges) timing requirements for TMS28F002AMy and TMS28F200AMy (commercial and extended temperature ranges) (continued) write/erase operations — E-controlled writes ’28F002AMy 60 ’28F200AMy 60 ALT ALT. SYMBOL 3.3-V VCC RANGE MIN tw(E) tw( EH) trec(RPHE) Pulse duration, E low MAX ’28F002AMy70 ’28F200AMy70 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX ’28F002AMy80 ’28F200AMy80 5-V VCC RANGE MIN MAX 3.3-V VCC RANGE MIN MAX 5-V VCC RANGE MIN UNIT MAX 90 50 105 50 120 50 ns Pulse duration, E high tELEH tEHEL 20 10 25 20 30 30 ns Recovery time, RP high to E going low tPHEL 800 450 800 450 800 450 ns NOTE 15: A–1 – A16 for byte-wide SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 49 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 TMS28F002AFy and TMS28F200AFy The TMS28F002AFy and TMS28F200AFy configurations offer a 5-V memory read with a 5-V or 12-V program and erase. These configurations are intended for systems using a single 5-V power supply. The configurations are offered in all three temperature ranges: 0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C. recommended operating conditions for TMS28F002AFy and TMS28F200AFy VCC VPP Supply voltage Supply voltage MIN NOM MAX 5 5.5 During write/read/erase/erase-suspend 5-V VCC range 4.5 During read only ( VPPL ) VPPL 5-V VPP range 0 4.5 5 12-V VPP range 11.4 12 During write/erase/erase-suspend write/erase/erase suspend TTL VIH High level dc input voltage High-level VIL Low level dc input voltage Low-level VLKO VHH VCC lock-out voltage from write/erase (See Note 7) RP unlock voltage VPPLK VPP lock-out voltage from write/erase TA Operating free-air temperature during read/erase/program TTL V 12.6 0.8 VSS – 0.2 2 11.4 5.5 VCC + 0.3 VCC + 0.2 VCC – 0.2 – 0.3 CMOS V 6.5 2 CMOS UNIT VSS + 0.2 V V V 12 13 V 0 1.5 V L suffix 0 70 E suffix – 40 85 Q suffix – 40 125 °C NOTE 7: Minimum value at TA = 25°C. word/byte typical write and block-erase performance for TMS28F002AFy and TMS28F200AFy (see Notes 8 and 9) 5-V VPP AND 5-V VCC RANGES MIN TYP MAX PARAMETER 12-V VPP AND 5-V VCC RANGES TYP MAX Main block erase time 1.9 1.1 14 Main block byte-program time 1.4 1.2 4.2 Main block word-program time 0.9 0.6 2.1 Parameter/ boot-block erase time 0.8 0.34 7 NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions. 9. Excludes system-level overhead (all times in seconds) 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MIN TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) PARAMETER VOH VOL VID High-level g dc output voltage TTL TEST CONDITIONS MIN IOH = – 2.5 mA IOH = – 100 µA 2.4 VCC = VCCMIN, VCC = VCCMIN, CMOS Low-level dc output voltage Input current (leakage), except for A9 when A9 = VID (see Note 10) VCC = VCCMAX, IID IRP A9 selection code current A9 = VID RP boot-block unlock current RP = VHH IO IPPS Output current (leakage) VCC = VCCMAX, VPP ≤ VCC II IPPL VPP standby current (standby) VPP supply current (reset / deep power-down mode) IPP1 VPP supply current (active read) IPP2 IPP3 IPP4 IPP5 ICCS VPP supply y current ((active byte-write) y ) (see Notes 11 and 12) y current ((active word-write)) VPP supply (see Notes 11 and 12) y current ((block-erase)) VPP supply (see Notes 11 and 12) VO = 0 V to VCCMAX 5-V VCC range ICC1 l currentt (reset ( t / deep d VCC supply ower-down mode) power-down VCC supply y current (active read) V ±1 µA 500 µA 500 µA ±10 µA 10 µA 5 µA VPP ≥ VCC 5-V VCC range 200 µA 5-V VPP range, 5-V VCC range 25 12-V VPP range, 5-V VCC range 20 5-V VPP range, 5-V VCC range 25 12-V VPP range, 5-V VCC range 20 5-V VPP range, 5-V VCC range 20 12-V VPP range, 5-V VCC range 15 5-V VPP range, 5-V VCC range 200 12-V VPP range, 5-V VCC range 200 Programming in progress Programming in progress Block erase suspended Block-erase VCC = VCCmax, ma E = RP = VIH RP = VSS ± 0.2 V mA mA mA µA 5-V VCC range 2 mA 5-V VCC range 130 µA 0°C to 70°C ICCL V 12.6 5-V VCC range TTL-input level CMOS-input level 0.45 RP = VSS ± 0.2 V, VPP ≤ VCC Block erase in progress Block-erase ( ) VPP supplyy current (erase-suspend) (see Notes 11 and 12) VCC supply y current (standby) VI = 0 V to VCCMAX, RP = VHH 11.4 UNIT V VCC – 0.4 VCC = VCCMIN, IOL = 5.8 mA During read algorithm-selection mode A9 selection code voltage MAX 8 – 40°C to 85°C 8 – 40°C to 125°C 30 µA TTL-input level E = VIL, G = VIH, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 65 mA CMOS-input level E = VCC, G = VCC, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 60 mA NOTES: 10. DQ15/A–1 is tested for output leakage only. 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless otherwise noted) (continued) PARAMETER ICC2 ICC3 ICC4 ICC5 TEST CONDITIONS VCC supplyy current (active ( byte-write) y ) (see Notes 11 and 12) VCC = VCCMAX,, Programming in progress VCC supplyy current (active ( word-write)) (see Notes 11 and 12) VCC = VCCMAX,, Programming in progress ( ) VCC supplyy current (block-erase) (see Notes 11 and 12) VCC = VCCMAX VPP = 12 V or 5 V Block-erase in progress VCC supply current (erase-suspend) (see Notes 11 and 12) VCC = VCCMAX,E = VIH, Block-erase suspended NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MIN MAX 5-V VPP range, 5-V VCC range 50 12-V VPP range, 5-V VCC range 45 5-V VPP range, 5-V VCC range 50 12-V VPP range, 5-V VCC range 45 5-V VPP range, 5-V VCC range 35 12-V VPP range, 5-V VCC range 30 5-V VCC range 10 UNIT mA mA mA mA TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 power-up and reset switching characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7) ’28F002AFy 60 ’28F200AFy 60 ’28F002AFy 70 ’28F200AFy 70 ’28F002AFy 80 ’28F200AFy 80 5 V VCC RANGE 5 V VCC RANGE 5 V VCC RANGE ALT ALT. SYMBOL PARAMETER MIN MAX MIN MAX MIN UNIT MAX tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) tPL5V tPL3V ta(DV) Access time from address valid to data valid for VCC = 5 V ± 10% tAVQV 60 70 80 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% tPHQV 450 450 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. 0 0 2 0 2 ns µs 2 power-up and reset switching characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of supply voltage (automotive temperature range) (see Notes 11, 12, 13) ALT ALT. SYMBOL PARAMETER ’28F002AFy70 ’28F200AFy70 ’28F002AFy80 ’28F200AFy80 ’28F002AFy90 ’28F200AFy90 5 V VCC RANGE 5 V VCC RANGE 5 V VCC RANGE MIN MAX MIN MAX MIN UNIT MAX tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) tPL5V tPL3V ta(DV) Access time from address valid to data valid for VCC = 5 V ± 10% tAVQV 70 80 90 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% tPHQV 450 450 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. POST OFFICE BOX 1443 0 0 2 • HOUSTON, TEXAS 77251–1443 2 0 2 ns µs 53 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 switching characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7) read operations ALT ALT. SYMBOL PARAMETER ’28F002AFy 60 ’28F200AFy 60 ’28F002AFy 70 ’28F200AFy 70 ’28F002AFy 80 ’28F200AFy 80 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN ta(A) ta(E) Access time from A0 – A16 (see Note 15) ta(G) tc(R) Access time from G td(E) td(G) Delay time, E low to low-impedance output tdis(E) tdis(G) Disable time, E to high-impedance output Access time from E Cycle time, read Delay time, G low to low-impedance output MAX MIN MAX MIN UNIT MAX tAVQV tELQV 60 70 80 ns 60 70 80 ns tGLQV tAVAV 35 40 40 ns tELQX tGLQX 60 70 80 ns 0 0 0 ns 0 0 0 ns Disable time, G to high-impedance output tEHQZ tGHQZ th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 ns td(RP) Output delay time from RP high tPHQV 450 450 450 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in the high-impedance state tFLQZ 25 30 30 ns ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide tFHQV 60 70 80 ns 54 • HOUSTON, TEXAS 77251–1443 POST OFFICE BOX 1443 25 30 30 ns 25 30 30 ns 0 0 0 ns TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 switching characteristics for TMS28F200AFy over recommended ranges of supply voltage (automotive temperature range) (see Table 9 and Figure 7) read operations ALT ALT. SYMBOL PARAMETER ’28F002AFy 70 ’28F200AFy 70 ’28F002AFy 80 ’28F200AFy 80 ’28F002AFy 90 ’28F200AFy 90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN ta(A) ta(E) Access time from A0 – A16 (see Note 15) ta(G) tc(R) Access time from G td(E) td(G) Delay time, E low to low-impedance output tdis(E) tdis(G) Disable time, E to high-impedance output Access time from E Cycle time, read Delay time, G low to low-impedance output MAX MIN MAX MIN UNIT MAX tAVQV tELQV 70 80 90 ns 70 80 90 ns tGLQV tAVAV 35 40 35 ns tELQX tGLQX 70 80 90 ns 0 0 0 ns 0 0 0 ns Disable time, G to high-impedance output tEHQZ tGHQZ th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 ns td(RP) Output delay time from RP high tPHQV 300 300 300 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in the high-impedance state tFLQZ 30 30 35 ns tFHQV 70 80 90 ns ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide POST OFFICE BOX 1443 25 30 35 ns 25 30 35 ns 0 0 • HOUSTON, TEXAS 77251–1443 0 ns 55 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F002AFy and TMS28F200AFy (commercial and extended temperature ranges) write/erase operations — W-controlled writes ALT ALT. SYMBOL ’28F002AFy 60 ’28F200AFy 60 ’28F002AFy 70 ’28F200AFy 70 ’28F002AFy80 ’28F200AFy80 5-V VCC RANGE 5–V VCC RANGE 5-V VCC RANGE MIN MAX MIN MAX MIN UNIT MAX tc( W ) Cycle time, write tAVAV 60 70 80 ns tc( W )OP Cycle time, duration of programming operation tWHQV1 6 6 6 µs tc( W )ERB Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th(E) Hold time, DQ valid tPHBR tWHAX Hold time, A0 – A16 (see Note 15) 100 100 100 ns 0 0 0 ns 0 0 0 ns Hold time, E tWHDX tWHEH 0 0 0 ns th( VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns tWHPL tELPH 0 0 0 ns 50 50 50 ns 50 50 50 ns 50 50 50 ns th(WP) tsu(WP) Hold time, WP from valid status-register bit tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu(E) tsu(RP) Setup time, E before write operation tsu( VPP)1 tw( W ) Setup time, VPP to W going high tw( WH) trec(RPHW) Pulse duration, W high Setup time, WP before write operation tAVWH tDVWH Setup time, DQ Setup time, RP at VHH to W going high Pulse duration, W low Recovery time, RP high to W going low tELWL tPHHWH tVPWH tWLWH tWHWL tPHWL 0 0 0 ns 100 100 100 ns 100 100 100 ns 50 50 50 ns 10 20 30 ns 450 450 450 ns NOTE 15: A–1 – A16 for byte-wide 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F200AFy (automotive temperature range) write/erase operations — W-controlled writes ALT ALT. SYMBOL ’28F002AFy 70 ’28F200AFy 70 ’28F002AFy 80 ’28F200AFy 80 ’28F002AFy 90 ’28F200AFy 90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN tc( W ) Cycle time, write MAX MIN MAX MIN UNIT MAX tAVAV 70 80 90 ns tc( W )OP Cycle time, duration of programming operation tWHQV1 6 6 7 µs tc( W )ERB Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.4 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.4 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 td(RPR) th(A) Delay time, boot-block relock th(D) th(E) Hold time, DQ valid th( VPP) th(RP) Hold time, A0 – A16 (see Note 15) tPHBR tWHAX 0.6 100 0.7 100 s 100 ns 0 0 0 ns 0 0 0 ns Hold time, E tWHDX tWHEH 0 0 0 ns Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns tWHPL tELPH 0 0 0 ns th(WP) tsu(WP) Hold time, WP from valid status-register bit tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu(E) tsu(RP) tsu( VPP)1 tw( W ) Setup time, VPP to W going high tw( WH) trec(RPHW) Setup time, WP before write operation 50 50 50 ns 50 50 50 ns Setup time, DQ tAVWH tDVWH 50 50 50 ns Setup time, E before write operation tELWL 0 0 0 ns tPHHWH tVPWH 100 100 100 ns 100 100 100 ns 60 60 60 ns Pulse duration, W high tWLWH tWHWL 20 30 40 ns Recovery time, RP high to W going low tPHWL 220 220 220 ns Setup time, RP at VHH to W going high Pulse duration, W low NOTE 15: A–1 – A16 for byte-wide POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F002AFy and TMS28F200AFy (commercial and extended temperature ranges) write/erase operations — E-controlled writes ALT ALT. SYMBOL ’28F002AFy 60 ’28F200AFy 60 ’28F002AFy70 ’28F200AFy70 ’28F002AFy80 ’28F200AFy80 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN tc( E ) tc(E)OP Cycle time, write tc(E)ERB tc(E)ERP Cycle time, erase operation (boot block) tc(E)ERM td(RPR) Cycle time, erase operation (main block) th(A) th(D) Hold time, A0 – A16 (see Note 15) th( W ) th (VPP) th(RP) Cycle time, duration of programming operation Cycle time, erase operation (parameter block) tAVAV tEHQV1 tEHQV2 tEHQV3 tEHQV4 Delay time, boot-block relock tPHBR tEHAX MAX MAX MIN MAX 60 70 80 ns 6 6 6 µs 0.3 0.3 0.3 s 0.3 0.3 0.3 s 0.6 0.6 0.6 s 100 100 100 ns 0 0 0 ns 0 0 0 ns Hold time, W tEHDX tEHWH 0 0 0 ns Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns tWHPL tELPH 0 0 0 ns 50 50 50 ns 50 50 50 ns 50 50 50 ns 0 0 0 ns tPHHEH tVPEH 100 100 100 ns 100 100 100 ns 50 50 50 ns 10 20 30 ns 450 450 450 ns Hold time, DQ valid th(WP) tsu(WP) Hold time, WP from valid status-register bit tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) Setup time, DQ valid tAVEH tDVEH tsu( W ) tsu(RP) Setup time, W before write operation tWLEL tsu( VPP)2 tw(E) Setup time, VPP to E going high tw( EH) trec(RPHE) Pulse duration, E high tELEH tEHEL Recovery time, RP high to E going low tPHEL Setup time, WP before write operation Setup time, RP at VHH to E going high Pulse duration, E low NOTE 15: A–1 – A16 for byte-wide 58 MIN UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F200AFy (automotive temperature range) write/erase operations — E-controlled writes ALT ALT. SYMBOL ’28F002AFy 70 ’28F200AFy 70 ’28F002AFy 80 ’28F200AFy 80 ’28F002AFy 90 ’28F200AFy 90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN tc( E ) Cycle time, write MAX MIN MAX MIN UNIT MAX tAVAV 70 80 90 ns tc(E)OP Cycle time, duration of programming operation tEHQV1 6 6 7 µs tc(E)ERB Cycle time, erase operation (boot block) tEHQV2 0.3 0.3 0.4 s tc(E)ERP Cycle time, erase operation (parameter block) tEHQV3 0.3 0.3 0.4 s tEHQV4 tPHBR 0.6 tc(E)ERM td(RPR) Cycle time, erase operation (main block) th(A) th(D) Hold time, A0 – A16 (see Note 15) th( W ) th (VPP) Hold time, W th(RP) Delay time, boot-block relock 0.6 100 0.7 100 s 100 ns tEHAX tEHDX tEHEH 0 0 0 ns 0 0 0 ns 0 0 0 ns Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns Hold time, RP status-register bit tQVPH 0 0 0 ns tWHPL tELPH 0 0 0 ns 50 50 50 ns 50 50 50 ns 50 50 50 ns Hold time, DQ valid at VHH from valid th(WP) tsu(WP) Hold time, WP from valid status-register bit tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu( W ) tsu(RP) Setup time, W before write operation tsu( VPP)2 tw(E) Setup time, VPP to E going high tw( EH) trec(RPHE) Pulse duration, E high Recovery time, RP high to E going low Setup time, WP before write operation Setup time, DQ valid Setup time, RP at VHH to E going high Pulse duration, E low tAVEH tDVEH tWLEL tPHHEH tVPEH 0 0 0 ns 100 100 100 ns 100 100 100 ns tELEH tEHEL 60 60 60 ns 20 30 40 ns tPHEL 300 300 300 ns NOTE 15: A–1 – A16 for byte-wide POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 TMS28F002AZy and TMS28F200AZy The TMS28F002AZy and TMS28F200AZy configurations offer a 5-V memory read with a 12-V program and a 12-V erase for fast programming and erasing times. These configurations are offered in three temperature ranges: 0°C to 70°C,– 40°C to 85°C and – 40°C to 125°C. recommended operating conditions for TMS28F002AZy and TMS28F200AZy VCC Supply voltage During write/read/erase/erase-suspend 5-V VCC range During read only VPPL 12-V VPP range VPP Supply voltage VIH High level dc input voltage High-level VIL Low level dc input voltage Low-level VLKO VHH VCC lock-out voltage from write/erase (see Note 7) RP unlock voltage VPPLK VPP lock-out voltage from write/erase TA Operating free-air temperature during read/erase/program During write/erase/erase-suspend MIN NOM MAX 4.5 5 5.5 0 11.4 TTL 6.5 12 2 CMOS VCC + 0.3 VCC + 0.2 VCC – 0.2 – 0.3 TTL CMOS 0.8 VSS – 0.2 2 11.4 12.6 VSS + 0.2 UNIT V V V V V 13 V 0 12 1.5 V L suffix 0 70 E suffix – 40 85 Q suffix – 40 125 °C NOTE 7:. Minimum value at TA = 25°C. word/byte typical write and block-erase performance for TMS28F002AZy and TMS28F200AZy (see Notes 8 and 9) PARAMETER 12-V VPP AND 5-V VCC RANGES MIN TYP MAX Main block-erase time 1.1 14 Main block-byte program time 1.2 4.2 Main block-word program time 0.6 2.1 Parameter/ boot-block erase time 0.34 7 NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions. 9. Excludes system-level overhead (all times in seconds) 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 electrical characteristics for TMS28F002AZy and TMS28F200AZy over recommended ranges of supply voltage and operating free-air temperature using test conditions given in Table 9 (unless otherwise noted) PARAMETER VOH High-level g dc output voltage TEST CONDITIONS TTL VCC = VCCMIN, IOH = – 2.5 mA CMOS VCC = VCCMIN, IOH = – 100 µA MIN MAX UNIT 2.4 V VCC – 0.4 VOL Low-level dc output voltage VCC = VCCMIN, IOL = 5.8 mA VID A9 selection code voltage During read algorithm-selection mode II Input current (leakage), except for A9 when A9 = VID (see Note 10) VCC = VCCMAX, VI = 0 V to VCCMAX, RP = VHH A9 selection code current 0.45 V 12.6 V ±1 µA A9 = VID 500 µA RP boot-block unlock current RP = VHH 500 µA IO Output current (leakage) VCC = VCCMAX, VO = 0 V to VCCmax ±10 µA IPPS VPP standby current (standby) VPP supply current (reset / deep power-down mode) VPP ≤ VCC 5-V VCC range 10 µA RP = VSS ± 0.2 V, VPP ≤ VCC 5-V VCC range 5 µA VPP ≥ VCC 5-V VCC range 200 µA IPP2 VPP supply current (active read) VPP supply current (active byte-write) (see Notes 11 and 12) Programming in progress 12-V VPP range, 5-V VCC range 20 mA IPP3 VPP supply current (active word-write) (see Notes 11 and 12) Programming in progress 12-V VPP range, 5-V VCC range 20 mA IPP4 VPP supply current (block-erase) (see Notes 11 and 12) Block-erase in progress 12-V VPP range, 5-V VCC range 15 mA IPP5 VPP supply current (erase-suspend) (see Notes 11 and 12) Block-erase suspended 12-V VPP range, 5-V VCC range 200 µA ICCS VCC supply y current (standby) VCC = VCCmax,, E = RP = VIH 5 V VCC range 5-V 2 mA 130 µA ICCL l currentt (reset ( t / deep d VCC supply ower-down mode) power-down IID IRP IPPL IPP1 ICC1 y current VCC supply (active read) TTL-input level CMOS-input level RP = VSS ± 0.2 V 11.4 0°C to 70°C 8 – 40°C to 85°C 8 – 40°C to 125°C 30 µA TTL-input level E = VIL, G = VIH IOUT = 0 mA, f = 10 MHz, 5-V VCC range 65 mA CMOS-input level E = VSS, G = VCC, IOUT = 0 mA, f = 10 MHz, 5-V VCC range 60 mA ICC2 VCC supply current (active byte-write) (see Notes 11 and 12) VCC = VCCMAX, Programming in progress 12-V VPP range, 5-V VCC range 50 mA ICC3 VCC supply current (active word-write) (see Notes 11 and 12) VCC = VCCMAX, Programming in progress 12-V VPP range, 5-V VCC range 45 mA ICC4 VCC supply current (block-erase) (see Notes 11 and 12) VCC = VCCMAX, Block erase in progress 12-V VPP range, 5-V VCC range 45 mA ICC5 VCC supply current (erase-suspend) (see Notes 11 and 12) VCC = VCCMAX, E = VIH, Block erase suspended 5-V VCC range 10 mA NOTES: 10. DQ15/A–1 is tested for output leakage only. 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 power-up and reset switching characteristics for TMS28F002AZy and TMS28F200AZy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7) ’28F002AZy 60 ’28F200AZy 60 ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy 80 ’28F200AZy 80 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE ALT ALT. SYMBOL PARAMETER MIN MAX MIN MAX MIN UNIT MAX tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) tPL5V tPL3V ta(DV) Address valid to data valid for VCC = 5 V ± 10% tAVQV 60 70 80 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% tPHQV 450 450 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. 0 0 2 0 2 ns µs 2 power-up and reset switching characteristics for TMS28F002AZy and TMS28F200AZy over recommended ranges of supply voltage (automotive temperature range) (see Notes 11, 12, and 13) ALT ALT. SYMBOL PARAMETER ’28F002AZy70 ’28F200AZy70 ’28F002AZy80 ’28F200AZy80 ’28F002AZy90 ’28F200AZy90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN MAX MIN MAX MIN UNIT MAX tsu(VCC) Setup time, RP low to VCC at 4.5 V MIN (to VCC at 3 V MIN or 3.6 V MAX) (see Note 14) tPL5V tPL3V ta(DV) Address valid to data valid for VCC = 5 V ± 10% tAVQV 70 80 90 ns tsu(DV) Setup time, RP high to data valid for VCC = 5 V ± 10% tPHQV 450 450 450 ns th(RP5) Hold time, VCC at 4.5 V (MIN) to RP high t5VPH NOTES: 11. Characterization data available 12. All ac current values are RMS unless otherwise noted. 13. E and G are switched low after power up. 14. The power supply can switch low concurrently with RP going low. 62 POST OFFICE BOX 1443 0 0 2 • HOUSTON, TEXAS 77251–1443 2 0 2 ns µs TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 switching characteristics for TMS28F002AZy and TMS28F200AZy over recommended ranges of supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7) read operations ALT ALT. SYMBOL PARAMETER ’28F002AZy60 ’28F200AZy 60 ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy 80 ’28F200AZy 80 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN ta(A) ta(E) Access time from A0 – A16 (see Note 15) ta(G) tc(R) Access time from G td(E) td(G) Delay time, E low to low-impedance output tdis(E) tdis(G) Disable time, E to high-impedance output Access time from E Cycle time, read Delay time, G low to low-impedance output MAX MIN MAX MIN UNIT MAX tAVQV tELQV 60 70 80 ns 60 70 80 ns tGLQV tAVAV 35 40 40 ns tELQX tGLQX 60 70 80 ns 0 0 0 ns 0 0 0 ns Disable time, G to high-impedance output tEHQZ tGHQZ th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 ns td(RP) Output delay time from RP high tPHQV 450 450 450 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in high-impedance state tFLQZ 25 30 30 ns tFHQV 60 70 80 ns ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide POST OFFICE BOX 1443 25 30 30 ns 25 30 30 ns 0 0 • HOUSTON, TEXAS 77251–1443 0 ns 63 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 switching characteristics for TMS28F200AZy over recommended ranges of supply voltage (automotive temperature range) (see Table 9 and Figure 7) read operations ALT ALT. SYMBOL PARAMETER ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy 80 ’28F200AZy 80 ’28F002AZy90 ’28F200AZy90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN ta(A) ta(E) Access time from A0 – A16 (see Note 15) ta(G) tc(R) Access time from G td(E) td(G) Delay time, E low to low-impedance output tdis(E) tdis(G) Disable time, E to high-impedance output Access time from E Cycle time, read Delay time, G low to low-impedance output MAX MIN MAX MIN UNIT MAX tAVQV tELQV 70 80 90 ns 70 80 90 ns tGLQV tAVAV 35 40 45 ns tELQX tGLQX 70 80 90 ns 0 0 0 ns 0 0 0 ns Disable time, G to high-impedance output tEHQZ tGHQZ th(D) Hold time, DQ valid from A0 – A16, E, or G, whichever occurs first (see Note 15) tAXQX tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 ns td(RP) Output delay time from RP high tPHQV 300 300 300 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in high-impedance state tFLQZ 30 30 35 ns ta(BH) Access time from BYTE going high NOTE 15: A–1 – A16 for byte-wide tFHQV 70 80 90 ns 64 • HOUSTON, TEXAS 77251–1443 POST OFFICE BOX 1443 25 30 35 ns 25 30 35 ns 0 0 0 ns TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F002AZy and TMS28F200AZy (commercial and extended temperature ranges) write/erase operations — W-controlled writes ALT ALT. SYMBOL ’28F002AZy 60 ’28F200AZy 60 ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy80 ’28F200AZy80 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN MAX MIN MAX MIN UNIT MAX tc( W ) Cycle time, write tAVAV 60 70 80 ns tc( W )OP Cycle time, duration of programming operation tWHQV1 6 6 6 µs tc( W )ERB Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 0.6 s td(RPR) th(A) Delay time, boot-block relock th(D) th(E) Hold time, DQ valid Hold time, A0 – A16 (see Note 15) tPHBR tWHAX 100 100 100 ns 0 0 0 ns 0 0 0 ns Hold time, E tWHDX tWHEH 0 0 0 ns th( VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns 50 50 50 ns 50 50 50 ns 0 0 0 ns tPHHWH tVPWH 100 100 100 ns 100 100 100 ns 50 50 50 ns 10 20 30 ns 450 450 450 ns tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) Setup time, DQ tAVWH tDVWH tsu(E) tsu(RP) Setup time, E before write operation tELWL tsu( VPP)1 tw( W ) Setup time, VPP to W going high tw( WH) trec(RPHW) Pulse duration, W high tWLWH tWHWL Recovery time, RP high to W going low tPHWL Setup time, RP at VHH to W going high Pulse duration, W low NOTE 15: A–1 – A16 for byte-wide POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F200AZy (automotive temperature ranges) write/erase operations — W-controlled writes ALT ALT. SYMBOL ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy 80 ’28F200AZy 80 ’28F002AZy 90 ’28F200AZy 90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN tc( W ) Cycle time, write MAX MIN MAX MIN UNIT MAX tAVAV 70 80 90 ns tc( W )OP Cycle time, duration of programming operation tWHQV1 6 6 7 µs tc( W )ERB Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.4 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.4 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 td(RPR) th(A) Delay time, boot-block relock th(D) th(E) Hold time, DQ valid th( VPP) th(RP) tPHBR tWHAX Hold time, A0 – A16 (see Note 15) 0.6 100 s 100 ns 0 0 0 ns 0 0 0 ns Hold time, E tWHDX tWHEH 0 0 0 ns Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns 50 50 50 ns 50 50 50 ns 0 0 0 ns tPHHWH tVPWH 100 100 100 ns 100 100 100 ns 60 60 60 ns 20 30 40 ns 220 220 220 ns tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) Setup time, DQ tAVWH tDVWH tsu(E) tsu(RP) Setup time, E before write operation tELWL tsu( VPP)1 tw( W ) Setup time, VPP to W going high tw( WH) trec(RPHW) Pulse duration, W high tWLWH tWHWL Recovery time, RP high to W going low tPHWL Setup time, RP at VHH to W going high Pulse duration, W low NOTE 15: A–1 – A16 for byte-wide 66 0.7 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F002AZy and TMS28F200AZy (commercial and extended temperature ranges) write/erase operations — E-controlled writes ALT ALT. SYMBOL ’28F002AZy 60 ’28F200AZy 60 ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy80 ’28F200AZy80 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN tc( E ) tc(E)OP Cycle time, write tc(E)ERB tc(E)ERP Cycle time, erase operation (boot block) tc(E)ERM td(RPR) Cycle time, erase operation (main block) th(A) th(D) Hold time, A0 – A16 (see Note 15) th( W ) th (VPP) th(RP) Cycle time, duration of programming operation Cycle time, erase operation (parameter block) Delay time, boot-block relock tAVAV tEHQV1 tEHQV2 tEHQV3 tEHQV4 tPHBR tEHAX MAX MIN MAX MIN UNIT MAX 60 70 80 ns 6 6 6 µs 0.3 0.3 0.3 s 0.3 0.3 0.3 s 0.6 0.6 0.6 s 100 100 100 ns 0 0 0 ns 0 0 0 ns Hold time, W tEHDX tEHWH 0 0 0 ns Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns tAVEH tDVEH tWLEL 50 50 50 ns 50 50 50 ns 0 0 0 ns tPHHEH tVPEH 100 100 100 ns 100 100 100 ns Hold time, DQ valid tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) tsu( W ) tsu(RP) Setup time, W before write operation tsu( VPP)2 tw(E) Setup time, VPP to E going high 50 50 ns Pulse duration, E high tELEH tEHEL 50 tw( EH) trec(RPHE) 10 20 30 ns Recovery time, RP high to E going low tPHEL 450 450 450 ns Setup time, DQ valid Setup time, RP at VHH to E going high Pulse duration, E low NOTE 15: A–1 – A16 for byte-wide POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 timing requirements for TMS28F200AZy (automotive temperature range) write/erase operations — E-controlled writes ALT ALT. SYMBOL ’28F002AZy 70 ’28F200AZy 70 ’28F002AZy 80 ’28F200AZy 80 ’28F002AZy 90 ’28F200AZy 90 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE MIN tc( E ) Cycle time, write MAX MIN MAX MIN UNIT MAX tAVAV 70 80 90 ns tc(E)OP Cycle time, duration of programming operation tEHQV1 6 6 7 µs tc(E)ERB Cycle time, erase operation (boot block) tEHQV2 0.3 0.3 0.4 s tc(E)ERP Cycle time, erase operation (parameter block) tEHQV3 0.3 0.3 0.4 s tEHQV4 tPHBR 0.6 0 0 0 ns 0 0 0 ns 0 0 0 ns tc(E)ERM td(RPR) Cycle time, erase operation (main block) th(A) th(D) Hold time, A0 – A16 (see Note 15) th( W ) th (VPP) Hold time, W tEHAX tEHDX tEHWH Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns 50 50 50 ns 50 50 50 ns 0 0 0 ns tPHHEH tVPEH 100 100 100 ns 100 100 100 ns 60 60 60 ns 20 30 40 ns 300 300 300 ns th(RP) Delay time, boot-block relock Hold time, DQ valid tsu(A) tsu(D) Setup time, A0 – A16 (see Note 15) Setup time, DQ valid tAVEH tDVEH tsu( W ) tsu(RP) Setup time, W before write operation tWLEL tsu( VPP)2 tw(E) Setup time, VPP to E going high tw( EH) trec(RPHE) Pulse duration, E high tELEH tEHEL Recovery time, RP high to E going low tPHEL Setup time, RP at VHH to E going high Pulse duration, E low 0.6 100 NOTE 15: A–1 – A16 for byte-wide 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0.7 100 s 100 ns PARAMETER MEASUREMENT INFORMATION RP (P) 5.0 V 4.5 V 3.3 V VCC (3 V, 5 V) 3.0 V 0V th(RP3) tsu(VCC) th(RP5) Valid Valid ta(DV) ta(DV) Data (D) Valid 3.3 Outputs tsu(DV) Figure 10. Power-Up Timing and Reset Switching Valid 5.0 Outputs tsu(DV) SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 69 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Address (A) TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION tc(R) A –1 – A16 (byte-wide) A0 – A16 (word-wide) Address Valid ta(A) E tdis(E) ta(E) G tdis(G) ta(G) W td(G) th(D) td(E) DQ0 – DQ7 (byte-wide) DQ0 – DQ15 (word-wide) VCC Hi-Z Hi-Z td(RP) RP Figure 11. Read-Cycle Timing 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION Power Up and A –1 – A16 Standby (byte-wide) A0 – A16 (word-wide) Write Program-Setup Command Write Valid Address or Data Automated Byte- / WordProgramming Write Read-Array Command Read StatusRegister Bits tc(W) tsu(A) th(A) E tsu(E) th(E) G tc( W )OP tw( WH ) W DQ0 – DQ7 (byte-wide) DQ0 – DQ15 (word-wide) tw( W ) tsu(D) th(D) Data Valid SR Hi-Z Hi-Z FFh Hi-Z 40h or 10h trec(RPHW) tsu(RP) th(RP) RP tsu(WP) th(WP) WP th( VPP) tsu( VPP)1 VPP Figure 12. Write-Cycle Timing ( W-Controlled Write) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION Power Up and – A16 Standby A –1 (byte - wide) A0 – A16 (word - wide) Write Program-Setup Command Automated Byte - / Word Programming Write Valid Address And Data tc( E ) Read Status Register Bits Write Read-Array Command tsu(A) th(A) W tsu( W ) th( W ) G tc(E)OP tw(EH) E DQ0 – DQ7 (byte - wide) DQ0 – DQ15 (word - wide) tw(E) tsu(D) th(D) Data Valid SR Hi-Z Hi-Z Hi-Z 40h or 10h tsu(RP) trec(RPHE) th(RP) RP tsu(WP) th(WP) WP tsu( VPP)2 VPP Figure 13. Write-Cycle Timing (E-Controlled Write) 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 FFh th( VPP) TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION Power Up and A –1 – A16 Standby (byte - wide) A0 – A16 (word - wide) Write Erase - Setup Command Write EraseConfirm Command Automated Erase tc( W ) Read StatusRegister Bits Write Read-Array Command tsu(A) th(A) E tsu(E) th(E) G tc( W )ERB tc( W )ERP tc( W )ERM tw( WH) W DQ0 – DQ7 (byte - wide) DQ0 – DQ15 (word - wide) tw( W ) tsu(D) th(D) Hi-Z D0h Valid SR Hi-Z 20h trec(RPHW) FFh Hi-Z tsu(RP) th(RP) VHH VIH RP tsu(WP) th(WP) WP tsu( VPP)1 th( VPP) VPPH VPPL VPP Figure 14. Erase-Cycle Timing (W-Controlled Write) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION Power Up and A –1 – A16 Standby (byte-wide) A0 – A16 (word-wide) Write Erase-Setup Command Write EraseConfirm Command tc( E ) Automated Erase Read StatusRegister Bits Write Read-Array Command tsu(A) th(A) W tsu( W ) th( W ) G tc(E)ERB tc(E)ERP tc(E)ERM tw(EH) E DQ0 – DQ7 (byte-wide) DQ0 – DQ15 (word-wide) tw(E) tsu(D) th(D) Hi-Z D0h Valid SR Hi-Z 20h trec(RPHE) Hi-Z tsu(RP) th(RP) RP tsu(WP) th(WP) WP tsu( VPP)2 VPP Figure 15. Erase-Cycle Timing (E-Controlled Write) 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 FFh th( VPP) TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION A–1 – A16 (byte-wide) A0 – A16 (word-wide) Address Valid tc( R ) ta(A) E ta(E) tdis(E) G tdis(G) ta(G) BYTE th(D) tsu(EB) DQ0 – DQ7 Hi-Z Hi-Z Byte DQ0 – DQ7 td(G) Word DQ0 – DQ7 td(E) DQ8 – DQ14 Hi-Z Hi-Z ta(A) tdis(BL) Word DQ8 – DQ14 DQ15/A –1 Hi-Z A –1 Input Hi-Z Word DQ15 Figure 16. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 75 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION A –1 – A16 (byte-wide) A0 – A16 (word-wide) Address Valid tc( R ) ta(A) E ta(E) tdis(E) G tdis(G) ta(G) BYTE th(D) tsu(EB) Byte DQ0 – DQ7 ta(BH) DQ0 – DQ7 Hi-Z Hi-Z td(G) Word DQ0 – DQ7 td(E) DQ8 – DQ14 Hi-Z Hi-Z Word DQ8 – DQ14 Word DQ15 DQ15/A –1 A –1 Input Hi-Z Figure 17. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode 76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Hi-Z TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 MECHANICAL DATA DBJ (R-PDSO-G44) PLASTIC SMALL-OUTLINE PACKAGE 0,45 0,35 1,27 0,16 M 44 23 13,40 13,20 16,10 15,90 0,15 NOM 1 22 28,30 28,10 Gage Plane 0,25 0°– 8° 0,80 Seating Plane 2,625 MAX 0,50 MIN 0,10 4073325 / A 10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 77 TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 MECHANICAL DATA DCD (R-PDSO-G**) PLASTIC DUAL SMALL-OUTLINE PACKAGE 40 PIN SHOWN NO. OF PINS ** MAX MIN 40 0.402 (10,20) 0.385 (9,80) 48 0.476 (12,10) 0.469 (11,90) 1 40 0.020 (0,50) A A 0.012 (0,30) 0.004 (0,10) 0.008 (0,21) M 21 20 0.728 (18,50) 0.720 (18,30) 0.795 (20,20) 0.780 (19,80) 0.041 (1,05) 0.037 (0,95) 0.006 (0,15) NOM 0.047 (1,20) MAX Seating Plane 0.028 (0,70) 0.020 (0,50) 0.004 (0,10) 0.010 (25,00) NOM 4073307/B 07/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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