TI PT5527C

PT5520 Series
1.5-A 5-V/3.3-V Input Adjustable
Integrated Switching Regulator
SLTS147A
(Revised 10/5/2001)
Features
•
•
•
•
•
•
•
•
•
Single-Device: 5V/3.3V Input
DSP Compatible
89% Efficiency
Small Footprint
Space-Saving package
Adjustable Output Voltage
Output Inhibit Function
Short Circuit Protection
Solderable Copper Case
Description
Ordering Information
The PT5520 Excalibur™ power modules
are a series of high-performance Integrated
Switching Regulators (ISRs). Rated 1.5A,
these modules operate from input voltages as
low as 3.1V to provide a local step-down
power source. They are an ideal compliment
to the industry’s latest high-performance DSPs
and microprocessors. The series includes
output voltage options as low as 1.0VDC.
The PT5520 series is packaged in a 5-pin
thermally efficient copper case. The case is
solderable, has a small footprint, and can
accommodate both through-hole and surface
mount pin configurations.
The product features external output
voltage adjustment, an inhibit function, and
short circuit protection. A 100µF capacitor
is required for proper operation.
PT5521¨
PT5522¨
PT5523¨
PT5524¨
PT5525¨
PT5526¨
PT5527¨
Pin-Out Information
Pin Function
=3.3 Volts
=2.5 Volts
=2.0 Volts
=1.8 Volts
=1.5 Volts
=1.2 Volts
=1.0 Volts
PT Series Suffix (PT1234 x )
Case/Pin
Configuration
Order
Suffix
N
A
C
Vertical
Horizontal
SMD
1
Inhibit *
2
3
Vin
GND
4
Vo
5
Vo Adjust
* For Inhibit pin:
Open = output enabled
Ground = output disabled
Package
Code
(EFK)
(EFL)
(EFM)
(Reference the applicable package code drawing for the dimensions and PC board layout)
Standard Application
INH
V OA D J
5
1
+ V IN
2
PT5520
+VO
4
+
3
C1
COM
C2
COM
C1 = Optional 1µF ceramic
C2 = Required 100µF (See Notes)
For technical support and more information, see inside back cover or visit www.ti.com
PT5520 Series
1.5-A 5-V/3.3-V Input Adjustable
Integrated Switching Regulator
Specifications
(Unless otherwise stated, Ta =25°C, Vin =5V, Cout =100µF, and Io =I omax)
Characteristics
Symbols
Output Current
Input Voltage Range
Io
Vin
Set-Point Voltage Tolerance
Temperature Variation
Line Regulation
Load Regulation
Total Output Variation
Vo tol
∆Regtemp
∆Regline
∆Regload
∆Regtot
Efficiency
η
Vo Ripple (pk-pk)
Transient Response
Current Limit
Switching Frequency
Inhibit Control (pin1)
Input High Voltage
Input Low Voltage
Input Low Current
External Capacitance
Absolute Maximum
Operating Temperature Range
Storage Temperature
Mechanical Shock
Over Vin range
Over Io range
Min
Vo =3.3V
Vo ≤2.5V
–40°C <Ta <+85°C
Over Vin range
Over Io range
Includes set-point, line, load,
–40°C ≤ T a ≤ +85°C
PT5521
PT5522
PT5523
PT5524
PT5525
PT5526
PT5527
Vr
ttr
∆Vtr
Ilim
ƒo
20MHz bandwidth
1A/µs load step from 50% to 100% I omax
V o over/undershoot
VIH
VIL
IIL
Cout
Ta
Referenced to GND (pin3)
Ts
—
Per Mil-STD-883D, Method 2002.3 , 1 msec,
Half Sine, mounted to a fixture
Per Mil-STD-883D, Method 2007.2,
20-2000 Hz, Soldered in a PC board
—
Materials meet UL 94V-0
Mechanical Vibration
Weight
Flammability
Conditions
—
—
Over Vin and Io ranges
Pin 1 to GND
Over Vin range
0.1 (1)
4.5
3.1
—
—
—
—
PT5520 SERIES
Typ
Max
—
—
Units
A
V
—
±0.5
—
—
1.5
5.5
5.5
±2
—
±6
±10
—
—
±3
%Vo
—
—
—
—
—
—
—
—
—
—
—
—
89
86
84
83
81
79
76
15
50
50
4
600 (2)
—
—
—
—
—
—
—
30
—
100
—
—
mV
µSec
mV
A
kHz
Vin –0.5
–0.2
—
100 (4)
–40 (5)
—
—
–0.5
—
—
Open (3)
0.5
—
—
+85 (6)
mA
µF
°C
-40
—
—
500
+125
—
°C
G’s
—
—
15 (7)
6.5
—
—
G’s
grams
%Vo
%Vo
mV
mV
%
V
Notes: (1) The ISR will operate down to no load with reduced specifications.
(2) This is a typical value only. The switching frequency will vary with input voltage.
(3) The Inhibit control (pin 1) has an internal pull-up, and if left open-circuit the module will operate when input power is applied. A small low-leakage
(<100nA) MOSFET is recommended to control this input. Ensure an On/Off transition time of ≤ 10µs. See application notes for more information.
(4) The PT5520 Series requires a 100µF electrolytic or tantalum output capacitor for proper operation in all applications.
(5) For operation below 0°C, the output capacitor C2 must have stable characteristics. Use either a low ESR tantalum or Oscon® capacitor.
(6) See SOA curves or consult factory for the appropriate derating.
(7) The case pins on the through-hole package types (suffixes N & A) must be soldered. For more information see the applicable package outline drawing.
For technical support and more information, see inside back cover or visit www.ti.com
Typical Characteristics
PT5520 Series
1.5-A 5-V/3.3-V Input Adjustable
Integrated Switching Regulator
Performance Data; Vin =5.0V (See Note A)
Performance Data; Vin =3.3V (See Note A)
Efficiency vs Output Current
Efficiency vs Output Current
100
100
90
90
Efficiency - %
80
70
60
PT5522
PT5523
PT5524
PT5525
PT5526
PT5527
80
Efficiency - %
PT5521
PT5522
PT5523
PT5524
PT5525
PT5526
PT5527
70
60
50
50
40
40
0
0.3
0.6
0.9
1.2
0
1.5
0.3
0.6
Ripple vs Output Current
15
PT5522
PT5523
PT5524
PT5521
PT5525
PT5526
PT5527
10
5
Ripple - mV
Ripple - mV
1.5
20
15
PT5522
PT5523
PT5524
PT5525
PT5526
PT5527
10
5
0
0
0
0.3
0.6
0.9
1.2
1.5
0
0.3
0.6
Iout (A)
0.9
1.2
1.5
Iout (A)
Power Dissipation vs Output Current
Power Dissipation vs Output Current
0.75
1
0.6
PT5521
PT5522
PT5523
PT5524
PT5525
PT5526
PT5527
0.6
0.4
Pd - Watts
0.8
Pd - Watts
1.2
Ripple vs Output Current
20
0.2
PT5522
PT5523
PT5524
PT5525
PT5526
PT5527
0.45
0.3
0.15
0
0
0
0.3
0.6
0.9
1.2
0
1.5
0.3
0.6
Iout (A)
0.9
1.2
1.5
Iout (A)
Safe Operating Area; Vin =5.0V (See Note B)
Safe Operating Area; Vin =3.3V (See Note B)
90.0
90.0
80.0
80.0
70.0
Airflow
200LFM
120LFM
60LFM
Nat conv
60.0
50.0
40.0
30.0
Ambient Temperature (°C)
Ambient Temperature (°C)
0.9
Iout (A)
Iout (A)
70.0
200LFM
120LFM
60LFM
Nat conv
60.0
50.0
40.0
30.0
20.0
20.0
0.0
0.3
0.6
0.9
1.2
1.5
0.0
Iout (A)
0.3
0.6
0.9
1.2
1.5
Iout (A)
Note A: Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the ISR.
Note B: SOA curves represent operating conditions at which internal components are at or below manufacturer’s maximum rated operating temperatures.
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT5500/5520 Series
Adjusting the Output Voltage of the PT5500/20
Series of Excalibur Step-Down ISRs
The output voltage of both the PT5500 and PT5520
series ISRs may be adjusted higher or lower than the
factory trimmed pre-set voltage with the addition of a
single external resistor. Table 1 accordingly gives the
allowable adjustment range for each model for either
series as Va (min) and Va (max).
Adjust Up:
An increase in the output voltage is obtained by
adding a resistor R2, between pin 5 (Vo adj) and pin 3 (GND).
Adjust Down:
pin 4 (Vout).
Add a resistor (R1), between pin 5 (Vo adj) and
Notes:
1. Use only a single 1% resistor in either the (R1) or R2
location. Place the resistor as close to the ISR as possible.
2. Never connect capacitors from Vo adj to either GND or
Vout. Any capacitance added to the Vo adjust pin will
affect the stability of the ISR.
3. For each model, adjustments to the output voltage may
place additional limits on the minimum input voltage.
The revised minimum input voltage must comply with the
following requirement.
Vin(min) = (Va + 0.5)V or as specified in the data sheet,
whichever is greater.
Figure 1
2
+ V IN
V in
PT5500
GND
3
4
Vo
+VO
Vo(adj)
5
C1
1 µF C e r a m i c
(Optional)
(R1)
Adj Down
C2
1 0 0 µF
(Req'd)
+
R2
Adjust Up
COM
COM
The values of (R1) [adjust down], and R2 [adjust up], can
also be calculated using the following formulas. Refer to
Figure 1 and Table 2 for both the placement and value of the
required resistor; either (R1) or R2 as appropriate.
Ro (Va – 0.9)
Vo – Va
(R1)
=
R2
=
Where:
Vo
Va
Ro
Rs
0.9 Ro
Va – Vo
– Rs
kΩ
– Rs
kΩ
= Original output voltage
= Adjusted output voltage
= The resistance value from Table 1
= The series resistance from Table 1
Table 1
ISR ADJUSTMENT RANGE AND FORMULA PARAMETERS
3.0 Adc Rated
PT5501
PT5502
PT5503
1.5 Adc Rated
PT5521
PT5522
PT5523
PT5504
PT5524
PT5505
PT5525
PT5506
PT5526
PT5507
PT5527
Vo (nom)
3.3
2.5
2.0
1.8
1.5
1.2
1.0
Va (min)
2.88
1.97
1.64
1.5
1.3
1.08
0.97
Va (max)
3.5
Ω)
Ro (kΩ
10.0
10.0
2.95
10.0
2.45
10.0
2.25
10.0
1.95
10.0
10.2
Rs (kΩ)
49.9
20.0
20.0
20.0
20.0
20.0
20.0
For technical support and more information, see inside back cover or visit www.ti.com
1.65
1.45
Application Notes continued
PT5500/5520 Series
Table 2
ISR ADJUSTMENT RESISTOR VALUES
3.0 Adc Rated
PT5501
PT5502
1.5 Adc Rated
PT5521
PT5522
Vo (nom)
3.3
2.5
Va (req.d)
PT5503
PT5523
2.0
PT5504
PT5524
1.8
PT5505
PT5525
1.5
PT5506
PT5526
1.2
0.97
PT5507
PT5527
1.0
(0.0)kΩ
1.0
1.05
164.0kΩ
1.1
(0.0)kΩ
1.15
(30.0)kΩ
1.2
72.8kΩ
41.2kΩ
25.9kΩ
1.25
160.0kΩ
16.7kΩ
1.3
(0.0)kΩ
70.0kΩ
10.6kΩ
1.35
(10.0)kΩ
40.0kΩ
6.2kΩ
1.4
(30.0)kΩ
25.0kΩ
3.0kΩ
1.45
(90.0)kΩ
16.0kΩ
0.4kΩ
1.5
(0.0)kΩ
10.0kΩ
1.55
(6.0)kΩ
160.0kΩ
5.7kΩ
1.6
(15.0)kΩ
70.0kΩ
2.5kΩ
0.0kΩ
1.65
(1.4)kΩ
(30.0)kΩ
40.0kΩ
1.7
(6.7)kΩ
(60.0)kΩ
25.0kΩ
1.75
(14.0)kΩ
(150.0)kΩ
1.8
(25.0)kΩ
1.85
(43.3)kΩ
160.0kΩ
5.7kΩ
1.9
(80.0)kΩ
70.0kΩ
2.5kΩ
1.95
(190.0)kΩ
40.0kΩ
0.0kΩ
2.0
(2.0)kΩ
16.0kΩ
10.0kΩ
25.0kΩ
2.05
(5.6)kΩ
160.0kΩ
16.0kΩ
2.1
(10.0)kΩ
70.0kΩ
10.0kΩ
2.15
(15.7)kΩ
0.0kΩ
5.7kΩ
2.2
(23.3)kΩ
25.0kΩ
2.5kΩ
2.25
(34.0)kΩ
16.0kΩ
0.0kΩ
2.3
(50.0)kΩ
10.0kΩ
2.35
(76.7)kΩ
5.7kΩ
2.4
(130.0)kΩ
2.5kΩ
2.45
(284.0)kΩ
0.0kΩ
2.5
2.55
160.0kΩ
2.6
70.0kΩ
2.65
40.0kΩ
2.7
25.0kΩ
2.75
16.0kΩ
2.8
10.0kΩ
2.85
2.9
5.7kΩ
(0.0kΩ
2.5kΩ
2.95
(8.5)kΩ
0.0kΩ
3.0
(20.1)kΩ
3.05
(36.1)kΩ
3.1
(60.1)kΩ
3.15
(100.0)kΩ
3.2
(180.0)kΩ
3.25
(420.0)kΩ
3.3
3.35
130.0kΩ
3.4
40.1kΩ
3.45
10.1kΩ
3.48
R1 = (Blue)
0.0kΩ
R2 = Black
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT5500/5520 Series
Using the Inhibit Control on the PT5500/PT5520
Series of Excalibur Step-Down ISRs
For applications requiring output voltage On/Off control,
both the PT5500 and PT5520 series of power modules
incorporate an inhibit function. This function can be used
for power-up sequencing or wherever there is a requirement for the module to be switched off. The On/Off
function is provided by the Inhibit (pin 1) control.
The ISR functions normally with Pin 1 open-circuit,
providing a regulated output whenever a valid source
voltage is applied to Vin, (pin 2). When a low-level2
ground signal is applied to pin 1, the regulator output
will be disabled.
Figure 1 shows an application schematic, which details
the typical use of the Inhibit function. Note the discrete
transistor (Q1). The Inhibit control has its own internal
pull-up to +Vin potential. An open-collector or opendrain device is required to control this pin.
Turn-On Time: In the circuit of Figure 1, turning Q1 on applies
a low-voltage to the Inhibit control (pin 1) and disables the
regulator output. Correspondingly, turning Q1 off allows the
Inhibit control pin to be pulled high by its internal pull-up
resistor. The ISR produces a fully regulated output voltage
within 10-msec of the release of the Inhibit control pin. The
actual turn-on time will vary with input voltage, output
load, and the total amount of load capacitance. Figure 2
shows the typical rise in both output voltage and input
current for a PT5502 (2.5V) following the turn-off of Q1 at
time t =0. The waveform was measured with a 5Vdc input
voltage, and 2.5A resistive load.
Figure 2
Vo (1V / Div)
The Inhibit pin control thresholds are given in Table 1.
Equation 1 may be used to determine the approximate
current drawn from the input source, and by Q1 when the
regulator is in the inhibit state.
IIN (1A / Div)
VINH (5V / Div)
Table 1; Inhibit Control Requirements
Parameter
Enable (VIH)
Disable (VIL)
Min
Max
Vin – 0.5
–0.2V
Open
-1
0
+0.5V
1
2
3
4
5
6
7
8
t (milli-secs)
Equation 1
= Vin ÷ 10kΩ
Iinh
± 20%
Figure 1
+ V IN
2
V in
INH
1
C1, 1 µF
(Optional)
Inhibit
COM
PT5502
Q1
BSS138
Vo
+VO
4
GND
3
C2
1 0 0µF
+
COM
Notes:
1. Use an open-collector device (preferably a discrete
transistor) for the Inhibit input. A pull-up resistor is not
necessary. To disable the output voltage, the control pin
should be pulled low to less than +0.5VDC.
2. Do not control the Inhibit input with an external DC
voltage. This will lead to erratic operation of the ISR and
may over-stress the regulator.
5. Avoid capacitance greater than 500pF at the Inhibit
control pin. Excessive capacitance at this pin will cause
the ISR to produce a pulse on the output voltage bus at
turn-on.
6. Keep the On/Off transition to less than 10µs. This
prevents erratic operation of the ISR, which could cause a
momentary high output voltage.
For technical support and more information, see inside back cover or visit www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
(Requires Login)
PT5521A
NRND
SIP MODULE
EFL
5
30
Pb-Free (RoHS)
Call TI
N / A for Pkg Type
PT5521C
NRND
SIP MODULE
EFM
5
30
Pb-Free (RoHS)
Call TI
Level-3-215C-168HRS
PT5522A
NRND
SIP MODULE
EFL
5
30
Pb-Free (RoHS)
Call TI
N / A for Pkg Type
PT5522C
NRND
SIP MODULE
EFM
5
30
Pb-Free (RoHS)
Call TI
Level-3-215C-168HRS
PT5523A
NRND
SIP MODULE
EFL
5
30
Pb-Free (RoHS)
Call TI
N / A for Pkg Type
PT5523C
NRND
SIP MODULE
EFM
5
30
Pb-Free (RoHS)
Call TI
Level-3-215C-168HRS
PT5523N
NRND
SIP MODULE
EFK
5
TBD
Call TI
Call TI
PT5524A
NRND
SIP MODULE
EFL
5
30
Pb-Free (RoHS)
Call TI
N / A for Pkg Type
PT5525A
NRND
SIP MODULE
EFL
5
30
Pb-Free (RoHS)
Call TI
N / A for Pkg Type
PT5525C
NRND
SIP MODULE
EFM
5
30
Pb-Free (RoHS)
Call TI
Level-3-215C-168HRS
PT5526A
NRND
SIP MODULE
EFL
5
30
Pb-Free (RoHS)
Call TI
N / A for Pkg Type
PT5526C
NRND
SIP MODULE
EFM
5
30
Pb-Free (RoHS)
Call TI
Level-3-215C-168HRS
OBSOLETE SIP MODULE
EFL
5
TBD
Call TI
Call TI
PT5527A
Samples
PT5527C
NRND
SIP MODULE
EFM
5
TBD
Call TI
Call TI
PT5527N
NRND
SIP MODULE
EFK
5
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
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Addendum-Page 2
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