SCLS075E − JANUARY 1991 − REVISED APRIL 1996
D EPIC (Enhanced-Performance Implanted
D
D
D
D
CMOS) 2-µ Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54LV245 . . . FK PACKAGE
(TOP VIEW)
A2
A1
DIR
VCC
OE
D
SN54LV245 . . . J OR W PACKAGE
SN74LV245 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
description
A3
A4
A5
A6
A7
These octal bus transceivers are designed for
2.7-V to 5.5-V VCC operation.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
A8
GND
B8
B7
B6
The ’LV245 are designed for asynchronous
communication between data buses. The device
transmits data from the A bus to the B bus or from
the B bus to the A bus, depending upon the logic
level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable
the device so the buses are effectively isolated.
4
The SN74LV245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV245 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV245 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$ $%$ $&'"%$ !''#$ % & (!)*%$ %#+ '! $&'" (#&%$ (#' # #'" & #,% $'!"#$ %$%' -%''%$.+
'!$ ('#$/ # $ $##%'*. $*!# #$/ & %**
(%'%"##'+
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1
SCLS075E − JANUARY 1991 − REVISED APRIL 1996
logic symbol†
OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
19
1
2
3
logic diagram (positive logic)
G3
DIR
1
3EN1[BA]
3EN2[AB]
19
18
1
2
17
4
16
5
15
6
14
7
13
8
12
9
11
B1
A1
OE
2
B2
18
B3
B1
B4
B5
B6
B7
To Seven Other Channels
B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DB, DW, J, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 70 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
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•
SCLS075E − JANUARY 1991 − REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV245
VCC
Supply voltage
UNIT
MIN
MAX
MIN
MAX
2.7
5.5
2.7
5.5
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
Low-level output current
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74LV245
2
2
3.15
3.15
0.8
0.8
1.65
0
0
V
V
1.65
VCC
VCC
UNIT
VCC
VCC
−8
−8
−16
−16
8
8
16
16
V
V
V
mA
mA
0
50
0
50
ns / V
−55
125
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VCC†
TEST CONDITIONS
IOH = −100 µA
IOH = −8 mA
MIN to MAX
IOH = −16 mA
IOL = 100 µA
4.5 V
3V
II
VI = VCC or GND
IOZ‡
VO = VCC or GND
ICC
VI = VCC or GND,
nICC
One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
Control inputs
VI = VCC or GND
Co
A or B port
VO = VCC or GND
SN74LV245
UNIT
MIN
TYP
MAX
MIN
VCC−0.2
2.4
VCC−0.2
2.4
3.6
3.6
MIN to MAX
IOL = 8 mA
IOL = 16 mA
VOL
SN54LV245
TYP
MAX
V
0.2
0.2
3V
0.4
0.4
4.5 V
0.55
0.55
3.6 V
±1
±1
5.5 V
±1
±1
3.6 V
±5
±5
5.5 V
±5
±5
3.6 V
20
20
5.5 V
20
20
3 V to 3.6 V
500
500
IO = 0
3.3 V
2.5
2.5
5V
3
3
3.3 V
7
7
5V
8
8
V
µA
A
µA
A
µA
A
µA
pF
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
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3
SCLS075E − JANUARY 1991 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LV245
FROM
(INPUT)
TO
(OUTPUT)
tpd
ten
A or B
B or A
8
11
8
14
18
ns
OE
A or B
6
14
12
21
25
ns
tdis
OE
A or B
8
16
12
20
24
ns
PARAMETER
VCC = 5 V ± 0.5 V
MIN
TYP
MAX
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
VCC = 2.7 V
MIN
MAX
UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74LV245
FROM
(INPUT)
TO
(OUTPUT)
tpd
ten
A or B
B or A
8
11
8
14
18
ns
OE
A or B
6
14
12
21
25
ns
tdis
OE
A or B
8
16
12
20
24
ns
PARAMETER
VCC = 5 V ± 0.5 V
MIN
TYP
MAX
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
VCC = 2.7 V
MIN
MAX
UNIT
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance per
transceiver
3.3 V
Outputs disabled
Outputs enabled
CL = 50 pF,
Outputs disabled
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VCC
f = 10 MHz
5V
TYP
UNIT
36
4
46
4
pF
SCLS075E − JANUARY 1991 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
S1
1 kΩ
From Output
Under Test
Vz
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
1 kΩ
WAVEFORM
CONDITION
Vm
Vi
Vz
LOAD CIRCUIT
VCC = 4.5 V
to 5.5 V
0.5 × VCC
VCC
2 × VCC
VCC = 2.7 V
to 3.6 V
1.5 V
2.7 V
6V
Vi
Vm
Timing Input
0V
tw
tsu
Vi
Input
Vm
th
Vi
Vm
Vm
Data Input
Vm
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Vi
Vm
Input
0V
VOH
Vm
Output
Vm
VOL
Output
VOH
Vm
0V
Vm
VOL
tPLZ
Output
Waveform 1
S1 at Vz
(see Note B)
tPLH
tPHL
Vm
Vm
tPZL
tPHL
tPLH
Vi
Output
Control
Vm
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Vm
tPZH
0.5 × Vz
VOL + 0.3 V
VOL
tPHZ
Vm
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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•
5
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
SN74LV245DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74LV245DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LV245DWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LV245PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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