TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 CAP-FREE NMOS 150 mA LOW DROPOUT REGULATOR WITH REVERSE CURRENT PROTECTION FEATURES 1 • Controlled Baseline – One Assembly – Test Site – One Fabrication Site • Extended Temperature Performance of –55°C to 125°C • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification • Qualification Pedigree (1) • Stable With No Output Capacitor or Any Value or Type of Capacitor • Input Voltage Range of 1.7 V to 5.5 V • Ultralow Dropout Voltage: 30 mV Typical • Excellent Load Transient Response—With or Without Optional Output Capacitor • New NMOS Topology Provides Low Reverse Leakage Current 2 (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • • • • Low Noise: 30 μVRMS Typ (10 kHz to 100 kHz) 0.5% Initial Accuracy 1% Overall Accuracy Over Line, Load, and Temperature Less Than 1 μA Maximum IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions – Fixed Outputs of 1.2 V to 5 V – Adjustable Outputs from 1.2 V to 5.5 V – Custom Outputs Available APPLICATIONS • • • • Portable/Battery-Powered Equipment Post-Regulation for Switching Supplies Noise-Sensitive Circuitry such as VCOs Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors DESCRIPTION/ORDERING INFORMATION The TPS731xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR and even allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. The TPS731xx uses an advanced BiCMOS process to yield high precision while delivering low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1 μA and ideal for portable applications. The low output noise (30 μVRMS with 0.1 μF CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 Optional Optional VIN IN DBV PACKAGE SOT23 (TOP VIEW) VOUT OUT TPS731xx EN GND NR IN 1 GND 2 EN 3 Optional 5 OUT 4 NR/FB Typical Application Circuit for Fixed-Voltage Versions This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCT INFORMATION (1) VOUT (2) PRODUCT TPS731xxMyyyzEP (1) (2) (3) For the most current specification and package information, see the Package Option Addendum located at the end of this data sheet or see the Texas Instruments website at www.ti.com. Output voltages from 1.3 V to 4 V in 100 mV increments are available through the use of innovative factory EEPROM programming. Minimum order quantities apply; contact factory for details and availability. For fixed 1.2 V operation, tie FB to OUT ORDERING INFORMATION (1) TA –55°C to 125°C (1) (2) 2 XX is nominal output voltage (for example, 25 = 2.5 V, 01 = Adjustable (3)). YYY is package designator. Z is package quantity. PACKAGE (2) SOT23 - DBV ORDERABLE PART NUMBER TOP-SIDE MARKING TPS73101MDBVREP PKAM TPS73115MDBVREP PKBM TPS731125MDBVREP PMMM TPS73118MDBVREP PKCM TPS73125MDBVREP PKDM TPS73130MDBVREP PKEM TPS73132MDBVREP PKFM TPS73133MDBVREP PKHM TPS73150MDBVREP PKIM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 ABSOLUTE MAXIMUM RATINGS over operating junction temperature range unless otherwise noted (1) VIN range –0.3 V to 6 V VEN range –0.3 V to 6 V VOUT range –0.3 V to 5.5 V Peak output current Internally limited Output short-circuit duration Indefinite See Power Dissipation Ratings Table Continuous total power dissipation Ambient temperature range, TA –55°C to 150°C Storage temperature range –65°C to 150°C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. POWER DISSIPATION RATINGS (1) BOARD PACKAGE RΘJC RΘJA DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING Low-K (2) DBV 64°C/W 255°C/W 3.9 mW/°C 450 mW 275 mW 215 mW 58 mW DBV 64°C/W 180°C/W 5.6 mW/°C 638 mW 388 mW 305 mW 83 mW High-K (1) (2) (3) (3) See Power Dissipation in the Application Information section for more information related to thermal design. The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2-ounce copper traces on top of the board. The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board. Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 3 TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS Over operating temperature range (TA = –55°C to +125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. Typical values are at TA = 25°C PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference (TPS73101) MIN TA = 25°C 1.198 Output voltage range (TPS73101) VOUT Accuracy (1) ΔVOUT%/ΔVIN TA = 25°C VIN, IOUT, and T VOUT + 0.5 V ≤ VIN ≤ 5.5 V, 10 mA ≤ IOUT ≤ 150 mA ΔVOUT%/ΔIOUT Load regulation MAX V 1.21 V 5.5 – VDO V ±0.5 –1 VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V ±0.5 % +1 0.01 1 mA ≤ IOUT ≤ 150 mA 0.002 10 mA ≤ IOUT ≤ 150 mA 0.0005 UNIT 5.5 1.2 VFB Nominal Line regulation (1) TYP 1.7 % %/V %/mA VDO Dropout voltage (2) (VIN = VOUT (nom) – 0.1 V) IOUT = 150 mA ZO(DO) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO ICL Output current limit VOUT = 0.9 × VOUT(nom) ISC Short-circuit current VOUT = 0 V 200 IREV Reverse leakage current (3) (–IIN) VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT 0.1 15 IOUT = 10 mA (IQ) 400 550 IOUT = 150 mA 550 750 VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 0.02 1 μA 0.1 0.475 μA IGND Ground pin current ISHDN Shutdown current (IGND) IFB FB pin current (TPS73101) 30 360 PSRR Power-supply rejection ratio (ripple rejection) VN Output noise voltage BW = 10 Hz to 100 kHz COUT = 10 μF, No CNR 27 × VOUT COUT = 10 μF, CNR = 0.01 μF 8.5 × VOUT tSTR Startup time VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) IEN(HI) Enable pin current (enabled) TSD Thermal shutdown temperature TA Operating ambient temperature 4 mV 500 mA Ω 0.25 150 f = 100 Hz, IOUT = 150 mA (1) (2) (3) 100 58 f = 10 kHz, IOUT = 150 mA 37 VOUT = 3 V, RL = 30Ω COUT = 1 μF, CNR = 0.01 μF mA μVRMS μs VIN 0 VEN = 5.5 V 0.02 Shutdown, Temperature increasing 160 Reset, Temperature decreasing 140 –55 μA dB 600 1.7 μA V 0.5 V 0.1 μA °C 125 °C Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater. VDO is not measured for the TPS73115 (VO(nom) = 1.5 V) and TPS731125 (VO(nom) = 1.25 V) since minimum VIN = 1.7 V. Fixed-voltage versions only; see the Applications Infomation section for more information. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 16 14 Years Estimated Life 12 10 8 6 4 2 0 100 A. 110 120 130 Continuous Tj (°C) 140 150 160 Tj = θJA × W + TA (at standard JESD 51 conditions) Figure 1. Estimated Device Life at Elevated Temperatures Electromigration Fail Mode Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 5 TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 FUNCTIONAL BLOCK DIAGRAMS IN 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp Current Limit OUT 8kΩ GND R1 R1 + R2 = 80kΩ R2 NR Figure 2. Fixed Voltage Version Table 1. Standard 1% Resistor Values for Common Output Voltages IN VO 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp OUT Current Limit GND 8kΩ 80kΩ R1 R2 1.2V Short Open 1.5V 23.2kΩ 95.3kΩ 1.8V 28.0kΩ 56.2kΩ 2.5V 39.2kΩ 36.5kΩ 2.8V 44.2kΩ 33.2kΩ 3.0V 46.4kΩ 30.9kΩ 3.3V 52.3kΩ 30.1kΩ 5.0V 78.7kΩ 24.9kΩ NOTE: VOUT = (R1 + R2)/R2 × 1.204; R1R2 ≅ 19kΩ for best accuracy. R1 FB R2 Figure 3. Adjustable Voltage Version 6 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 PIN ASSIGNMENTS DBV PACKAGE SOT23 (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 NR/FB TERMINAL FUNCTIONS TERMINAL NAME SOT23 (DBV) PIN NO. DESCRIPTION IN 1 Unregulated input supply GND 2 Ground EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under Application Information for more details. EN can be connected to IN if not used. NR 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 Output of the regulator. There are no output capacitor requirements for stability. Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 7 TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted LOAD REGULATION LINE REGULATION 0.5 0.20 Referred to IOUT = 10mA 0.4 Change in VOUT (%) 0.3 Change in VOUT (%) Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 0.2 0.1 0 −0.1 −0.2 −0.3 0.10 0 −0.05 −40_ C −0.10 −0.15 −0.4 −0.20 −0.5 0 15 30 45 60 75 90 105 120 135 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN − VOUT (V) IOUT (mA) Figure 4. Figure 5. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 50 50 TPS73125DBV +125_ C 40 30 +25_ C 20 10 40 VDO (mV) VDO (mV) +25_ C +125_C 0.05 0 30 60 90 120 30 20 10 −40_C 0 TPS73125DBV IOUT = 150mA 0 −50 150 IOUT (mA) −25 0 25 50 75 100 125 Temperature (_ C) Figure 6. Figure 7. OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 30 18 I OUT = 10mA 16 25 I OUT = 10mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 0 8 −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/_ C) Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted GROUND PIN CURRENT vs TEMPERATURE 700 600 600 500 500 IGND (µA) IGND (µA) GROUND PIN CURRENT vs OUTPUT CURRENT 700 400 300 200 400 300 VIN = 5.5V VIN = 4V VIN = 2V 200 VIN = 5.5V VIN = 4V VIN = 2V 100 100 0 0 30 60 90 120 0 −50 150 −25 0 25 50 75 100 I OUT (mA) Temperature (_ C) Figure 10. Figure 11. CURRENT LIMIT vs VOUT (FOLDBACK) GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE 400 125 1 VENABLE = 0.5V VIN = VO + 0.5V 350 ICL 300 250 IGND (µA) Current Limit (mA) IOUT = 150mA ISC 200 150 0.1 100 50 TPS73133 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0.01 −50 3.5 0 25 50 Temperature (_C) Figure 12. Figure 13. CURRENT LIMIT vs VIN 75 100 125 CURRENT LIMIT vs TEMPERATURE 500 500 450 450 400 400 Current Limit (mA) Current Limit (mA) −25 VOUT (V) 350 300 250 200 350 300 250 200 150 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 150 −50 −25 0 25 50 VIN (V) Temperature (_C) Figure 14. Figure 15. Copyright © 2006–2007, Texas Instruments Incorporated 75 100 Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 125 9 TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN – VOUT 90 40 IO = 1mA CO = Any 70 IO = 1mA CO = 1 m F IO = 1mA CO = 10mF 35 30 PSRR (dB) 60 IO = 100mA C O = 1m F 50 IO = 100mA CO = Any 40 PSRR (dB) 80 30 25 20 15 10 20 10 VIN = VOUT = 1.25V 0 10 1k 100 10k Frequency = 100kHz COUT = 10µF VOUT = 2.5V 5 IO = Any CO = 0 mF 0 100k 1M 10M 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Frequency (Hz) VIN − VOUT (V) Figure 16. Figure 17. NOISE SPECTRAL DENSITY CNR = 0 μF NOISE SPECTRAL DENSITY CNR = 0.01 μF 1 1.8 2.0 1 COUT = 0µF 0.1 COUT = 10µF eN (µV/√Hz) eN (µV/√Hz) C OUT = 1µF COUT = 1µF 0.1 COUT = 0µF COUT = 10µF I OUT = 150mA I OUT = 150mA 0.01 0.01 10 100 1k 10k 100k 10 100 1k Frequency (Hz) Frequency (Hz) Figure 18. Figure 19. RMS NOISE VOLTAGE vs COUT 10k 100k RMS NOISE VOLTAGE vs CNR 60 140 50 120 VOUT = 5.0V VOUT = 5.0V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3V 20 10 0.1 10 20 CNR = 0.01µF 10Hz < Frequency < 100kHz 0 1 10 VOUT = 3.3V 60 40 VOUT = 1.5V 0 80 VOUT = 1.5V COUT = 0µF 10Hz < Frequency < 100kHz 1p 10p 100p COUT (µF) CNR (F) Figure 20. Figure 21. Submit Documentation Feedback 1n 10n Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted TPS73133 LOAD TRANSIENT RESPONSE VIN = 3.8V TPS73133 LINE TRANSIENT RESPONSE COUT = 0µF 40mV/tick IOUT = 150mA VOUT COUT = 0µF 50mV/div COUT = 1µF 40mV/tick COUT = 10µF 40mV/tick VOUT VOUT VOUT COUT = 100µF 50mV/div IOUT 25mA/tick 10mA 4.5V 1V/div VIN 10µs/div 10µs/div Figure 23. TPS73133 TURN-ON RESPONSE TPS73133 TURN-OFF RESPONSE RL = 20Ω COUT = 10µF VOUT RL = 20Ω CO UT = 1µF = 0.5V/µs dt Figure 22. RL = 1kΩ COUT = 0µF R L = 20Ω C OUT = 1µF 1V/div RL = 1kΩ COUT = 0µF RL = 20Ω COUT = 10µF VOUT 2V 2V VEN 1V/div 1V/div 0V 0V VEN 100µs/div 100µs/div Figure 24. Figure 25. TPS73133 POWER UP / POWER DOWN IENABLE vs TEMPERATURE 10 6 5 4 VIN VOUT IENABLE (nA) 3 Volts dVIN 5.5V 150mA 1V/div VOUT 2 1 1 0.1 0 −1 −2 50ms/div 0.01 −50 −25 0 25 50 75 100 125 Temperature (_C) Figure 26. Copyright © 2006–2007, Texas Instruments Incorporated Figure 27. Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 11 TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted TPS73101 IFB vs TEMPERATURE 60 160 55 140 50 120 45 100 IFB (nA) VN (rms) TPS73101 RMS NOISE VOLTAGE vs CADJ 40 35 30 25 80 60 VOUT = 2.5V COUT = 0µF R1 = 39.2kΩ 10Hz < Frequency < 100kHz 20 10p 100p 40 20 1n 10n 0 −50 −25 0 25 50 75 100 CFB (F) Temperature (_C) Figure 28. Figure 29. TPS73101 LOAD TRANSIENT, ADJUSTABLE VERSION TPS73101 LINE TRANSIENT, ADJUSTABLE VERSION CFB = 10nF R1 = 39.2kΩ COUT = 0µF 50mV/div VOUT COUT = 0µF COUT = 10µF 50mV/div VOUT = 2.5V CFB = 10nF 100mV/div COUT = 10µF 100mV/div 125 VOUT VOUT VOUT 4.5V 150mA 3.5V VIN 10mA 25µs/div Figure 30. 12 Submit Documentation Feedback IOUT 5µs/div Figure 31. Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION The TPS731xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS731xx ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 32 shows the basic circuit connections for the fixed voltage models. Figure 33 gives the connections for the adjustable output version (TPS73101). Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN VOUT OUT TPS731xx EN GND NR Figure 32. Typical Application Circuit for Fixed-Voltage Versions VIN Optional output capacitor. May improve load transient noise, or PSRR. IN EN VOUT OUT TPS73101 GND R1 CFB FB R2 VOUT = (R1 + R2) R2 x 1.204 Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1 μF to 1 μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS731xx does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where VIN – VOUT < 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50 nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. OUTPUT NOISE Optional bypass capacitor to reduce output noise. Optional input capacitor. May improve source impedance, noise, or PSRR. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Optional capacitor reduces output noise and improves transient response. Figure 33. Typical Application Circuit for Adjustable-Voltage Versions R1 and R2 can be calculated for any output voltage using the formula shown in Figure 33. Sample resistor values for common output voltages are shown in Figure 3. For the best accuracy, make the parallel combination of R1 and R2 approximately 19 kΩ. A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS731xx and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: VOUT (R1 ) R2) V N + 32mVRMS + 32mVRMS R2 VREF (1) Since the value of VREF is 1.2 V, this relationship reduces to: mV RMS V N(mVRMS) + 27 V OUT(V) V (2) ǒ Ǔ for the case of no CNR. An internal 27 kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10 Hz to 100 kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: ǒmVV Ǔ V N(mVRMS) + 8.5 RMS V OUT(V) (3) for CNR = 10nF. Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 13 TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP www.ti.com SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. The TPS73101 adjustable version does not have the noise-reduction pin available. However, connecting a feedback capacitor, CFB, from the output to the FB pin reduces output noise and improves load transient performance. The TPS731xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250 μV of switching noise at ~4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. DROPOUT VOLTAGE The TPS731xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. For large step changes in load current, the TPS731xx requires a larger voltage drop across it to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN – VOUT above this line ensure normal transient response. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions (full-scale instantaneous load change with (VIN – VOUT) close to dc dropout levels), the TPS731xx can take a couple of hundred microseconds to return to the specified regulation accuracy. INTERNAL CURRENT LIMIT TRANSIENT RESPONSE The TPS731xx internal current limit helps protect the regulator during fault conditions. Foldback current helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5 V. See Figure 12 in the Typical Characteristics section for a graph of IOUT vs VOUT. The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1 μF) from the output pin to ground reduces undershoot magnitude but increases duration. In the adjustable version, the addition of a capacitor, CFB, from the output to the adjust pin also improves the transient response. BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE SHUTDOWN The Enable pin is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5 V (max) turns the regulator off and drops the ground pin current to approximately 10 nA. When shutdown capability is not required, the Enable pin can be connected to VIN. When a pullup resistor is used and operation down to 1.8 V is required, use pullup resistor values below 50 kΩ. The TPS731xx does not have active pulldown when the output is overvoltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed voltage version) VOUT dVńdt + C OUT 80kW ø R LOAD 14 Submit Documentation Feedback (4) Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP www.ti.com (Adjustable voltage version) V OUT dVńdt + C OUT 80kW ø (R 1 ) R 2) ø R LOAD TPS73101-EP,, TPS73115-EP TPS731125-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP TPS73132-EP, TPS73133-EP, TPS73150-EP SGLS347A – JUNE 2006 – REVISED SEPTEMBER 2007 (5) REVERSE CURRENT The NMOS pass element of the TPS731xx provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the enable pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. After the enable pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There is additional current flowing into the OUT pin due to the 80-kΩ internal resistor divider to ground (see Figure 2 and Figure 3). For the TPS73101, reverse current may flow when VFB is more than 1 V above VIN. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least Copyright © 2006–2007, Texas Instruments Incorporated 35°C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS731xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS731xx into thermal shutdown will degrade device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low-K and high-K boards are shown in the Power Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): PD = (VIN – VOUT) × IOUT Power dissipation can be minimized by using the lowest possible input voltage necessary to ensure the required output voltage. Package Mounting Solder pad footprint recommendations for the TPS731xx are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (AB-132), available from the Texas Instruments web site at www.ti.com. Submit Documentation Feedback Product Folder Link(s): TPS73101-EP TPS73115-EP TPS731125-EP TPS73118-EP TPS73125-EP TPS73130-EP TPS73132-EP TPS73133-EP TPS73150-EP 15 PACKAGE OPTION ADDENDUM www.ti.com 18-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS73101MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-01XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-02XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-03XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-04XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-05XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-06XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-07XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-08XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06652-09XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Mar-2009 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TPS73101-EP, TPS731125-EP, TPS73115-EP, TPS73118-EP, TPS73125-EP, TPS73132-EP, TPS73133-EP, TPS73150-EP : • Catalog: TPS73101, TPS731125, TPS73115, TPS73118, TPS73125, TPS73130, TPS73132, TPS73133, TPS73150 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 TPS73130-EP, PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS73101MDBVREP SOT-23 DBV 5 3000 179.0 8.4 TPS731125MDBVREP SOT-23 DBV 5 3000 179.0 TPS73115MDBVREP SOT-23 DBV 5 3000 179.0 TPS73118MDBVREP SOT-23 DBV 5 3000 TPS73125MDBVREP SOT-23 DBV 5 TPS73130MDBVREP SOT-23 DBV TPS73132MDBVREP SOT-23 DBV TPS73133MDBVREP SOT-23 TPS73150MDBVREP SOT-23 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73101MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS731125MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73115MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73118MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73125MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73130MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73132MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73133MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73150MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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