SDLS032G − DECEMBER 1983 − REVISED MAY 2004
D Convert TTL Voltage Levels to MOS Levels
D High Sink-Current Capability
D Input Clamping Diodes Simplify System
D
D
SN5407, SN5417 . . . J OR W PACKAGE
SN7407, SN7417 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
Design
Open-Collector Driver for Indicator Lamps
and Relays
Inputs Fully Compatible With Most TTL
Circuits
description/ordering information
These TTL hex buffers/drivers feature
high-voltage open-collector outputs for interfacing
with high-level circuits (such as MOS) or for
driving high-current loads (such as lamps or
relays) and also are characterized for use as
buffers for driving TTL inputs. The SN5407 and
SN7407 have minimum breakdown voltages of
30 V, and the SN5417 and SN7417 have
minimum breakdown voltages of 15 V. The
maximum sink current is 30 mA for the SN5407
and SN5417 and 40 mA for the SN7407 and
SN7417.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
1Y
1A
NC
VCC
6A
SN5407 . . . FK PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
2A
NC
2Y
NC
3A
These devices perform the Boolean function
Y = A in positive logic.
NC − No internal connection
ORDERING INFORMATION
TA
ORDERABLE
PART NUMBER
PACKAGE†
SOIC − D
Tube
SN7407D
Tape and reel
SN7407DR
Tube
SN7417D
Tape and reel
SN7417DR
0°C to 70°C
PDIP − N
−55°C to 125°C
Tube
TOP-SIDE
MARKING
7407
7417
SN7407N
SN7407N
SN7417N
SN7417N
SN7407NSR
SN7407
SN7417NSR
SN7417
SNJ5407J
SNJ5407J
SNJ5417J
SNJ5417J
SOP − NS
Tape and reel
CDIP − J
Tube
CFP − W
Tube
SNJ5407W
SNJ5407W
LCCC − FK
Tube
SNJ5407FK
SNJ5407FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
*"!-('%& '!#*,$% %! 4565 $,, *$"$#)%)"& $") %)&%)(,)&& !%/)"1&) !%)-. $,, !%/)" *"!-('%& *"!-('%!
*"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SDLS032G − DECEMBER 1983 − REVISED MAY 2004
description/ordering information (continued)
These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize
transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average
propagation delay time is 14 ns.
logic diagram, each buffer/driver (positive logic)
A
Y
schematic
VCC
6 kΩ
3.4 kΩ
1.6 kΩ
Input A
Output Y
100 Ω
1 kΩ
GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage, VO (see Notes 1 and 2): SN5407, SN7407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN5417, SN7417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SDLS032G − DECEMBER 1983 − REVISED MAY 2004
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
VIL
High-level input voltage
MIN
NOM
MAX
SN5407, SN5417
4.5
5
5.5
SN7407, SN7417
4.75
5
5.25
2
0.8
High-level output voltage
IOL
Low-level output current
TA
Operating free-air temperature
V
V
Low-level input voltage
VOH
UNIT
SN5407, SN7407
30
SN5417, SN7417
15
SN5407, SN5417
30
SN7407, SN7417
40
SN5407, SN5417
−55
125
SN7407, SN7417
0
70
V
V
mA
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
VIK
VCC = MIN,
MIN
TYP‡
II = −12 mA
IOH
VCC = MIN,
VIH = 2 V
VOL
VCC = MIN,
VIL = 0.8 V
II
IIH
VCC = MAX,
VCC = MAX,
VI = 5.5 V
VIH = 2.4 V
IIL
ICCH
VCC = MAX,
VCC = MAX
VIL = 0.4 V
MAX
UNIT
−1.5
V
VOH = 30 V (SN5407, SN7407)
VOH = 15 V (SN5417, SN7417)
0.25
IOL = 16 mA
IOL = 30 mA (SN5407, SN5417)
0.4
IOL = 40 mA (SN7407, SN7417)
0.7
0.25
0.7
mA
V
1
mA
40
µA
−1.6
mA
29
41
mA
ICCL
VCC = MAX
21
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
30
mA
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
RL = 110 Ω,
CL = 15 pF
tPLH
tPHL
A
Y
RL = 150 Ω,
CL = 50 pF
POST OFFICE BOX 655303
TEST CONDITIONS
MIN
TYP
MAX
6
10
20
30
UNIT
ns
15
• DALLAS, TEXAS 75265
26
ns
3
SDLS032G − DECEMBER 1983 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
RL
From Output
Under Test
Test Point
CL
(see Note A)
LOAD CIRCUIT
3V
1.5 V
Input
1.5 V
0V
tPLH
High-Level
Pulse
1.5 V
1.5 V
1.5 V
1.5 V
tPLH
VOH
Out-of-Phase
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
CL includes probe and jig capacitance.
In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns.
The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
1.5 V
VOL
tPHL
VOLTAGE WAVEFORMS
PULSE WIDTHS
NOTES: A.
B.
C.
D.
VOH
In-Phase
Output
1.5 V
tw
Low-Level
Pulse
tPHL
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
JM38510/00803BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00803BCA
JM38510/00803BDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00803BDA
M38510/00803BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00803BCA
M38510/00803BDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00803BDA
SN5407J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN5407J
SN5417J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN5417J
SN7407D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7407
SN7407DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7407
SN7407DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7407
SN7407DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7407
SN7407DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7407
SN7407DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7407
TBD
Call TI
Call TI
0 to 70
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN7407J
OBSOLETE
CDIP
J
14
SN7407N
ACTIVE
PDIP
N
14
SN7407N
SN7407N3
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
0 to 70
SN7407NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN7407N
SN7407NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SN7407
SN7407NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SN7407
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN7407NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SN7407
SN7417D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7417
SN7417DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7417
SN7417DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7417
SN7417DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7417
SN7417DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7417
SN7417DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7417
SN7417N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN7417N
SN7417N3
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
0 to 70
SN7417NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SNJ5407FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
SNJ5407FK
SNJ5407J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ5407J
SNJ5407W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ5407W
SNJ5417J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ5417J
SN7417N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5407, SN5417, SN7407, SN7417 :
• Catalog: SN7407, SN7417
• Military: SN5407, SN5417
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN7407DR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
D
14
2500
330.0
16.4
6.55
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.05
2.1
8.0
16.0
Q1
SN7407DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN7407NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN7417DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN7407DR
SOIC
D
14
2500
385.0
388.0
194.0
SN7407DR
SOIC
D
14
2500
333.2
345.9
28.6
SN7407NSR
SO
NS
14
2000
367.0
367.0
38.0
SN7417DR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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