CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 FEATURES • • • • • • • • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications Spread Spectrum Clock Compatible Operating Frequency: 10 MHz to 400 MHz Low Current Consumption: <135 mA Low Jitter (Cycle-Cycle): ±30 ps Low Output Skew: 35 ps Low Period Jitter: ±20 ps Low Dynamic Phase Offset: ±15 ps • • Low Static Phase Offset: ±50 ps Distributes One Differential Clock Input to Ten Differential Outputs 52-Ball μBGA (MicroStar™ Junior BGA, 0,65-mm pitch) and 40-Pin MLF External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300 Fail-Safe Inputs • • • • DESCRIPTION The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from —40°C to 85°C. ORDERING INFORMATION TA -40°C to 85°C (1) 52-BALL BGA (1) 40-Pin MLF CDCU877ZQL CDCU877RHA CDCU877AZQL CDCU877ARHA CDCU877GQL CDCU877RTB CDCU877AGQL CDCU877ARTB For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2007, Texas Instruments Incorporated CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 3 Y6 Y5 Y5 Y0 2 GND GND Y0 Y1 MicroStar Junior (ZQL) Package (TOP VIEW) 4 5 6 A Y1 GND B Y6 GND C NB NB Y7 GND Y2 GND Y2 VDDQ VDDQ CK D Y7 OS VDDQ E NB NB F NB NB FBIN VDDQ VDDQ FBIN OE CK VDDQ AGND VDDQ VDDQ AVDD GND Y3 GND G FBOUT VDDQ VDDQ NB H NB FBOUT GND J Y8 GND A. NC = No Connection B. NB = No Ball Y8 Y9 GND Y9 GND Y4 Y4 Y3 K Y1 Y1 Y0 Y0 VDDQ Y5 Y5 Y6 Y6 VDDQ RHA/RTB Package (MLF PAckage (TOP VIEW) 40 39 38 37 36 35 34 33 32 31 VDDQ Y2 Y2 CK CK VDDQ AGND AVDD VDDQ GND 1 30 2 29 28 3 27 4 5 GND 26 6 25 7 24 8 23 22 9 21 10 VDDQ Y9 Y9 Y8 Y8 VDDQ Y3 Y3 Y4 Y4 11 12 13 14 15 16 17 18 19 20 40-pin HP-VFQFP-N (6,0 x 6,0 mm Body Size, 0,5 mm Pitch, M0#220, Variation VJJD-2, E2 = D2 = 2,9 mm ± 0,15 mm) Package Pinouts 2 Submit Documentation Feedback Y7 Y7 VDDQ FBIN FBIN FBOUT FBOUT VDDQ OE OS CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME GQL/ZQL RHA/RTB AGND G1 7 AVDD H1 8 CK E1 4 I Clock input with a (10 kΩ to 100 kΩ) pulldown resistor CK F1 5 I Complementary clock input with a (10 kΩ to 100 kΩ) pulldown resistor FBIN E6 27 I Feedback clock input FBIN F6 26 I Complementary feedback clock input FBOUT H6 24 O Feedback clock output FBOUT G6 25 O Complementary feedback clock output OE F5 22 I Output enable (asynchronous) I Output select (tied to GND or VDD) OS Analog ground Analog power D5 21 GND B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, J5 10 VDDQ D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 1, 6, 9, 15, 20, 23, 28, 31, 36 Y[0:9] A2, A1, D1, J1, K3, A5, A6, D6, J6, K4 3, 11, 14, 16, 19, 29, 33, 34, 38, 39 O Clock outputs Y[0:9] A3, B1, C1, K1, K2, A4, B6, C6, K6, K5 2, 12, 13, 18, 17, 30, 32, 35, 37, 40 O Complementary clock outputs Ground Logic and output power FUNCTION TABLE INPUTS AVDD OE OS GND H GND H GND OUTPUTS CK CK Y Y FBOUT FBOUT PLL X L X H H L L H H L H Bypassed/Off L H L L H L H Bypassed/Off LZ LZ L H Bypassed/Off GND L L H L LZ Y7 Active LZ Y7 Active H L Bypassed/Off 1.8 V Nominal L H L H LZ LZ L H On H L LZ Y7 Active LZ Y7 Active H L On 1.8 V Nominal L L 1.8 V Nominal H X L H L H L H On 1.8 V Nominal H X H L H L H L On 1.8 V Nominal X X L L LZ LZ LZ LZ Off X X X H H Submit Documentation Feedback Reserved 3 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D – JUNE 2005 – REVISED JULY 2007 Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC) 4 Submit Documentation Feedback www.ti.com CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range VDDQ or AVDD VI Input voltage range (2) (3) (2) (3) MIN MAX –0.5 2.5 UNIT V –0.5 VDDQ + 0.5 V –0.5 VDDQ + 0.5 VO Output voltage range IIK Input clamp current VI < 0 or VI > VDDQ ±50 mA IOK Output clamp current VO < 0 or VO > VDDQ ±50 mA IO Continuous output current VO = 0 to VDDQ Continuous current through each VDDQ or GND Tstg (1) (2) (3) Storage temperature range –65 V ±50 mA ±100 mA 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum. Recommended Operating Conditions VCC Output supply voltage, VDDQ Supply Voltage, AVDD MIN NOM MAX 1.7 1.8 1.9 (1) VDDQ UNIT V V VIL Low-level input voltage (2) OE, OS VIH High-level input voltage (2) CK, CK IOH High-level output current (see Figure 2) -9 mA IOL Low-level output current (see Figure 2) 9 mA VIX Input differential-pair cross voltage VI Input voltage level (2) VID Input differential voltage (see Figure 9 ) TA Operating free-air temperature (1) (2) 0.35 x VDDQ 0.65 x VDDQ V V (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V -0.3 VDDQ + 0.3 V DC 0.3 VDDQ + 0.4 V AC 0.6 VDDQ + 0.4 V -40 85 °C The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are specified. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK, VIH and VIL limits define the dc low and high levels for the logic detect state. Submit Documentation Feedback 5 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input VOH High-level output voltage VOL Low-level output voltage IO(DL) Low-level output current, dissabled VOD Differential output voltage (1) II = 18 mA (1) (2) UNIT -1.2 V VDDQ – 0.2 V 1.1 0.1 IOL = 9 mA 1.7 VO(DL) = 100 mV, OE = L 1.7 100 1.7 0.5 μA V ±250 OE, OS, FBIN, FBIN 1.9 ±10 CK and CK = L 1.9 500 CK and CK = 270 MHz. All outputs are open (not connected to a PCB) 1.9 135 All outputs are loaded with 2 pF and 120-Ω termination resistor 1.9 CK, CK FBIN, FBIN CK, CK FBIN, FBIN VI = VDD or GND VI = VDD or GND V 0.6 1.9 Supply current, dynamic (IDDQ + IADD) (see Note (2) for CPD calculation) Change in input current MAX CK, CK Supply current, static (IDDQ + IADD) CI(Δ) 1.7 IOL = 100 μA IDD(LD) Input capacitance 1.7 to 1.9 IOH = –9 mA Input current CI MIN TYP (1) 1.7 IOH = –100 μA II IDD AVDD , VDDQ μA μA mA 235 1.8 2 3 1.8 2 3 1.8 0.25 1.8 0.25 pF VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. Total IDD = IDDQ + IADD = fCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER fCK Duty cycle, input clock tL Stabiliztion time (3) (4) 6 Clock frequency (application) (1) (3) tDC (1) (2) TEST CONDITIONS Clock frequency (operating) (1) (2) AVDD, VDD = 1.8 V ±0.1 V (4) MIN MAX UNIT 10 400 MHz 160 340 MHz 40% 60% 12 μs The PLL must be able to handle spread spectrum induced skew. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). Application clock frequency indicates a range over which the PLL must meet all timing parameters. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Submit Documentation Feedback CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see PARAMETER TEST CONDITIONS (1) ) AVDD, VDD = 1.8 V ± 0.1 V MIN TYP MAX UNIT ten Enable time, OE to any Y/Y See Figure 11 8 ns tdis Disable time, OE to any Y/Y See Figure 11 8 ns Cycle-to-cycle period jitter (2) 160 MHz to 190 MHz, see Figure 4 Cycle-to-cycle period jitter (2) 160 MHz to 340 MHz, see Figure 4 t(ω) Static phase offset time (3) t(ω)dyn Dynamic phase offset time tsk(o) Output clock skew See Figure 6 tjit(cc+) tjit(cc-) tjit(cc+) tjit(cc-) tjit(per) VOX 40 0 -40 0 30 0 -30 See Figure 5 -50 50 ps See Figure 10 -15 15 ps 35 ps 160 MHz to 190 MHz, see Figure 7 -30 30 190 MHz to 340 MHz, see Figure 7 -20 20 160 MHz to 190 MHz, see Figure 8 -115 115 190 MHz to 250 MHz, see Figure 8 -70 70 250 MHz to 300 MHz, see Figure 8 -40 40 300 MHz to 340 MHz, see Figure 8 -60 60 Slew rate, OE See Figure 3 and Figure 9 0.5 Input clock slew rate See Figure 3 and Figure 9 1 2.5 4 Output clock slew rate (5) (6) (no load) See Figure 3 and Figure 9 1.5 2.5 3 Period jitter (4) (2) tjit(hper) Half-period jitter (4) (2) SR 0 Output differential-pair cross voltage CDCU877, See Figure 2 (VDDQ/2) 0.1 (VDDQ/2) + 0.1 CDCU877A (8), See Figure 2 (0 - 85°C) (VDDQ/2) 0.1 (VDDQ/2) + 0.1 (7) SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (1) (2) (3) (4) (5) (6) (7) (8) 30 33 0% -0.5% 2 ps ps ps ps V/ns V kHz MHz There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. This parameter is specifieded by design and characterization. Phase static offset time does not include jitter. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. The output slew rate is determined from the IBIS model with a 120-Ω load only. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. Output differential-pair cross voltage specified at the DRAM clock input or the test load. VOX of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application. Submit Documentation Feedback 7 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION VDD CU877 SCOPE GND C = 10 pF Z = 60 W L = 2.97” C = 1 pF Z = 120 W R = 1 MW VTT Z = 60 W L = 2.97” C = 1 pF R = 1 MW C = 10 pF VTT GND Note: VTT = GND Figure 2. Output Load Test Circuit 1 VDD/2 CU877 SCOPE −VDD/2 C = 10 pF Z = 60 W Z = 50 W L = 2.97” R = 10 W Z = 60 W R = 50 W VTT Z = 50 W L = 2.97” R = 10 W R = 50 W C = 10 pF −VDD/2 VTT Note: VTT = GND −VDD/2 Figure 3. Output Load Test Circuit 2 Yx, FBOUT Yx, FBOUT tcycle n tcycle n+1 tjit(cc) = tcycle n − tcycle n+1 Figure 4. Cycle-To-Cycle Period Jitter 8 Submit Documentation Feedback CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) tjn tjn+1 Figure 5. Static Phase Offset n=N å1 tj = tjn N (N is the large number of samples) (N > 1000 samples) (1) Figure 6. Output Skew Figure 7. Period Jitter t jit(per) = tcycle n - 1 fO (fO average input frequency measured at CK/CK Submit Documentation Feedback (2) 9 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 8. Half-Period Jitter t jit(hper) = thalf period n - 1 2 x fO n = any half cycle (fO average input frequency measured at CK/CK (3) 80% 80% VID, VOD Clock Inputs and Outputs, OE 20% 20% tr(i), tr(o) tf(i), tf(o) Figure 9. Input and Output Slew Rates slrr(i/o) = V80% - V20% tr(i/o) slrf(i/o) = V80% - V20% t f(i/o) (4) tj tj tjdyn tjdyn tjdyn Figure 10. Dynamic Phase Offset 10 Submit Documentation Feedback tjdyn CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 11. Time Delay Between OE and Clock Output (Y, Y) RECOMMENDED AVDD FILTERING Bead 0603 CARD VIA AV DD V DDQ 1W 4.7 mF 1206 0.1 mF 0603 2200 pF 0603 PLL GND AGND CARD VIA A. Place the 2200-pF capacitor close to the PLL. B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz). Figure 12. Recommended AVDD Filtering Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 5-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDCU877AGQLT NRND BGA MICROSTAR JUNIOR GQL 52 250 TBD SNPB Level-2-235C-1 YEAR -40 to 85 CDCU877A CDCU877ARHAR NRND VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHARG4 NRND VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAT NRND VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHATG4 NRND VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARTBR OBSOLETE VQFN RTB 40 TBD Call TI Call TI -40 to 85 CDCU877A CDCU877AZQLR NRND BGA MICROSTAR JUNIOR ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 CDCU877A CDCU877AZQLT NRND BGA MICROSTAR JUNIOR ZQL 52 250 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 CDCU877A CDCU877GQLR NRND BGA MICROSTAR JUNIOR GQL 52 1000 TBD SNPB Level-2-235C-1 YEAR -40 to 85 CDCU877 CDCU877GQLT NRND BGA MICROSTAR JUNIOR GQL 52 250 TBD SNPB Level-2-235C-1 YEAR -40 to 85 CDCU877 CDCU877RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHARG4 ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHATG4 ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RTBR OBSOLETE VQFN RHA 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RTBT OBSOLETE VQFN RTB 40 TBD Call TI Call TI -40 to 85 CDCU877 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 5-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDCU877ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 CDCU877 CDCU877ZQLT ACTIVE BGA MICROSTAR JUNIOR ZQL 52 250 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 CDCU877 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCU877AGQLT CDCU877ARHAR CDCU877ARHAT Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant GQL 52 250 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 CDCU877AZQLR BGA MI CROSTA R JUNI OR ZQL 52 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CDCU877AZQLT BGA MI CROSTA R JUNI OR ZQL 52 250 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CDCU877GQLR BGA MI CROSTA R JUNI OR GQL 52 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CDCU877GQLT BGA MI CROSTA R JUNI OR GQL 52 250 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CDCU877RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 CDCU877RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 CDCU877ZQLR BGA MI CROSTA R JUNI OR ZQL 52 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CDCU877ZQLT BGA MI CROSTA R JUNI OR ZQL 52 250 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCU877AGQLT BGA MICROSTAR JUNIOR GQL 52 250 336.6 336.6 28.6 CDCU877ARHAR VQFN RHA 40 2500 367.0 367.0 38.0 CDCU877ARHAT VQFN RHA 40 250 210.0 185.0 35.0 CDCU877AZQLR BGA MICROSTAR JUNIOR ZQL 52 1000 336.6 336.6 28.6 CDCU877AZQLT BGA MICROSTAR JUNIOR ZQL 52 250 336.6 336.6 28.6 CDCU877GQLR BGA MICROSTAR JUNIOR GQL 52 1000 336.6 336.6 28.6 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCU877GQLT BGA MICROSTAR JUNIOR GQL 52 250 336.6 336.6 28.6 CDCU877RHAR VQFN RHA 40 2500 367.0 367.0 38.0 CDCU877RHAT VQFN RHA 40 250 210.0 185.0 35.0 CDCU877ZQLR BGA MICROSTAR JUNIOR ZQL 52 1000 336.6 336.6 28.6 CDCU877ZQLT BGA MICROSTAR JUNIOR ZQL 52 250 336.6 336.6 28.6 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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