UC1707, UC2707, UC3707 www.ti.com ............................................................................................................................................. SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 DUAL CHANNEL POWER DRIVER • • • • • • FEATURES 1 • • • • • • Two Independent Drivers 1.5 A Totem Pole Outputs Inverting and Non-Inverting Inputs 40 ns Rise and Fall Into 1000 pF High-Speed, Power MOSFET Compatible Low Cross-Conduction Current Spike Analog Shutdown With Optional Latch Low Quiescent Current 5 V to 40 V Operation Thermal Shutdown Protection 16-Pin Dual-In-Line Package 20-Pin PLCC and CLCC Package DESCRIPTION The UC1707 family of power drivers is made with a high-speed Schottky process to interface between low-level control functions and high-power switching devices–particularly power MOSFETs. These devices contain two independent channels, each of which can be activated by either a high or low input logic level signal. Each output can source or sink up to 1.5 A as long as power dissipation limits are not exceeded. Although each output can be activated independently with its own inputs, it can be forced low in common through the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The Shutdown command from either source can either be latching or not, depending on the status of the Latch Disable pin. Supply voltage for both VIN and VC can independently range from 5 V to 40 V. These devices are available in two-watt plastic "bat-wing" DIP for operation over a 0°C to 70°C temperature range and, with reduced power, in a hermetically sealed cerdip for –55°C to +125°C operation. Also available in surface mount DW, Q, L packages. TRUTH TABLE (Each Channel) (1) (1) INV. N.I. OUT H H L L H H H L L L L L OUT = INV and N.I. OUT = INV or N.I. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2008, Texas Instruments Incorporated UC1707, UC2707, UC3707 SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 ............................................................................................................................................. www.ti.com BLOCK DIAGRAM CONNECTION DIAGRAMS 2 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 UC1707, UC2707, UC3707 www.ti.com ............................................................................................................................................. SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Supply voltage N/J package 40 V VC Collector supply voltage N/J package 40 V Output current (each output, source or sink) steady-state N/J package ±500 N package ±1.5 J package ±1.0 N package 20 J package 15 Digital inputs (1) N/J-package 5.5 Analog stop inputs N/J package VIN Peak transient Capacitive discharge energy Power dissipation at TA = 25°C Power dissipation at T (leads/case) = 25°C (1) N package 2 J package 1 N package 5 J package 2 A mJ V W W Operating temperature range –55 +125 °C Storage temperature range –65 +150 °C 300 °C Lead temperature (soldering, 10 seconds) (1) mA All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the specified terminal. Digital drive can exceed 5.5 V if input current is limited to 10 mA. Consult packaging section of databook for thermal limitations and considerations of package. ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1707, –25°C to +85°C for the UC2707, and 0°C to +70°C for the UC3707; VIN = VC = 20 V. TA = TJ. PARAMETER TEST CONDITIONS VIN Supply current VIN = 40 V VC Supply current VC = 40 V, outputs low VC Leakage current VIN = 0, VC - 30 V, no load MIN TYP MAX 12 15 mA 5.2 7.5 mA 0.05 0.1 mA 0.8 V –0.06 –1.0 mA 0.05 0.1 mA Digital input low level Digital input high level 2.2 Input current VI = 0 Input leakage VI = 5 V VC – VO Output high sat. VO Output low sat. V IO = –50 mA 2.0 IO = –500 mA 2.5 IO = –50 mA 0.4 IO = –500 mA 2.5 Analog threshold VCM = 0 to 15 V Input bias current VCM = 0 100 Thermal shutdown UNIT V V 130 160 mV –10 –20 µA 155 °C Shutdown threshold Pin 7 input 0.4 1.0 2.2 V Latch disable threshold Pin 3 input 0.8 1.2 2.2 V Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 Submit Documentation Feedback 3 UC1707, UC2707, UC3707 SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL SWITCHING CHARACTERISTICS VIN = VC = 20 V, TA = 25°C. Delays measured to 10% output change. PARAMETER TEST CONDITIONS OUTPUT CL = From Inv. Input to Output UNIT open 1.0 2.2 nF Rise time delay 40 50 60 ns 10% to 90% rise 25 40 50 ns Fall time delay 30 40 50 ns 90% to 10% fall 25 40 50 ns Rise time delay 30 40 50 ns 10% to 90% rise 25 40 50 ns Fall time delay 45 55 65 ns 90% to 10% fall 25 40 50 ns VC cross-conduction current spike duration Output rise 25 ns 0 ns Stop non-Inv. = 0 V 180 ns Stop Inv. = 0 to 0.5 V 180 ns 50 ns From N.I. Input to Output Output fall Analog shutdown delay Digital shutdown delay 4 Submit Documentation Feedback 2 V input on Pin 7 Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 UC1707, UC2707, UC3707 www.ti.com ............................................................................................................................................. SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 SIMPLIFIED INTERNAL CIRCUITRY Figure 1. Typical Digital Input Gate Figure 2. Typical Digital Input Gate Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 Figure 3. Latch Disable Submit Documentation Feedback 5 UC1707, UC2707, UC3707 SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 ............................................................................................................................................. www.ti.com SIMPLIFIED INTERNAL CIRCUITRY (continued) Figure 4. Use of the Shutdown Pin SHUTDOWN CIRCUIT DESCRIPTION The function of the circuitry is to be able to provide a shutdown of the device. This is defined as functionality that will drive both outputs to the low state. There are three different inputs that govern this shutdown capability. • Analog Stop Pins — The differential inputs to this comparator provide a way to execute a shutdown. • Latch Disable Pin — Assuming that the Shutdown pin is left open, a high on this pin disables the latching functionality of the Analog Stop shutdown. A low on this pin enables the latching functionality of the Analog Stop shutdown. If a shutdown occurs through the Analog Stop circuit while Latch Disable is high, then the outputs will go low, but will return to normal operation as soon as the Analog Stop circuit allows it. If a shutdown occurs through the Analog Stop circuit while Latch Disable is low, then the outputs will go low and remain low even if the Analog Stop circuit no longer drives the shutdown. The outputs will remain "latched" low (in shutdown) until the Latch Disable goes high and the Analog Stop circuit allows it to return from shutdown or the VIN voltage is cycled to 0V and then returned above 5V. • Shutdown Pin — This pin serves two purposes. 1. It can be used as an output of the Analog Stop circuit. 2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin can override both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels into the Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not function as it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, the outputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs will operate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins. In order to use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in series with the Shutdown signal or to use an open collector pull-up so that the Shutdown pin is not pulled low. This configuration will allow the Latch Disable function to work with the Shutdown pin. 6 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 UC1707, UC2707, UC3707 www.ti.com ............................................................................................................................................. SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 SIMPLIFIED INTERNAL CIRCUITRY (continued) UG1707 SHUTDOWN TRUTH TABLE (1) ANALOG STOP LOGIC SHUTDOWN LATCH DISABLE PREVIOUS STATE OF OUTPUT OUTPUT X 0 X X Follows Input Logic X 1 X X Low (Shutdown) 1 Open X X 0 Open 0 Shutdown 0 Open 0 Normal Follows Input Logic 0 Open 1 X Follows Input Logic Low (Shutdown) (1) Latched Shutdown If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or the Shutdown pin is open, the outputs will remain in Shutdown. Figure 5. Transformer Coupled Push-Pull MOSFET Drive Circuit Figure 6. Current Limiting Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 Submit Documentation Feedback 7 UC1707, UC2707, UC3707 SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 ............................................................................................................................................. www.ti.com Figure 7. Over-Voltage Protection Figure 8. Power MOSFET Drive Circuit Figure 9. Charge Pump Circuits 8 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 UC1707, UC2707, UC3707 www.ti.com ............................................................................................................................................. SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 Figure 10. Power Bipolar Drive Circuit Figure 11. Transformer Coupled MOSFET Drive Circuit Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 Submit Documentation Feedback 9 UC1707, UC2707, UC3707 SLUS177B – MARCH 1999 – REVISED SEPTEMBER 2008 ............................................................................................................................................. www.ti.com Figure 12. Power MOSFET Drive Circuit Using Negative Bias Voltage and Level Shifting to Ground Reference PWM 10 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UC1707 UC2707 UC3707 PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) 5962-87619012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596287619012A UC1707L/ 81032 5962-8761901EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8761901EA UC1707J/80900 5962-8761901V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59628761901V2A UC1707L QMLV 5962-8761901VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8761901VE A UC1707JQMLV 5962-8761903VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8761903VE A UC1707J-SP 5962-8761903VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8761903VF A UC1707W-SP UC1707J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1707J UC1707J/80313 OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 UC1707J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1707J/883B UC1707L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1707L UC1707L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1707L/ 883B UC2707DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2707DW UC2707DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2707DW UC2707DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2707DW UC2707DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2707DW Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) UC2707N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2707N UC2707NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2707N UC2707Q ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 UC2707Q UC2707QG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 UC2707Q UC3707DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3707DW UC3707DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3707DW UC3707DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3707DW UC3707DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3707DW UC3707J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 0 to 70 UC3707J UC3707N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3707N UC3707NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3707N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF UC1707, UC1707-SP, UC3707, UC3707M : • Catalog: UC3707, UC1707, UC3707M, UC3707 • Military: UC1707 • Space: UC1707-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UC2707DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 UC3707DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2707DWTR SOIC DW 16 2000 367.0 367.0 38.0 UC3707DWTR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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