SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
D Organization . . . 4 194 304 × 72 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D JEDEC 168-Pin Dual-In-Line Memory
D
D
D
D
Module (DIMM) With Buffer for Use With
Socket
TM4EP72xxB-xx — Uses Eighteen 16M-Bit
High-Speed (4M × 4-Bit) Dynamic Random
Access Memories (DRAMs)
High-Speed, Low-Noise LVTTL Interface
High-Reliability Plastic 26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix) and
26-Lead 300-Mil-Wide Surface-Mount Thin
Small-Outline Package (TSOP) (DGA Suffix)
Intended for Workstation / Server
Applications
D Long Refresh Periods:
D
D
D
D
D
− TM4EP72CxB: 64 ms (4 096 Cycles)
− TM4EP72BxB: 32 ms (2 048 Cycles)
3-State Output
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Performance Ranges
ACCESS
TIME
tRAC
(MAX)
’4EP72xxB-50
50 ns
’4EP72xxB-60
60 ns
’4EP72xxB-70
70 ns
ACCESS ACCESS EDO
TIME
TIME CYCLE
tCAC
tAA
tHPC
(MAX)
(MAX)
(MIN)
13 ns
25 ns
20 ns
15 ns
30 ns
25 ns
18 ns
35 ns
30 ns
description
The TM4EP72BxB is a 32M-byte, 168-pin, buffered, dual-in-line memory module (DIMM). The DIMM is
composed of eighteen TMS427409A, 4 194 304 × 4-bit 2K refresh EDO DRAMs, each in a 300-mil, 26-lead
plastic TSOP (DGA suffix) or SOJ package (DJ suffix), and two SN74LVT162244 16-bit buffers, each in a
48-lead plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS427409A data sheet
(literature number SMKS893).
The TM4EP72CxB is a 32M-byte, 168-pin, buffered DIMM. The DIMM is composed of eighteen TMS426409A,
4 194 304 × 4-bit 4K refresh EDO DRAMs, each in a 300-mil, 26-lead plastic TSOP (DGA suffix) or SOJ package
(DJ suffix), and two 16-bit buffers mounted on a substrate with decoupling capacitors. See the TMS427409A
data sheet (literature number SMKS893).
These modules are intended for multimodule workstation / server applications where buffering is needed for
address and control signals. Two copies of address 0 (A0 and B0) are defined to allow maximum performance
for 4-byte applications which interleave between two 4-byte banks. A0 is common to the DRAMs used for
DQ0−DQ31, while B0 is common to the DRAMs used for DQ32−DQ63.
operation
The TM4EP72xxB operates as eighteen TMS42x409As that are connected as shown in the TM4EP72xxB
functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
1
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM4EP72xPB
( SIDE VIEW )
PIN NOMENCLATURE − TM4EP72BxB
A[0:10]
A[0:10]
B0
DQ[0:63]
CB[0:7]
ID[0:1]
CAS0 and CAS4
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
PD[1:8]
PDE
NC
VDD
VSS
1
10
11
Row-Address Inputs
Column-Address Inputs
Addr0 for Bank 2 Devices
Data In / Data Out
Check Bit In / Check Bit Out
ID Pins
Column-Address Strobe
Row-Address Strobe
Write Enable
Output Enable
Presence Detect
Presence Detect Enable
No-Connect Pin
3.3-V Supply
Ground
PIN NOMENCLATURE − TM4EP72CxB
A[0:11]
A[0:9]
B0
DQ[0:63]
CB[0:7]
ID[0:1]
CAS0 and CAS4
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
PD[1:8]
PDE
NC
VDD
VSS
40
41
Row-Address Inputs
Column-Address Inputs
Addr0 for Bank 2 Devices
Data In / Data Out
Check Bit In / Check Bit Out
ID Pins
Column-Address Strobe
Row-Address Strobe
Write Enable
Output Enable
Presence Detect
Presence Detect Enable
No-Connect Pin
3.3-V Supply
Ground
PRESENCE DETECT
84
2
POST OFFICE BOX 1443
PIN
− 50
− 60
− 70
PD1
1
1
1
PD2
1
1
1
PD3
0
0
0
PD4
1
1
1
PD5
1
1
1
PD6
0
1
0
PD7
0
1
1
PD8
0
0
0
ID0
0
0
0
ID1
0
0
0
• HOUSTON, TEXAS 77251−1443
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
Pin Assignments
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
NO.
NAME
NO.
1
43
2
VSS
DQ0
3
DQ1
4
PIN
NAME
NO.
85
44
VSS
OE2
45
RAS2
DQ2
46
5
DQ3
6
7
VDD
DQ4
8
DQ5
9
PIN
NAME
NO.
PIN
NAME
127
86
VSS
DQ32
128
VSS
NC
87
DQ33
129
NC
CAS4
88
DQ34
130
NC
47
NC
89
DQ35
131
NC
48
WE2
90
132
PDE
49
91
133
50
VDD
NC
VDD
DQ36
92
DQ37
134
VDD
NC
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
DQ9
54
97
VSS
DQ41
138
55
VSS
DQ16
96
13
139
VSS
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
101
DQ45
143
18
60
102
144
61
NC
103
VDD
DQ46
VDD
DQ52
19
VDD
DQ14
VDD
DQ20
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
NC
22
CB1
64
NC
106
CB5
148
NC
23
VSS
NC
65
DQ21
107
DQ53
DQ22
108
VSS
NC
149
66
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
68
111
VDD
NC
152
69
VSS
DQ24
110
27
VDD
WE0
153
VSS
DQ56
28
CAS0
70
DQ25
112
NC
154
DQ57
29
NC
71
DQ26
113
NC
155
DQ58
30
RAS0
72
DQ27
114
NC
156
DQ59
31
OE0
73
115
NC
157
32
74
116
VDD
DQ60
75
DQ29
117
VSS
A1
158
33
VSS
A0
VDD
DQ28
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
A7
162
A8
79
VSS
PD1
120
37
121
A9
163
VSS
PD2
38
A10
80
PD3
122
A11
164
PD4
39
NC
81
PD5
123
NC
165
PD6
40
82
PD7
124
PD8
83
ID0
125
VDD
NC
166
41
VDD
NC
167
ID1
42
NC
84
VDD
126
B0
168
VDD
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
3
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
buffered dual-in-line memory module and components
The buffered dual-in-line memory module and components include:
D PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM4EP72xxB
RAS0
RAS2
WE0
WE2
OE0
OE2
CAS0
CAS4
CAS
DQ[0:3]
DQ[8:11]
CB[0:3]
DQ[20:23]
DQ[28:31]
DQ[0:3]
A0
U[0:8]
B0
A[1:n]
OE
W
W
OE
W
W
DQ[40:43]
OE
W
DQ[44:47]
OE
W
CB[4:7]
DQ[48:51]
DQ[52:55]
OE
CAS
DQ[56:59]
OE
CAS
DQ[60:63]
VDD
RAS
W
RAS
W
RAS
W
RAS
W
RAS
UB6
OE
DQ[0:3]
W
UB5
DQ[0:3]
RAS
RAS
UB4
DQ[0:3]
RAS
W
RAS
UB7
U[0:8], UB[0:8]
Two 0.1 µF (minimum)
per DRAM
UB[0:8]
A[1:n]: U[0:8], UB[0:8]
POST OFFICE BOX 1443
OE
CAS
RAS
W
UB8
DQ[0:3]
VSS
4
OE
CAS
RAS
UB3
DQ[0:3]
RAS
U7
OE
CAS
W
UB2
DQ[0:3]
RAS
U6
OE
CAS
RAS
UB1
DQ[0:3]
RAS
U5
OE
CAS
W
UB0
DQ[0:3]
RAS
U4
OE
CAS
DQ[36:39]
U8
DQ[0:3]
CAS
W
OE
DQ[0:3]
RAS
U3
DQ[0:3]
CAS
DQ[24:27]
OE
DQ[0:3]
CAS
DQ[32:35]
U2
DQ[0:3]
CAS
DQ[16:19]
OE
DQ[0:3]
CAS
W
CAS
RAS
U1
DQ[0:3]
CAS
DQ[12:15]
OE
DQ[0:3]
CAS
W
U0
DQ[0:3]
CAS
DQ[4:7]
OE
• HOUSTON, TEXAS 77251−1443
U[0:8], UB[0:8]
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM4EP72xxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
recommended operating conditions
MIN
NOM
MAX
3
3.3
3.6
VDD
VSS
Supply voltage
VIH
VIL
High-level input voltage
2
Low-level input voltage
TA
Ambient temperature
Supply voltage
0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UNIT
V
V
V
−0.3
VDD + 0.3
0.8
0
70
°C
V
5
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM4EP72BxB
PARAMETER
’4EP72BxB-50
TEST CONDITIONS†
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
MIN
LVTTL
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Average read- or
write-cycle
current
VDD = 3.6 V,
ICC2
MAX
MIN
2.4
VOH
Average standby
current
’4EP72BxB-60
LVCMOS
LVTTL
MAX
2.4
VDD −0.2
’4EP72BxB-70
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 20
± 20
± 20
µA
VO = 0 V to VDD,
± 20
± 20
± 20
µA
Minimum cycle
2 160
1 800
1 620
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
36
36
36
mA
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RASx and CASx high
18
18
18
mA
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
2 160
1 800
1 620
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RASx low,
1 980
1 620
1 440
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP72CxB
PARAMETER
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Average read- or
write-cycle
current
VDD = 3.6 V,
ICC2
MIN
LVTTL
VOH
Average standby
current
’4EP72CxB-50
TEST CONDITIONS†
’4EP72CxB-60
MAX
MIN
2.4
LVCMOS
2.4
VDD −0.2
LVTTL
MAX
’4EP72CxB-70
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 20
± 20
± 20
µA
VO = 0 V to VDD,
± 20
± 20
± 20
µA
Minimum cycle
1 620
1 260
1 080
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
36
36
36
mA
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RASx and CASx high
18
18
18
mA
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
1 620
1 260
1 080
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RASx low,
1 800
1 620
1 440
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
7
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’4EP72xxB
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 −A10
6
pF
Ci(OE)
Input capacitance, OEx
6
pF
Ci(CAS)
Input capacitance, CASx
6
pF
Ci(RAS)
Input capacitance, RASx
65
pF
Ci(W)
Input capacitance, WEx
6
pF
9
pF
Co
Output capacitance
NOTE 2: VDD= NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’4EP72xxB-50
PARAMETER
MIN
MAX
’4EP72xxB-60
MIN
MAX
’4EP72xxB-70
MIN
MAX
UNIT
tAA
tCAC
Access time from column address (see Note 4)
30
35
40
ns
Access time from CASx (see Note 4)
18
20
23
ns
tCPA
tRAC
Access time from CASx precharge (see Note 4)
33
40
45
ns
Access time from RASx (see Note 4)
50
60
70
ns
tOEA
tCLZ
Access time from OEx (see Note 4)
18
20
23
ns
Delay time, CASx to output in low impedance
2
tREZ
tCEZ
Output buffer turn off delay from RASx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from CASx (see Note 5)
5
18
5
20
5
23
ns
tOEZ
tWEZ
Output buffer turn off delay from OEx (see Note 5)
5
18
5
20
5
23
ns
Output buffer turn off delay from WEx (see Note 5)
3
13
3
15
3
18
ns
2
2
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data in must not be driven
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’4EP72xxB-50
MIN
MAX
’4EP72xxB-60
MIN
MAX
’4EP72xxB-70
MIN
MAX
UNIT
tHPC
tPRWC
Cycle time, EDO page mode, read-write
20
25
30
ns
Cycle time, EDO read-write
55
64
71
ns
tCSH
tCHO
Delay time, RASx active to CASx precharge
38
46
56
ns
Hold time, OEx from CASx
7
10
10
ns
tDOH
tCAS
Hold time, output from CASx
5
5
5
ns
Pulse duration, CASx active
8
tWPE
tOCH
Pulse duration, WEx active (output disable only)
7
7
7
ns
Setup time, OEx before CASx
8
10
10
ns
tCP
tOEP
Pulse duration, CASx precharge
8
10
10
ns
Precharge time, OEx
5
5
5
ns
10 000
NOTE 3: With ac parameters, it is assumed that tT = 2 ns.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
10
10 000
12
10 000
ns
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements (see Note 3)
’4EP72xxB-50
MIN
MAX
’4EP72xxB-60
MIN
MAX
’4EP72xxB-70
MIN
MAX
UNIT
tRC
tRWC
Cycle time, random read or write
tRASP
tRAS
Pulse duration, RASx active, fast page mode (see Note 6)
50 100 000
60 100 000
70 100 000
ns
Pulse duration, RASx active, non-page mode (see Note 6)
50
60
70
ns
tRP
tWP
Pulse duration, RASx precharge
30
40
50
ns
Pulse duration, write command
9
11
11
ns
tASC
tASR
Setup time, column address
0
0
0
ns
Setup time, row address
5
5
5
ns
tDS
tRCS
Setup time, data in (see Note 7)
5
5
5
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CASx precharge
9
11
13
ns
Setup time, write command before RASx precharge
10
12
14
ns
0
0
0
ns
tWCS
Cycle time, read-write
Setup time, write command before CASx active
(early-write only)
84
104
124
ns
116
140
165
ns
10 000
10 000
10 000
tWRP
tWTS
Setup time, WEx high before RAS low (CBR refresh only)
12
12
12
ns
Setup time, WEx low before RAS low (test mode only)
12
12
12
ns
tCSR
tCAH
Setup time, CASx referenced to RASx ( CBR refresh only )
3
3
3
ns
tDH
tRAH
Hold time, data in (see Note 7)
tRCH
tRRH
tWCH
tROH
Hold time, write command during CASx active ( early-write only )
Hold time, RASx referenced to OEx
tWRH
tWTH
tCHR
tOEH
Hold time, CASx referenced to RASx ( CBR refresh only )
tRHCP
tAWD
Hold time, column address
8
10
12
ns
13
15
17
ns
Hold time, row address
6
8
8
ns
Hold time, read command referenced to CASx (see Note 8)
0
0
0
ns
Hold time, read command referenced to RASx (see Note 8)
−2
−2
−2
ns
9
11
13
ns
8
10
10
ns
Hold time, WEx high after RAS low (CBR refresh)
12
12
12
ns
Hold time, WEx low after RAS low (test mode only)
12
12
12
ns
8
8
8
ns
Hold time, OEx command
14
16
19
ns
Hold time, RASx active from CASx precharge
33
40
45
ns
Delay time, column address to write command ( read-write only )
47
54
62
ns
tCPW
tCRP
Delay time, WEx low after CASx precharge (read-write only)
45
54
62
ns
3
3
3
ns
tCWD
tOED
Delay time, CASx to write command ( read-write only )
35
39
45
ns
Delay time, OEx to data in
15
17
20
tRAD
tRAL
Delay time, RASx to column address (see Note 9)
Delay time, CASx precharge to RASx
8
Delay time, column address to RASx precharge
tCAL
Delay time, column address to CASx precharge
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
6. In a read-write cycle, tRWD and tRWL must be observed.
7. Referenced to the later of CASx or WEx in write operations
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. The maximum value is specified only to ensure access time.
POST OFFICE BOX 1443
20
10
25
10
ns
30
ns
30
35
40
ns
20
23
28
ns
• HOUSTON, TEXAS 77251−1443
9
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements (see Note 3) (continued)
’4EP72xxB-50
tRCD
tRPC
Delay time, RASx to CASx ( see Note 9)
tRSH
tRWD
Delay time, RASx precharge to CASx
’4EP72xxB-60
’4EP72xxB-70
MIN
MAX
MIN
MAX
MIN
MAX
10
32
12
40
12
47
UNIT
ns
3
3
3
ns
Delay time, CASx active to RASx precharge
18
20
23
ns
Delay time, RASx to write command (read-write only)
67
79
92
ns
tTAA
tTCPA
Access time from address (test mode)
30
35
40
ns
Access time from column precharge (test mode)
40
45
50
ns
tTRAC
tREF
Access time from RASx (test mode)
50
60
70
ns
Refresh time interval
32
tT
Transition time
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
9. The maximum value is specified only to ensure access time.
10
POST OFFICE BOX 1443
2
• HOUSTON, TEXAS 77251−1443
30
32
2
30
2
32
ms
30
ns
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
device symbolization (TM4EP72BPB illustrated)
TM4EP72BPB
-SS
Buffered Key Position
YYMMT
3.3-V Voltage Key Position
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
11
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
MECHANICAL DATA
BRW (R-PDIM-N168)
DUAL IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
(Note D)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
0.039 (1,00) TYP
0.125 (3,18)
0.054 (1,37)
0.046 (1,17)
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.050 (1,27)
0.014 (0,35) MAX
0.118 (3,00) TYP
0.125 (3,18)
0.700 (17,78) TYP
0.118 (3,00) DIA
2 Places
1.005 (25,53)
0.995 (25,27)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double-Sided DIMM Only)
4088184/A 00/97
NOTES: A.
B.
C.
D.
E.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MO-161
Dimension includes De−panelization variations; applies between notch and tab edge.
Outline may vary above notches to allow router/panelization irregularities.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
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