CDCVF2505-Q1 www.ti.com........................................................................................................................................................................................... SCAS867 – DECEMBER 2008 3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER FEATURES 1 • • • • • • • • • Qualified for Automotive Applications Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Applications Spread-Spectrum Clock Compatible Operating Frequency: 24 MHz to 200 MHz Low Jitter (Cycle-to-Cycle): <150 ps Over the Range 66 MHz to 200 MHz Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay) Three-States Outputs When There Is No Input Clock Operates From Single 3.3-V Supply Available in 8-Pin SOIC Package • • • • Consumes Less Than 100 µA (Typically) in Power Down Mode Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock 25-Ω On-Chip Series Damping Resistors Integrated RC PLL Loop Filter Eliminates the Need for External Components D PACKAGE (TOP VIEW) CLKIN 1Y1 1Y0 GND 1 8 2 7 3 6 4 5 CLKOUT 1Y3 VDD 3.3 V 1Y2 DESCRIPTION The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference. The CDCVF2505 is characterized for operation from –40°C to 85°C. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) SOIC – D Reel of 2500 ORDERABLE PART NUMBER CDCVF2505IDRQ1 TOP-SIDE MARKING CKV05Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated CDCVF2505-Q1 SCAS867 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com FUNCTION TABLE INPUT (1) OUTPUTS CLKIN 1Y[0–3] CLKOUT L L L H H H <10 MHz (1) Z Z Below 2 MHz (typical) the device goes into power-down mode, during which the PLL is turned off and the outputs enter into Hi-Z mode. If a >10-MHz signal is applied at CLKIN, the PLL turns on, reacquires lock, and stabilizes after approximately 100 µs. The outputs are then enabled. FUNCTIONAL BLOCK DIAGRAM 8 CLKIN 1 PLL CLKOUT 25 W 3 1Y0 25 W 2 Power Down 1Y1 25 W 5 1Y2 25 W 7 1Y3 25 W Edge Detect Typical <10 MHz 3-State TERMINAL FUNCTIONS NAME NO. 1Y0 3 1Y1 2 1Y2 5 1Y3 7 I/O DESCRIPTION O Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25-Ω series damping resistor. CLKIN 1 I Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the PLL to phase lock the feedback signal to CLKIN. CLKOUT 8 O Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs. GND 4 Power Ground VDD3.3V 6 Power 3.3-V supply 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 CDCVF2505-Q1 www.ti.com........................................................................................................................................................................................... SCAS867 – DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD Supply voltage range VI Input voltage range (2) (3) –0.5 V to VDD + 0.5 V VO Output voltage range (2) (3) –0.5 V to VDD + 0.5 V IIK Input clamp current VI < 0 or VI > VDD ±50 mA IOK Output clamp current VO < 0 or VO > VDD ±50 mA IO Continuous total output current VO = 0 to VDD ±50 mA θJA Package thermal impedance Tstg Storage temperature range (1) (2) (3) (4) –0.5 V to 4.3 V (4) 97.1°C/W –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 4.3 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. ELECTROSTATIC DISCHARGE INFORMATION ESD MODEL LIMIT HBM Human-Body Model 2000 V MM Machine Model 300 V CDM Charged-Device Model 1000 V RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3 3.3 3.6 UNIT VDD Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VDD V IOH High-level output current –12 mA IOL Low-level output current 12 mA TA Operating free-air temperature 85 °C 0.7 × VDD V V 0.3 × VDD 0 –40 V TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN fclk Clock frequency Input clock duty cycle MAX UNIT MHz 24 200 24 MHz to 85 MHz (1) 30 85 86 MHz to 200 MHz 40 Stabilization time (2) (1) (2) NOM 50 60 100 % µs Specified by design. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 3 CDCVF2505-Q1 SCAS867 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VIK Input voltage VOH Low-level output voltage IOH High-level output current IOL Low-level output current II Input current Ci Input capacitance Co MIN TYP (1) VDD II = –18 mA High-level output voltage VOL (1) TEST CONDITIONS 3V IOH = –12 mA 3V 2.1 IOH = –6 mA 3V 2.4 IOL = 100 µA MIN to MAX IOL = 12 mA 3V 0.8 IOL = 6 mA 3V 0.55 VO = 1 V 3V VDD – 0.2 V –27 mA –36 3V VO = 1.65 V V 0.2 3.3 V VO = 2 V 27 3.3 V mA 40 µA ±5 VI = 0 V or VDD 3.3 V VI = 0 V or VDD CLKOUT V MIN to MAX VI = 0 V or VDD Output capacitance UNIT –1.2 IOH = –100 µA VO = 1.65 V Yn MAX 4.2 pF 2.8 3.3 V pF 5.2 All typical values are at nominal VDD and TA = 25°C. SWITCHING CHARACTERISTICS (1) over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER MIN TYP (2) TEST CONDITIONS tpd Propagation delay, normalized (see Figure 1) CLKIN to Yn, f = 66 MHz to 200 MHz tsk(o) Output skew (3) Yn to Yn tc(jit_cc) Jitter (cycle to cycle) (see Figure 5) –150 MAX UNIT 150 ps 150 ps f = 66 MHz to 200 MHz 70 150 f = 24 MHz to 50 MHz 200 400 ps odc Output duty cycle (see Figure 4) f = 24 MHz to 200 MHz at 50% VDD 45 55 % tr Rise time VO = 0.4 V to 2 V 0.5 2 ns tf Fall time VO = 2 V to 0.4 V 0.5 2 ns (1) (2) (3) 4 Not production tested All typical values are at nominal VDD and TA = 25°C. The tsk(o) specification is only valid for equal loading of all outputs. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 CDCVF2505-Q1 www.ti.com........................................................................................................................................................................................... SCAS867 – DECEMBER 2008 TYPICAL CHARACTERISTICS tpd, PROPAGATION DELAY TIME vs FREQUENCY (TYPICAL VALUES at 3.3 V, 25°C) tPD, PROPAGATION DELAY TIME vs DELTA LOAD (TYPICAL VALUES at 3.3 V, 25°C) CLOCK FREQUENCY, f = 100 MHz 500 Load: CLKOUT = 12 pF || 500 W, Yn = 25 pF || 500 W 1400 Yn = 3 pF t pd – Propagation Delay Time – ps 1050 t pd – Propagation Delay Time – ps Yn = 25 pF CLKOUT = Y n = 25 pF || 500 W 3 pF || 500 W 700 350 CLKOUT 3 pF to 25 pF 0 -13 -350 -4 CLKOUT 3 pF to 25 pF -700 400 300 200 100 -1050 -1400 -30 0 25 -20 -10 0 10 Delta Load – pF 20 50 30 NOTE: Delta Load = CLKOUT Load – Yn Load Figure 1. 175 200 175 200 Figure 2. tpd, TYPICAL PROPAGATION DELAY TIME vs FREQUENCY (TUNED FOR MINIMUM DELAY) DUTY CYCLE vs FREQUENCY 150 55 Load: CLKOUT = 21 pF || 500 W, Yn = 25 pF || 500 W Load: CLKOUT = 12 pF || 500 W, Yn = 25 pF || 500 W 100 52.5 Duty Cycle – % t pd – Propagation Delay Time – ps 75 100 125 150 f – Frequency – MHz 50 0 50 -50 47.5 -100 -150 0 50 100 150 200 45 25 50 f – Frequency – MHz Figure 3. 75 100 125 150 f – Frequency – MHz Figure 4. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 5 CDCVF2505-Q1 SCAS867 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) ICC, SUPPLY CURRENT vs FREQUENCY CYCLE-to-CYCLE JITTER vs FREQUENCY 120 Worst Case at VCC = 3.6 V, T A = 85°C, Load: Y and CLKOUT = 25 pF || 500 W Typical Values at 3.3 V, TA = 25°C 100 400 I CC – Supply Current – mA t c(jit_CC) – Cycle-to-Cycle Jitter – ps 500 300 200 100 80 60 40 20 0 25 0 50 75 100 125 150 f – Frequency – MHz 175 200 0 20 Figure 5. 6 40 60 80 100 120 140 160 180 200 f – Frequency – MHz Figure 6. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 CDCVF2505-Q1 www.ti.com........................................................................................................................................................................................... SCAS867 – DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test 500 W Yn = 25 pF || 500 W CLKOUT = 12 pF || 500 W Figure 7. Test Load Circuit 3V 50% VDD CLKIN 0V tpd 2V 0.4 V 1Y0–1Y3 tr VOH 2V 50% VDD 0.4 V VOL tf Figure 8. Voltage Threshold for Measurements, Propagation Delay (tpd) Any Y 50 % VDD tsk(o) Any Y 50 % VDD Figure 9. Output Skew tc1 tc2 tc(jit_CC) = tc1 – tc2 Figure 10. Cycle-to-Cycle Jitter Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 7 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CDCVF2505IDRQ1 ACTIVE SOIC D Pins Package Eco Plan (2) Qty 8 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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