DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com Dual Full Bridge PWM Motor Driver Check for Samples: DRV8412, DRV8432 FEATURES 1 • • • • • • • • • • High-Efficiency Power Stage (up to 97%) with Low RDS(on) MOSFETs (110 mΩ at TJ = 25°C) Operating Supply Voltage up to 52 V DRV8412 (power pad down): up to 2 x 3 A Continuous Output Current (2 x 6 A Peak) in Dual Full Bridge Mode or 6 A Continuous Current in Parallel Mode (12 A Peak) DRV8432 (power pad up): up to 2 x 7 A Continuous Output Current ( 2 x 12 A Peak) in Dual Full Bridge Mode or 14 A Continuous Current in Parallel Mode (24 A Peak) PWM Operating Frequency up to 500 kHz Integrated Self-Protection Circuits Including Undervoltage, Overtemperature, Overload, and Short Circuit Programmable Cycle-by-Cycle Current Limit Protection Independent Supply and Ground Pins for Each Half Bridge Intelligent Gate Drive and Cross Conduction Prevention No External Snubber or Schottky Diode is Required The DRV8412/32 require two power supplies, one at 12 V for GVDD and VDD, and another up to 50 V for PVDD. The DRV8412/32 can operate at up to 500-kHz switching frequency while still maintain precise control and high efficiency. They also have an innovative protection system safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and two-stage thermal protection. The DRV8412/32 have a current-limiting circuit that prevents device shutdown during load transients such as motor start-up. A programmable overcurrent detector allows adjustable current limit and protection level to meet different motor requirements. The DRV8412/32 have unique independent supply and ground pins for each half bridge, which makes it possible to provide current measurement through external shunt resistor and support multiple motors with different power supply voltage requirements. Simplified Application Diagram GVDD GVDD_B OTW FAULT APPLICATIONS • • • • • • • Brushed DC and Stepper Motors Three Phase Permanent Magnet Synchronous Motors Robotic and Haptic Control System Actuators and Pumps Precision Instruments TEC Drivers LED Lighting Drivers DESCRIPTION Controller BST_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B AGND BST_B BST_C PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD PWM_D VDD GVDD_C M PVDD_B VREG M3 PVDD PVDD_A PWM_A GND GVDD GVDD_A M OUT_D PVDD_D PVDD BST_D GVDD_D The DRV8412/32 are high performance, integrated dual full bridge motor drivers with an advanced protection system. Because of the low RDS(on) of the H-Bridge MOSFETs and intelligent gate drive design, the efficiency of these motor drivers can be up to 97%, which enables the use of smaller power supplies and heatsinks, and are good candidates for energy efficient applications. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted (1) VALUE –0.3 V to 13.2 V VDD to GND –0.3 V to 13.2 V GVDD_X to GND PVDD_X to GND_X (2) –0.3 V to 70 V OUT_X to GND_X (2) –0.3 V to 70 V BST_X to GND_X (2) –0.3 V to 80 V Transient peak output current (per pin), pulse width limited by internal over-current protection circuit. 16 A Transient peak output current for latch shut down (per pin) 20 A VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X to GND –0.3 V to 4.2 V OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V –0.3 V to 7 V RESET_X, FAULT, OTW to GND Maximum continuous sink current (FAULT, OTW) 9 mA Maximum operating junction temperature range, TJ -40°C to 150°C Storage temperature, TSTG –55°C to 150°C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT PVDD_X Half bridge X (A, B, C, or D) DC supply voltage 0 50 52.5 V GVDD_X Supply for logic regulators and gate-drive circuitry 10.8 12 13.2 V VDD Digital regulator supply voltage 10.8 12 13.2 V IO_PULSE Pulsed peak current per output pin (could be limited by thermal) 15 A IO Continuous current per output pin (DRV8432) FSW PWM switching frequency ROCP_CBC OC programming resistor range in cycle-by-cycle current limit modes ROCP_OCL OC programming resistor range in OC latching shutdown modes CBST Bootstrap capacitor range TON_MIN Minimum PWM pulse duration, low side TA Operating ambient temperature (1) 2 7 A 500 kHz 24 200 kΩ 22 200 kΩ 33 220 50 -40 nF nS 85 (1) °C Depending on power dissipation and heat-sinking, the DRV8412/32 can support ambient temperature in excess of 85°C. Refer to the package heat dissipation ratings table and package power deratings table. Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com PACKAGE HEAT DISSIPATION RATINGS DRV8412 DRV8432 RθJC, junction-to-case (power pad / heat slug) thermal resistance PARAMETER 1.1 °C/W 0.9 °C/W RθJA, junction-to-ambient thermal resistance 25 °C/W This device is not intended to be used without a heatsink. Therefore, RθJA is not specified. See the Thermal Information section. Exposed power pad / heat slug area 34 mm2 80 mm2 PACKAGE POWER DERATINGS (DRV8412) (1) PACKAGE TA = 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING 44-PIN TSSOP (DDW) 5.0 W 40.0 mW/°C 3.2 W 2.6 W 1.0 W (1) Based on EVM board layout MODE SELECTION PINS MODE PINS M3 M2 M1 OUTPUT CONFIGURATION 0 0 0 2 FB or 4 HB Dual full bridges (two PWM inputs each full bridge) or four half bridges with cycle-by-cycle current limit 0 0 1 2 FB or 4 HB Dual full bridges (two PWM inputs each full bridge) or four half bridges with OC latching shutdown (no cycle-by-cycle current limit) 0 1 0 1 PFB 0 1 1 2 FB 1 x x Copyright © 2009–2011, Texas Instruments Incorporated DESCRIPTION Parallel full bridge with cycle-by-cycle current limit Dual full bridges (one PWM input each full bridge with complementary PWM on second half bridge) with cycle-by-cycle current limit Reserved 3 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com DEVICE INFORMATION Pin Assignment Here are the pinouts for the DRV8412/32: • DRV8412: 44-pin TSSOP power pad down DDW package. This package contains a thermal pad that is located on the bottom side of the device for dissipating heat through PCB. • DRV8432: 36-pin PSOP3 DKD package. This package contains a thick heat slug that is located on the top side of the device for dissipating heat through heatsink. DRV8412 DDW Package (Top View) DRV8432 DKD Package (Top View) GVDD_C 1 44 VDD NC NC PWM_D RESET_CD PWM_C 2 43 3 42 4 41 5 40 6 39 7 38 M1 M2 M3 VREG AGND GND OC_ADJ PWM_B RESET_AB PWM_A 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 FAULT NC NC OTW GVDD_B 17 28 18 27 19 26 20 25 21 24 22 23 GVDD_D BST_D NC PVDD_D PVDD_D OUT_D GND_D GND_C OUT_C PVDD_C BST_C BST_B PVDD_B OUT_B GND_B GND_A OUT_A PVDD_A PVDD_A NC BST_A GVDD_A GVDD_B 1 36 OTW FAULT PWM_A 2 35 3 34 4 33 RESET_AB PWM_B OC_ADJ 5 32 GND AGND VREG M3 6 31 7 30 8 29 9 28 10 27 11 26 M2 M1 PWM_C 12 25 13 24 14 23 RESET_CD PWM_D 15 22 16 21 VDD GVDD_C 17 20 18 19 GVDD_A BST_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D BST_D GVDD_D PIN FUNCTIONS PIN (1) 4 NAME DRV8412 DRV8432 FUNCTION DESCRIPTION (1) AGND 12 9 P Analog ground BST_A 24 35 P High side bootstrap supply (BST), external capacitor to OUT_A required BST_B 33 28 P High side bootstrap supply (BST), external capacitor to OUT_B required BST_C 34 27 P High side bootstrap supply (BST), external capacitor to OUT_C required BST_D 43 20 P High side bootstrap supply (BST), external capacitor to OUT_D required GND 13 8 P Ground GND_A 29 32 P Power ground for half-bridge A requires close decoupling capacitor to ground GND_B 30 31 P Power ground for half-bridge B requires close decoupling capacitor to ground GND_C 37 24 P Power ground for half-bridge C requires close decoupling capacitor to ground GND_D 38 23 P Power ground for half-bridge D requires close decoupling capacitor to ground GVDD_A 23 36 P Gate-drive voltage supply GVDD_B 22 1 P Gate-drive voltage supply GVDD_C 1 18 P Gate-drive voltage supply GVDD_D 44 19 P Gate-drive voltage supply M1 8 13 I Mode selection pin I = input, O = output, P = power, T = thermal Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com PIN NAME FUNCTION DESCRIPTION (1) DRV8412 DRV8432 M2 9 12 I Mode selection pin M3 10 11 I Reserved mode selection pin, AGND connection is recommended NC 3,4,19,20,25,42 – – No connection pin. Ground connection is recommended OC_ADJ 14 7 O Analog overcurrent programming pin, requires resistor to AGND OTW 21 2 O Overtemperature warning signal, open-drain, active-low. An internal pull-up resistor to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be obtained by adding external pull-up resistor to 5 V OUT_A 28 33 O Output, half-bridge A OUT_B 31 30 O Output, half-bridge B OUT_C 36 25 O Output, half-bridge C OUT_D 39 22 O Output, half-bridge D PVDD_A 26,27 34 P Power supply input for half-bridge A requires close decoupling capacitor to ground. PVDD_B 32 29 P Power supply input for half-bridge B requires close decoupling capacitor to gound. PVDD_C 35 26 P Power supply input for half-bridge C requires close decoupling capacitor to ground. PVDD_D 40,41 21 P Power supply input for half-bridge D requires close decoupling capacitor to ground. PWM_A 17 4 I Input signal for half-bridge A PWM_B 15 6 I Input signal for half-bridge B PWM_C 7 14 I Input signal for half-bridge C PWM_D 5 16 I Input signal for half-bridge D RESET_AB 16 5 I Reset signal for half-bridge A and half-bridge B, active-low RESET_CD 6 15 I Reset signal for half-bridge C and half-bridge D, active-low FAULT 18 3 O Fault signal, open-drain, active-low. An internal pull-up resistor to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be obtained by adding external pull-up resistor to 5 V VDD 2 17 P Power supply for digital voltage regulator requires capacitor to ground for decoupling. VREG 11 10 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND. THERMAL PAD - N/A T Solder the exposed thermal pad to the landing pad on the pcb. Connect landing pad to bottom side of pcb through via for better thermal dissipation. HEAT SLUG N/A - T Mount heat sink with thermal interface on top of the heat slug for best thermal performance. Copyright © 2009–2011, Texas Instruments Incorporated 5 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com SYSTEM BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG FAULT M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D FB/PFB−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl. Timing Gate Drive OUT_C FB/PFB−Configuration Pulldown Resistor GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv. Ctrl. Timing Gate Drive OUT_B FB/PFB−Configuration Pulldown Resistor GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv. Ctrl. Timing Gate Drive OUT_A FB/PFB−Configuration Pulldown Resistor GND_A 6 Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS TA = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 400 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.95 3.3 3.65 9 12 mA 2.5 mA 1 mA Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as a reference node IVDD VDD supply current VDD = 12 V Idle, reset mode Operating, 50% duty cycle V 10.5 Reset mode 1.7 IGVDD_X Gate supply current per half-bridge IPVDD_X Half-bridge X (A, B, C, or D) idle current Reset mode 0.7 MOSFET drain-to-source resistance, low side (LS) TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance 110 mΩ MOSFET drain-to-source resistance, high side (HS) TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance 110 mΩ VF Diode forward voltage drop TJ = 25°C - 125°C, IO = 5 A 1 V tR Output rise time Resistive load, IO = 5 A 14 nS tF Output fall time Resistive load, IO = 5 A 14 nS tPD_ON Propagation delay when FET is on Resistive load, IO = 5 A 38 nS tPD_OFF Propagation delay when FET is off Resistive load, IO = 5 A 38 nS tDT Dead time between HS and LS FETs Resistive load, IO = 5 A 5.5 nS 8.5 V Operating, 50% duty cycle 8 Output Stage RDS(on) I/O Protection Gate supply voltage GVDD_X undervoltage protection threshold Vuvp,G Vuvp,hyst (1) Hysteresis for gate supply undervoltage event OTW (1) Overtemperature warning OTWhyst (1) Hysteresis temperature to reset OTW event OTSD (1) Overtemperature shut down OTEOTWdifferential (1) 0.8 115 125 V 135 °C 25 °C 150 °C OTE-OTW overtemperature detect temperature difference 25 °C OTSDHYST (1) Hysteresis temperature for FAULT to be released following an OTSD event 25 °C IOC Overcurrent limit protection Resistor—programmable, nominal, ROCP = 27 kΩ 9.7 A IOCT Overcurrent response time Time from application of short condition to Hi-Z of affected FET(s) 250 ns RPD Internal pulldown resistor at the output of each half-bridge Connected when RESET_AB or RESET_CD is active to provide bootstrap capacitor charge 1 kΩ Static Digital Specifications VIH High-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3 2 3.6 V VIH High-level input voltage RESET_AB, RESET_CD 2 5.5 V VIL Low-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD 0.8 V llkg Input leakage current 100 μA kΩ –100 OTW / FAULT RINT_PU Internal pullup resistance, OTW to VREG, FAULT to VREG VOH High-level output voltage VOL Low-level output voltage (1) Internal pullup resistor only External pullup of 4.7 kΩ to 5 V IO = 4 mA 20 26 35 2.95 3.3 3.65 4.5 5 0.2 0.4 V V Specified by design Copyright © 2009–2011, Texas Instruments Incorporated 7 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY vs SWITCHING FREQUENCY (DRV8432) NORMALIZED RDS(on) vs GATE DRIVE 1.10 100 TJ = 25°C Normalized RDS(on) / (RDS(on) at 12 V) 90 80 Efficiency – % 70 60 50 40 30 Full Bridge 20 Load = 5 A PVDD = 50 V TC = 75°C 10 0 0 50 1.08 1.06 1.04 1.02 1.00 0.98 0.96 8.0 100 150 200 250 300 350 400 450 500 8.5 9.0 10.5 11.0 11.5 Figure 1. Figure 2. NORMALIZED RDS(on) vs JUNCTION TEMPERATURE DRAIN TO SOURCE DIODE FORWARD ON CHARACTERISTICS 1.6 12 6 TJ = 25°C GVDD = 12 V 5 1.4 4 1.2 I – Current – A Normalized RDS(on) / (RDS(on) at 25oC) 10.0 GVDD – Gate Drive – V f – Switching Frequency – kHz 1.0 3 2 0.8 1 0.6 0.4 –40 –20 0 0 20 40 60 80 100 120 140 o TJ – Junction Temperature – C Figure 3. 8 9.5 –1 0 0.2 0.4 0.6 0.8 1 1.2 V – Voltage – V Figure 4. Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT DUTY CYCLE vs INPUT DUTY CYCLE 100 fS = 500 kHz TC = 25°C 90 Output Duty Cycle – % 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 Input Duty Cycle – % Figure 5. Copyright © 2009–2011, Texas Instruments Incorporated 9 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the DRV8412/32 need only a 12-V supply in addition to H-Bridge power supply (PVDD). An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, the high-side gate drive requiring a floating voltage supply, which is accommodated by built-in bootstrap circuitry requiring external bootstrap capacitor. To provide symmetrical electrical characteristics, the PWM signal path, including gate drive and output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has a separate gate drive supply (GVDD_X), a bootstrap pin (BST_X), and a power-stage supply pin (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Special attention should be paid to place all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. Furthermore, decoupling capacitors need a short ground path back to the device. For a properly functioning bootstrap circuit, a small ceramic capacitor (an X5R or better) must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 10 kHz to 500 kHz, the use of 100-nF ceramic capacitors (X5R or better), size 0603 or 0805, is recommended for the bootstrap supply. These 100-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET fully turned on during the remaining part of the PWM cycle. In an application running at a switching frequency lower than 10 kHz, the bootstrap capacitor might need to be increased in value. 10 Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pin (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a ceramic capacitor (X5R or better) placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the DRV8412/32 EVM board. The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the DRV8412/32 are fully protected against erroneous power-stage turn-on due to parasitic gate charging. Thus, voltage-supply ramp rates (dv/dt) are non-critical within the specified voltage range (see the Recommended Operating Conditions section of this data sheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The DRV8412/32 do not require a power-up sequence. The outputs of the H-bridges remain in a high impedance state until the gate-drive supply voltage GVDD_X and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, holding RESET_AB and RESET_CD in a low state while powering up the device is recommended. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. Powering Down The DRV8412/32 do not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the UVP voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down to prevent any unknown state during this transition. Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com ERROR REPORTING Bootstrap Capacitor Under Voltage Protection The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. When the device runs at a low switching frequency (e.g. less than 10 kHz with a 100-nF bootstrap capacitor), the bootstrap capacitor voltage might not be able to maintain a proper voltage level for the high-side gate driver. A bootstrap capacitor undervoltage protection circuit (BST_UVP) will prevent potential failure of the high-side MOSFET. When the voltage on the bootstrap capacitors is less than the required value for safe operation, the DRV8412/32 will initiate bootstrap capacitor recharge sequences (turn off high side FET for a short period) until the bootstrap capacitors are properly charged for safe operation. This function may also be activated when PWM duty cycle is too high (e.g. less than 20 ns off time at 10 kHz). Note that bootstrap capacitor might not be able to be charged if no load or extremely light load is presented at output during BST_UVP operation, so it is recommended to turn on the low side FET for at least 50 ns for each PWM cycle to avoid BST_UVP operation if possible. Any fault resulting in device shutdown, such as overtemperatue shut down, overcurrent shut-down, or undervoltage protection, is signaled by the FAULT pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see Table 1). Table 1. Protection Mode Signal Descriptions FAULT OTW DESCRIPTION 0 0 Overtemperature warning and (overtemperature shut down or overcurrent shut down or undervoltage protection) occurred 0 1 Overcurrent shut-down or GVDD undervoltage protection occurred 1 0 Overtemperature warning 1 1 Device under normal operation TI recommends monitoring the OTW signal using the system microcontroller and responding to an OTW signal by reducing the load current to prevent further heating of the device resulting in device overtemperature shutdown (OTSD). To reduce external component count, an internal pullup resistor to VREG (3.3 V) is provided on both FAULT and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pull-up resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). DEVICE PROTECTION SYSTEM The DRV8412/32 contain advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overcurrent, overtemperature, and undervoltage. The DRV8412/32 respond to a fault by immediately setting the half bridge outputs in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overcurrent or overtemperature, the device automatically recovers when the fault condition has been removed or the gate supply voltage has increased. For highest possible reliability, reset the device externally no sooner than 1 second after the shutdown when recovering from an overcurrent shut down (OCSD) or OTSD fault. Copyright © 2009–2011, Texas Instruments Incorporated For applications with lower than 10 kHz switching frequency and not to trigger BST_UVP protection, a larger bootstrap capacitor can be used (e.g., 1 µF cap for 800 Hz operation). When using a bootstrap cap larger than 220 nF, it is recommended to add 5 Ω resistors between 12V GVDD power supply and GVDD_X pins to limit the inrush current on the internal bootstrap circuitry. Overcurrent (OC) Protection The DRV8412/32 have independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. There are two settings for OC protection through mode selection pins: cycle-by-cycle (CBC) current limiting mode and OC latching (OCL) shut down mode. In CBC current limiting mode, the detector outputs are monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a CBC current-limiting function rather than prematurely shutting down the device. This feature could effectively limit the inrush current during motor start-up or transient without damaging the device. During short to power and short to ground conditions, the current limit circuitry might not be able to control the current to a proper level, a second protection system triggers a latching shutdown, resulting in the related half bridge being set in the high-impedance (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A, B, C, and, D, respectively. 11 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 Figure 6 illustrates cycle-by-cycle operation with high side OC event and Figure 7 shows cycle-by-cycle operation with low side OC. Dashed lines are the operation waveforms when no CBC event is triggered and solide lines show the waveforms when CBC event is triggered. In CBC current limiting mode, when low side FET OC is detected, devcie will turn off the affected low side FET and keep the high side FET at the same half brdige off until next PWM cycle; when high side FET OC is detected, devcie will turn off the affected high side FET and turn on the low side FET at the half brdige until next PWM cycle. In OC latching shut down mode, the CBC current limit and error recovery circuitries are disabled and an overcurrent condition will cause the device to shutdown immediately. After shutdown, RESET_AB and/or RESET_CD must be asserted to restore normal operation after the overcurrent condition is removed. For added flexibility, the OC threshold is programmable using a single external resistor connected between the OC_ADJ pin and GND pin. See Table 2 for information on the correlation between programming-resistor value and the OC threshold. The values in Table 2 show typical OC thresholds for a given resistor. Assuming a fixed resistance on the OC_ADJ pin across multiple devices, a 20% device-to-device variation in OC threshold measurements is possible. Therefore, this feature is designed for system protection and not for precise current control. It should be noted that a properly functioning overcurrent detector assumes the presence of a proper inductor or power ferrite bead at the power-stage output. Short-circuit protection is not guaranteed with direct short at the output pins of the power stage. www.ti.com For a system that has limited space, a power ferrite bead can be used instead of an inductor. The current rating of ferrite bead has to be higher than the RMS current of the system at normal operation. A ferrite bead designed for very high frequency is NOT recommended. A minimum impedance of 10 Ω or higher is recommended at 10 MHz or lower frequency to effectively limit the current rising rate during short circuit condition. The TDK MPZ2012S300A (with size of 0805 inch type) have been tested in our system to meet a short circuit condition in the DRV8412. But other ferrite beads that have similar frequency characteristics can be used as well. For higher power applications, such as in the DRV8432, there might be limited options to select suitable ferrite bead with high current rating. If an adequate ferrite bead cannot be found, an inductor can be used. The inductance can be calculated as: PVDD × Toc _ delay Loc _ min = Ipeak - Iave Where Toc_delay = 250 nS, Ipeak = 15 A (below abs max rating). Because an inductor usually saturates quickly after reaching its current rating, it is recommended to use an inductor with a doubled value or an inductor with a current rating well above the operating condition. Table 2. Programming-Resistor Values and OC Threshold OC-ADJUST RESISTOR VALUES (kΩ) MAXIMUM CURRENT BEFORE OC OCCURS (A) 22(1) 11.6 24 10.7 27 9.7 30 8.8 36 7.4 39 6.9 43 6.3 47 5.8 56 4.9 68 4.1 82 3.4 100 2.8 120 2.4 150 1.9 200 1.4 For normal operation, inductance in motor (assume larger than 10 µH) is sufficient to provide low di/dt output (e.g. for EMI) and proper protection during overload condition (CBC current limiting feature). So no additional output inductors are needed during normal operation. However during a short condition, the motor (or other load) is shorted, so the load inductance is not present in the system anymore; the current in the device can reach such a high level that may exceed the abs max current rating due to extremely low impendence in the short circuit path and high di/dt before oc detection circuit kickes in. So a ferrite bead or inductor is recommended to utilize the short circuit protection feature in DRV8412/32. With an external inductance or ferrite bead, the current will rise at a much slower rate and reach a lower current level before oc protection starts. The device will then either operate CBC current limit or OC shut down automatically (when current is well above the current limit threshold) to protect the system. 12 (1) (1) Recommended to use in OC Latching Mode Only Overtemperature Protection The DRV8412/32 have a two-level Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 www.ti.com temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTSD is latched in this case and RESET_AB and RESET_CD must be asserted low to clear the latch. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the DRV8412/32 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overcurrent circuit and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased above the UVP threshold. Copyright © 2009–2011, Texas Instruments Incorporated SLES242D – DECEMBER 2009 – REVISED JULY 2011 DEVICE RESET Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high- impedance state. To accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. E.g., when either or both half-bridge A and B have OC shutdown, a low to high transition of RESET_AB pin will clear the fault and FAULT pin; when either or both half-bridge C and D have OC shutdown, a low to high transition of RESET_CD pin will clear the fault and FAULT pin as well. When an OTSD occurs, both RESET_AB and RESET_CD need to have a low to high transition to clear the fault and FAULT signal. 13 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com DIFFERENT OPERATIONAL MODES The DRV8412/32 support four different modes of operation: 1. Dual full bridges (FB) (two PWM inputs each full bridge) or four half bridges (HB) with CBC current limit 2. Dual full bridges (two PWM inputs each full bridge) or four half bridges with OC latching shutdown (no CBC current limit) 3. Parallel full bridge (PFB) with CBC current limit 4. Dual full bridges (one PWM input each full bridge) with CBC current limit In mode 1 and 2, PWM_A controls half bridge A, PWM_B controls half bridge B, etc. Figure 8 shows an application example for full bridge mode operation. In parallel full bridge mode (mode 3), PWM_A controls both half bridges A and B, and PWM_B controls both half bridges C and D, while PWM_C and PWM_D pins are not used (recommended to connect to ground). Bridges A and B are synchronized internally (even during CBC), and so are bridges C and D. OUT_A and OUT_B should be connected together and OUT_C and OUT_D should be connected together after the output inductor or ferrite bead. Figure 9 shows an example of parallel full bridge mode connection. In mode 4, one PWM signal controls one full bridge to relieve some I/O resource from MCU, i.e., PWM_A controls half bridges A and B and PWM_C controls half bridges C and D. In this mode, the operation of half bridge B is complementary to half bridge A, and the operation of half bridge D is complementary to half bridge C. For example, when PWM_A is high, high side FET in half bridge A and low side FET in half bridge B will be on and low side FET in half bridge A and high side FET in half bridge B will be off. Since PWM_B and PWM_D pins are not used in this mode, it is recommended to connect them to ground. Because each half bridge has independent supply and ground pins, a shunt sensing resistor can be inserted between PVDD to PVDD_X or GND_X to GND (ground plane). A high side shunt resistor between PVDD and PVDD_X is recommended for differential current sensing because a high bias voltage on the low side sensing could affect device operation. If low side sensing has to be used, a shunt resistor value of 10 mΩ or less or sense voltage 100 mV or less is recommended. The DRV8412/32 can be used for stepper motor applications as illustrated in Figure 10; they can be also used in three phase permanent magnet synchronous motor (PMSM) and sinewave brushless DC motor applications. Figure 11 shows an example of a TEC driver application. Same configuration can also be used for DC output applications. CBC with High Side OC During T_OC Period PVDD Current Limit Load Current PWM_HS Load PWM_LS PWM_HS PWM_LS GND_X T_HS T_OC T_LS Figure 6. Cycle-by-Cycle Operation with High Side OC (dashed line: normal operation; solid line: CBC event) 14 Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com During T_OC Period CBC with Low Side OC PVDD Current Limit Load Current PWM_HS PWM_HS Load PWM_LS PWM_LS T_LS T_OC T_HS GND_X Figure 7. Cycle-by-Cycle Operation with Low Side OC (dashed line: normal operation; solid line: CBC event) GVDD 1uF 330 uF PVDD 3.3 1000 uF GVDD_B 1uF OTW GVDD_A 10 nF BST_A 100 nF FAULT PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B Rsense_AB (option) 100nF Controller (MSP430 C2000 or Stellaris MCU) Roc_adj M 100nF OC_ADJ OUT_B 1 GND 100 nF PVDD_B AGND BST_B VREG BST_C M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 100 nF 100 nF Rsense_CD (option) 100nF PWM_D M 100nF PVDD_D 100 nF GVDD VDD 47 uF BST_D 1uF GVDD_C 1uF PVDD GVDD_D 1uF Figure 8. Application Diagram Example for Full Bridge Mode Operation Copyright © 2009–2011, Texas Instruments Incorporated 15 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com GVDD 1uF 330 uF PVDD 3.3 1000 uF GVDD_B 1uF OTW GVDD_A 10 nF BST_A 100 nF FAULT Controller (MSP430 C2000 or Stellaris MCU) Rsense_AB (option) PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B 100nF Roc_adj 100nF Loc Loc 1 GND PVDD_B AGND BST_B VREG BST_C M 100 nF 100 nF 100 nF M3 Rsense_CD (option) PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 100nF 100nF PWM_D Loc Loc PVDD_D 100 nF GVDD VDD BST_D 1uF 47 uF GVDD_C PVDD GVDD_D 1uF 1uF PWM_A controls OUT_A and OUT_B; PWM_B controls OUT_C and OUT_D. Figure 9. Application Diagram Example for Parallel Full Bridge Mode Operation GVDD 1uF 330 uF PVDD 3.3 1000 uF GVDD_B 1uF OTW GVDD_A 10 nF BST_A 100 nF FAULT PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B 100nF M Controller (MSP430 C2000 or Stellaris MCU) Roc_adj 100nF OC_ADJ OUT_B 1 GND PVDD_B AGND BST_B VREG BST_C 100 nF 100 nF 100 nF M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 100nF 100nF PWM_D PVDD_D 100 nF GVDD VDD 47 uF BST_D 1uF GVDD_C 1uF PVDD GVDD_D 1uF Figure 10. Application Diagram Example for Stepper Motor Operation 16 Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com GVDD 1uF PVDD 330 uF 3.3 1000 uF GVDD_A GVDD_B 1uF OTW 10 nF BST_A 100 nF PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B 100nF Roc_adj TEC Controller 100nF 4.7 uH 4.7 uH 1 GND 47 uF PVDD_B AGND BST_B VREG BST_C 100 nF 100 nF 100 nF M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D PWM_D 47 uF 100nF 100nF TEC FAULT 47 uF 4.7 uH 47 uF 4.7 uH 47 uF PVDD_D 100 nF GVDD VDD BST_D 1uF 47 uF GVDD_C PVDD GVDD_D 1uF 1uF Figure 11. Application Diagram Example for TEC Driver VIN Up to 50V VDD GVDD_C RESET_CD GVDD_D RESET_AB GVDD_B GVDD_A 12V PVDD_A PVDD_B PWM_A PVDD_C PWM_B PVDD_D PWM_C BST_A PWM_D OUT_A VLED BST_B FAULT DRV8412 OTW OUT_B BST_C OC_ADJ OUT_C BST_D OUT_D GND_D GND_C GND_B AGND M3 GND M2 GND_A M1 VREG Figure 12. Application Diagram Example for LED Lighting Driver Copyright © 2009–2011, Texas Instruments Incorporated 17 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com APPLICATION INFORMATION SYSTEM DESIGN RECOMMENDATIONS Voltage of Decoupling Capacitor The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling capacitor should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage rating of 63 V is recommended. VREG Pin The VREG pin is used for internal logic and not recommended to be used as a voltage source for external circuitry. VDD Pin The transient current in VDD pin could be significantly higher than average current through that pin. A low resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the 100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient. OTW Pin OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to decrease system power when OTW is low in order to prevent OT shut down at a higher temperature. Mode Select Pin Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND. Parallel Mode Operation For a device operated in parallel mode, a minimum of 30 nH to 100 nH inductance or a ferrite bead is required after the output pins (e.g. OUT_A and OUT_B) before connecting the two channels together. This will help to prevent any shoot through between two paralleled channels during switching transient due to mismatch of paralleled channels (e.g., processor variation, unsymmetrical PCB layout, etc). TEC Driver Application For TEC driver or other non-motor related applications (e.g. resistive load or dc output), a low-pass LC filter can be used to meet the requirement. PCB LAYOUT RECOMMENDATION PCB Material Recommendation FR-4 Glass Epoxy material with 2 oz. copper on both top and bottom layer is recommended for improved thermal performance (better heat sinking) and less noise susceptibility (lower PCB trace inductance). Ground Plane Because of the power level of these devices, it is recommended to use a big unbroken single ground plane for the whole system / board. The ground plane can be easily made at bottom PCB layer. In order to minimize the impedance and inductance of ground traces, the traces from ground pins should keep as short and wide as possible before connected to bottom ground plane through vias. Multiple vias are suggested to reduce the impedance of vias. Try to clear the space around the device as much as possible especially at bottom PCB side to improve the heat spreading. Decoupling Capacitor High frequency decoupling capacitors (100 nF) on PVDD_X pins should be placed close to these pins and with a short ground return path to minimize the inductance on the PCB trace. 18 Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 www.ti.com SLES242D – DECEMBER 2009 – REVISED JULY 2011 AGND AGND is a localized internal ground for logic signals. A 1-Ω resistor is recommended to be connected between GND and AGND to isolate the noise from board ground to AGND. There are other two components are connected to this local ground: 0.1-µF capacitor between VREG to AGND and Roc_adj resistor between OC_ADJ and AGND. Capacitor for VREG should be placed close to VREG and AGND pin and connected without vias. Current Shunt Resistor If current shunt resistor is connected between GND_X to GND or PVDD_X to PVDD, make sure there is only one single path to connect each GND_X or PVDD_X pin to shunt resistor, and the path is short and symmetrical on each sense path to minimize the measurement error due to additional resistance on the trace. PCB LAYOUT EXAMPLE An example of the schematic and PCB layout of DRV8412 are shown in Figure 13, Figure 14, and Figure 15. Copyright © 2009–2011, Texas Instruments Incorporated 19 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com GVDD C14 1.0ufd/16V 0603 U1 GND 44 1 43 C13 42 1.0ufd/16V 0603 41 PVDD 40 GND 2 + 3 C11 C12 47ufd/16V FC 0.1ufd/16V 0603 C15 C16 0.1ufd/100V 0805 0.1ufd/100V 0805 4 GND 39 GND OUTD Orange GND 38 5 37 6 GVDD GND J2 1 2 GRAY 6A/250V 36 + C4 C5 330ufd/16V M 0.1ufd/16V 0603 OUTC Orange 35 7 PVDD 8 GVDD = 12V 9 GND C18 C19 0.1ufd/100V 0805 0.1ufd/100V 0805 PVDD 10 GND J1 + 34 11 1 33 2 C10 3 0.1ufd/16V 0603 4 5 R7 C20 C21 13 0.1ufd/100V 0805 0.1ufd/100V 0805 GND 8 R5 GND PVDD 12 1.0 1/4W 0805 7 Red C1 1000ufd/63V VZ 32 6 PVDD Black GND GND 14 31 15 30 OUTB 0603 47K Orange 29 GND 28 OUTA 16 Orange 27 17 26 18 19 PVDD C23 C24 0.1ufd/100V 0805 0.1ufd/100V 0805 20 U1 PowerPad GND 25 21 24 22 GVDD C9 GND 23 DRV8412DDW GVDD C8 HTSSOP44-DDW 1.0ufd/16V 0603 GND 1.0ufd/16V 0603 GND Figure 13. DRV8412 Schematic Example 20 Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com T1: PVDD decoupling capacitors C16, C19, C21, and C24 should be placed very close to PVDD_X pins and ground return path. T2: VREG decoupling capacitor C10 should be placed very close to VREG abd AGND pins. T3: Clear the space above and below the device as much as possible to improve the thermal spreading. T4: Add many vias to reduce the impedance of ground path through top to bottom side. Make traces as wide as possible for ground path such as GND_X path. Figure 14. Printed Circuit Board – Top Layer Copyright © 2009–2011, Texas Instruments Incorporated 21 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com B1: Do not block the heat transfer path at bottom side. Clear as much space as possible for better heat spreading. Figure 15. Printed Circuit Board – Bottom Layer THERMAL INFORMATION The thermally enhanced package provided with the DRV8432 is designed to interface directly to heat sink using a thermal interface compound, (e.g., Ceramique from Arctic Silver, TIMTronics 413, etc.). The heat sink then absorbs heat from the ICs and couples it to the local air. It is also a good practice to connect the heatsink to system ground on the PCB board to reduce the ground noise. RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the following components: • RθJC (the thermal resistance from junction to case, or in this example the power pad or heat slug) • Thermal grease thermal resistance • Heat sink thermal resistance 22 Copyright © 2009–2011, Texas Instruments Incorporated DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com The thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the thermal grease manufacturer's area thermal resistance (expressed in °C-in 2/W or °C-mm2/W). The approximate exposed heat slug size is as follows: • DRV8432, 36-pin PSOP3 …… 0.124 in2 (80 mm 2) The thermal resistance of thermal pads is considered higher than a thin thermal grease layer and is not recommended. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus the system RθJA = RθJC + thermal grease resistance + heat sink resistance. See the TI application report, IC Package Thermal Metrics (SPRA953A), for more thermal information. DRV8412 Thermal Via Design Recommendation Thermal pad of the DRV8412 is attached at bottom of device to improve the thermal capability of the device. The thermal pad has to be soldered with a very good coverage on PCB in order to deliver the power specified in the datasheet. The figure below shows the recommended thermal via and land pattern design for the DRV8412. For additional information, see TI application report, PowerPad Made Easy (SLMA004B) and PowerPad Layout Guidelines (SOLA120). Figure 16. DRV8412 Thermal Via Footprint Copyright © 2009–2011, Texas Instruments Incorporated 23 DRV8412 DRV8432 SLES242D – DECEMBER 2009 – REVISED JULY 2011 www.ti.com REVISION HISTORY Changes from Revision A (December 2009) to Revision B Page • Added note to recommended operating conditions table ..................................................................................................... 2 • Added TA = 125°C power rating of 1.0 W to package power deratings table ...................................................................... 3 Changes from Revision B (Jan 2010) to Revision C Page • Deleted all DRV8422 related descriptions from this data sheet ........................................................................................... 1 • Changed DRV8432 pinout .................................................................................................................................................... 4 • Added Thermal Pad and Heat slug rows to end of Pin Functions table. Also added T=thermal in note ............................. 5 • Added second paragraph to Bootstrap Capacitor....section ............................................................................................... 11 • Deleted or GVDD undervoltage from DEVICE RESET section second paragraph ............................................................ 13 Changes from Revision C (May 2010) to Revision D Page • Changed from 80 mΩ to 110 mΩ in first Feature ................................................................................................................. 1 • Changed from 50 V to 52 V in second Feature .................................................................................................................... 1 • Deleted (70 V Absolute Maximum) from second Feature ..................................................................................................... 1 • Added LED Lighting Drivers to Applications ......................................................................................................................... 1 • Added Includes metallization bond wire and pin resistance to RDS(on) test conditions ......................................................... 7 • Changed RDS(on) typ from 80 mΩ to 110 mΩ ........................................................................................................................ 7 • Added text to 5th paragraph of Overcurrent (OC) Protection section ................................................................................ 12 • Deleted Output Inductor Selection section and moved information into Overcurrent (OC) Protection section .................. 12 • Changed Figure 8 ............................................................................................................................................................... 15 • Changed Figure 10 ............................................................................................................................................................. 16 • Deleted Application Diagram Example for Three Phase PMSM PVDD Sense Operation and Application Diagram Example for Three Phase PMSM GND Sense Operation figures ...................................................................................... 17 • Added Figure 12 ................................................................................................................................................................. 17 • Changed Figure 13 ............................................................................................................................................................. 20 24 Copyright © 2009–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DRV8412DDW ACTIVE HTSSOP DDW 44 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8412DDWR ACTIVE HTSSOP DDW 44 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8432DKD ACTIVE HSSOP DKD 36 29 Green (RoHS & no Sb/Br) NIPDAU Level-4-260C-72 HR DRV8432DKDR ACTIVE HSSOP DKD 36 500 Green (RoHS & no Sb/Br) NIPDAU Level-4-260C-72 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8412DDWR Package Package Pins Type Drawing SPQ HTSSOP 2000 DDW 44 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8412DDWR HTSSOP DDW 44 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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