LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 Micropower DSBGA 150-mA Ultra Low-Dropout CMOS Voltage Regulator With Sleep MODE Check for Samples: LP3987 FEATURES DESCRIPTION • • The LP3987 is a 150mA fixed output voltage regulator with very low dropout voltage designed specially to meet requirements of battery-powered applications. The additional sleep MODE feature will reduce current consumption during standby operation to prolong the usage of battery. 1 2 • • Miniature 5-I/O DSBGA Package Stable With Ceramic and High-Quality Tantalum Output Capacitors Logic Controlled Enable Thermal Shutdown and Short-Circuit Current Limit Dropout Voltage: 100mV maximum dropout with 150mA load. APPLICATIONS • • • • • • • Shutdown: Less than 1µA quiescent current. CDMA Cellular Handsets Wideband CDMA Cellular Handsets GSM Cellular Handsets Portable Information Appliances µP/DSP Power Supplies Digital Cameras SRAM Backup Sleep Mode: Typically 14µA quiescent current during sleep MODE to reduce battery consumption. Enhanced Stability: The LP3987 is stable with minimum 1µF±20% low ESR ceramic output capacitor as low as 5mΩ and high quality tantalum capacitors. The LP3987 is available in a thin 5 Bump DSBGA package. Performance is specified for −40°C to 125°C. KEY SPECIFICATIONS • • • • • • • • This device is available with output voltage options of 2.5V, 2.6V, 2.8V, 2.85V, and 3.0V. For other voltage options, please contact Texas Instruments. 2.7 to 6.0V Input Range 150 mA Output Current 1μA Quiescent Current on Shutdown 100 mV Maximum Dropout with 150 mA Load 50dB PSRR at 10KHz Sleep MODE Features Over Temperature & Over Current Protection −40°C to +125°C Junction Temperature Range for Operation Typical Application Circuit C3 VIN VOUT C1 1PF 1PF LP3987 A1 VEN A3 MODE B2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com Block Diagram Figure 1. LP3987 Connection Diagram Figure 2. Top View 5 I/O DSBGA Package See Package Number YZR0005ADA PIN DESCRIPTIONS (1) 2 Name Pin (1) VEN A1 Enable Input Logic, Enable High GND B2 Common Ground VOUT C1 Output voltage of the LDO VIN C3 Input voltage of the LDO MODE A3 Power Mode Control, Active = 1, Sleep Mode = 0 Function The pin numbering scheme for the DSBGA package was revised in April, 2002 to conform to JEDEC standard. Only the pin numbers were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and MODE as pin 5. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 ORDERING INFORMATION (1) (2) DSBGA Package LP3987 Supplied as 250 Units Tape and Reel LP3987 Supplied as 3000 Units Tape and Reel 2.5V LP3987ITL-2.5 LP3987ITLX-2.5 2.6V LP3987ITL-2.6 LP3987ITLX-2.6 Output Voltage Grade 2.8V (1) (2) LP3987ITL-2.8 LP3987ITLX-2.8 2.85V STD LP3987ITL-2.85 LP3987ITLX-2.5 3.0V LP3987ITL-3.0 LP3987ITLX-3.0 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3 to 6.5V VIN −0.3 to 6.5V VEN, VMODE −0.3V to(V IN+ 0.3V) ≤ 6.5 VOUT −65°C to +150°C Storage Temperature ESD (4) Human Body Model 2KV Machine Model Maximum Power Dissipation (1) (2) (3) (4) (5) (5) θJA (DSBGA small bump) (1) (2) VIN VOUT+ 200mV to 6V VEN, VMODE 0 to 6.0V −40°C to +125°C Junction Temperature Maximum Power Dissipation (2) (3) 255°C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact theTI Sales Office/Distributors for availability and specifications. The human body model is 100pF discharged through 1.5kΩ. The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:PD = (TJ TA)/θJA,Where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For instant, if VIN in target application is 4.2V and worse case current consumption is 90mA. Therefore PMAX_DISSIPATION = (4.2-2.7)*0.09 =135mW. With PMAX_DISSIPATION is 135mW, TJmax is 125°C and worse case ambient temperature (TA ) in target application is 85°C, θJA = (125-85)/0.135 = 296°C/W. Operating Ratings (1) 200V (3) 392mW at 25°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:PD = (TJ TA)/θJA,Where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For instant, if VIN in target application is 4.2V and worse case current consumption is 90mA. Therefore PMAX_DISSIPATION = (4.2-2.7)*0.09 =135mW. With PMAX_DISSIPATION is 135mW, TJmax is 125°C and worse case ambient temperature (TA ) in target application is 85°C, θJA = (125-85)/0.135 = 296°C/W. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 3 LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com Electrical Characteristics Unless otherwise specified: VEN = 1.8V, MODE = 1.8V, VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF. Typical values and limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2) Parameter Test Conditions Output Voltage Tolerance IOUT = 1mA, 25°C -2 2 IOUT = 1mA −3 3 % of VOUT(nom) −0.1 0.1 %/V 0.0004 0.002 %/mA Load Regulation Error IOUT = 1mA to 150 mA Dropout Voltage Unit Max VIN = (VOUT(nom) + 0.5V) to 6.0V, IOUT = 1 mA (3) Limit Min Line Regulation Error ΔVOUT Typ IOUT = 1mA 0.4 2 IOUT = 150mA 60 100 (4) mV ΔVOUT(SLEEP) Output Voltage difference at MODE = 0V MODE = 0V, Transient Response Line Transient Response (5) MODE = 1.8V, ILOAD = 100mA, TRISE = TFALL = 10µS, VIN = 600mV P-P AC Square wave, (6) 21 mVpp Load Transient Response (5) MODE = 1.8V, COUT = 4.7µF, TRISE = TFALL = 100nS, VIN = 3.1V, 3.6V, 4.2V, (7) (8) 100 mVpk VIN = VOUT(nom) + 1V, MODE = 1.8V, f = <10 kHz, IOUT = 1mA 50 VIN = VOUT(nom) + 1V, MODE = 0V, f = <10 kHz, IOUT = 1mA 10 MODE = 1.8V, IOUT = 0mA, VIN = 4.2V 85 120 MODE = 1.8V, IOUT = 150mA, VIN = 4.2V 160 200 1 3 21 PSRR Power Supply Rejection Ratio (5) IQ(ON) Quiescent Current -150 +100 mV dB µA IQ(OFF) Quiescent Current ENABLE = 0V, VIN = 4.2V µA IQ(SLEEP) Current in Standby Mode MODE = 0V, IOUT = 50µA, VIN = 4.2V 14 ISC Short Circuit Current Limit (5) Output Grounded 600 ISC(SLEEP) Short Circuit Current in Sleep MODE Output Grounded 28 IOUT(ON) Maximum Output Current at MODE = 1.8V MODE = 1.8V IOUT(SLEEP) Maximum Output Current at MODE = 0V MODE = 0V en Output Noise Voltage (5) BW = 10 Hz to 100 kHz, COUT = 1µF 70 µVrms TSHUTDOWN Shutdown Temperature (5) Sleep MODE = 1.8V 155 °C µA mA 43 150 mA mA 3 mA Logic Control Characteristics IEN Maximum Input Current at EN VEN = 0 and VIN= 6.0V VIL Logic Low Input Threshold VIN = 3.05 to 6V VIH Logic High Input Threshold VIN = 3.05 to 6V (1) (2) (3) (4) (5) (6) (7) (8) 4 0.015 µA 0.5 V 1.2 V Min and Max Limits are verified by design, test, or statistical analysis. Typical (Typ.) numbers are not verified, but do represent the most likely norm. The nominal output voltage, which is labeled VOUT(nom), is the output voltage measured with the input 0.5V above VOUT(nom) and a 1mA load. Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output voltage. VIN less than minimum operating voltage may be used for test purposes. On/Sleep Mode voltage tolerance and current capability requirement. See Figure 3. This electrical specification is specified by design. Line Transient response requirement. See Figure 4. Load Transient response requirement. See Figure 5. During transient recovery, output voltage should not be oscillating. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 Electrical Characteristics (continued) Unless otherwise specified: VEN = 1.8V, MODE = 1.8V, VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF. Typical values and limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2) Parameter Test Conditions VMODE_L Logic Low Input Threshold VIN = 3.05 to 6V VMODE_H Logic High Input Threshold VIN = 3.05 to 6V IMODE Maximum Input Current at VMODE VMODE = 0 and VIN = 6.0V Typ Limit Min Max Unit 0.5 V 1.2 V µA 0.015 Timing Characteristics TON Turn on Time (On Mode) (5) (9) TSLEEP Turn on Time (Sleep Mode) (5) (10) MODE = 0V, COUT = 4.7µF TMODE Sleep to On Mode Settle Time (5) (11) COUT = 4.7µF, Enable = 1.8V MODE = 1.8V, COUT = 4.7µF 170 250 5 0.5 µs ms 300 200 µs (9) TON is measured from rising edge of Enable with MODE = 1.8V to when VOUT reaches 95% of final value. (10) TSLEEP is measured from rising edge of Enable with MODE = 0V to when VOUT reaches 95% of final value. (11) TMODE is measured from rising edge of MODE with ENABLE = 1.8V to time before full current capability. Figure 3. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 5 LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com Figure 4. Figure 5. 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN = VOUT(nom) + 0.5V, TA = 25°C, Enable pin is tied to VIN, MODE = 1.8V. Ground Current at TA = 25°C Ground Current at TA = 40°C Figure 6. Figure 7. Ground Current at TA = 85°C Dropout Voltage vs Load Current Figure 8. Figure 9. Ripple Rejection (CIN = COUT = 1µF, IL = 1mA) Ripple Rejection (VIN = VOUT(nom) + 1V, CIN = COUT = 1µF, IL = 1mA) Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 7 LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN = VOUT(nom) + 0.5V, TA = 25°C, Enable pin is tied to VIN, MODE = 1.8V. 8 TSLEEP at MODE = 0V, COUT = 1µF, IL = 1mA TSLEEP at MODE = 0V, COUT = 1µF, IL = 1mA Figure 12. Figure 13. TON at MODE = 1.8V, COUT = 1µF, IL = 150mA TON at MODE = 1.8V, COUT = 1µF, IL = 150mA Figure 14. Figure 15. TSLEEP at MODE = 0V, COUT = 4.7µF, IL = 1mA TSLEEP at MODE = 0V, COUT = 4.7µF, IL = 1mA Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN = VOUT(nom) + 0.5V, TA = 25°C, Enable pin is tied to VIN, MODE = 1.8V. TON at MODE = 1.8V, COUT = 4.7µF, IL = 150mA TON at MODE = 1.8V, COUT = 4.7µF, IL = 150mA Figure 18. Figure 19. TMODE Measurement at VIN = 3.05V TMODE Measurement at VIN = 3.6V Figure 20. Figure 21. TMODE Measurement at VIN = 4.2V Output Short Circuit Current Figure 22. Figure 23. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 9 LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN = VOUT(nom) + 0.5V, TA = 25°C, Enable pin is tied to VIN, MODE = 1.8V. 10 Output Short Circuit Current Load Transient Response at VIN = 3.1V Figure 24. Figure 25. Load Transient Response at VIN = 3.35V Load Transient Response at VIN = 3.6V Figure 26. Figure 27. Load Transient Response at VIN = 4.2V Load Transient Response at VIN = 3.1V, COUT = 1µF Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN = VOUT(nom) + 0.5V, TA = 25°C, Enable pin is tied to VIN, MODE = 1.8V. Load Transient Response at VIN = 3.35V, COUT = 1µF Load Transient Response at VIN = 4.2V, COUT = 1µF Figure 30. Figure 31. Load Transient Response at VIN = 3.6V, COUT = 1µF Output Voltage Change vs Temperature Figure 32. Figure 33. Line Transient Response Line Transient Response Figure 34. Figure 35. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 11 LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN = VOUT(nom) + 0.5V, TA = 25°C, Enable pin is tied to VIN, MODE = 1.8V. 12 Line Transient Response Line Transient Response Figure 36. Figure 37. Line Transient Response Line Transient Response Figure 38. Figure 39. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 APPLICATION HINTS EXTERNAL CAPACITORS Like any low-dropout regulator, the LP3987 requires external capacitors for regulator stability. The LP3987 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitance of ≊ 1µF is required between the LP3987 input pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be ≊ 1µF over the entire operating temperature range. OUTPUT CAPACITOR The LP3987 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types Z5U, Y5V or X7R) in 1 to 4.7 µF range with 5mΩ to 500mΩ ESR range is suitable in the LP3987 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see next section Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range (5 mΩ to 500 mΩ). NO-LOAD STABILITY The LP3987 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. CAPACITOR CHARACTERISTICS The LP3987 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1µF to 4.7µF range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3987. The ceramic capacitor's capacitance can vary with temperature. Most large value ceramic capacitors (≊ 2.2µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C. A better choice for temperature coefficient in a ceramic capacitor is X7R, which holds the capacitance within ±15%. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 13 LP3987 SNVS164G – OCTOBER 2001 – REVISED MAY 2013 www.ti.com ON/OFF INPUT OPERATION The LP3987 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used, the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. MODE OPERATION The LP3987 enters sleep mode by pulling MODE = 0V externally to reduce current during standby operation. During sleep mode, LP3987 consumes only 14µA of quiescent current and supplies up to 3mA of current. The device returns to active mode by pulling MODE = 1.8V. If this function is not used, the MODE pin should be tied to VIN. THERMAL PROTECTION The LP3987 has internal thermal protection circuitry to disable the internal pass transistor if the junction temperature exceeds 125°C to allow the device to cool down. The pass transistor will turn on when temperature falls below the maximum operating junction temperature of 125°C. This feature is designed to protect the device in the event of fault conditions. For normal operation, it is suggested to limit the device junction temperature to less than 125°C. DSBGA MOUNTING The DSBGA package requires specific mounting techniques which are detailed in Texas Instruments AN-1112 Application Report (SNOA401). Referring to the section PCB Layout, note that the pad style which must be used with the 5 pin package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. DSBGA LIGHT SENSITIVITY Exposing the DSBGA device to direct sunlight will cause misoperation of the device. Light sources such as Halogen lamps can effect electrical performance if brought near to the device. The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to within 1cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less than 0.1% from nominal. 14 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 LP3987 www.ti.com SNVS164G – OCTOBER 2001 – REVISED MAY 2013 REVISION HISTORY Changes from Revision F (May 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LP3987 15 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LP3987ITL-2.5/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 7 LP3987ITL-2.6/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP3987ITL-2.8/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP3987ITL-2.85/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP3987ITL-3.0/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 7 LP3987ITLX-2.5/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 7 LP3987ITLX-2.6/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP3987ITLX-2.8/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP3987ITLX-2.85/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP3987ITLX-3.0/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 7 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 3-May-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP3987ITL-2.5/NOPB DSBGA YZR 5 250 178.0 8.4 LP3987ITL-2.6/NOPB DSBGA YZR 5 250 178.0 LP3987ITL-2.8/NOPB DSBGA YZR 5 250 178.0 LP3987ITL-2.85/NOPB DSBGA YZR 5 250 LP3987ITL-3.0/NOPB DSBGA YZR 5 LP3987ITLX-2.5/NOPB DSBGA YZR LP3987ITLX-2.6/NOPB DSBGA YZR LP3987ITLX-2.8/NOPB DSBGA LP3987ITLX-2.85/NOPB LP3987ITLX-3.0/NOPB 1.09 1.55 0.76 4.0 8.0 Q1 8.4 1.09 1.55 0.76 4.0 8.0 Q1 8.4 1.09 1.55 0.76 4.0 8.0 Q1 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3987ITL-2.5/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3987ITL-2.6/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3987ITL-2.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3987ITL-2.85/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3987ITL-3.0/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3987ITLX-2.5/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3987ITLX-2.6/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3987ITLX-2.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3987ITLX-2.85/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3987ITLX-3.0/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0005xxx D 0.600±0.075 E TLA05XXX (Rev C) D: Max = 1.502 mm, Min =1.441 mm E: Max = 1.045 mm, Min =0.984 mm 4215043/A NOTES: A. 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