NEC UPD16488AW

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16488A
1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
DESCRIPTION
The µPD16488A is a controller/driver which includes display RAM for full-dot LCDs that can provide a four-level gray
scale display. This IC is able to drive full-dot LCDs that contain up to 128 x 92 dots.
FEATURES
• LCD controller/driver with on-chip display RAM
• Full dot outputs: 128 segment outputs and 92 common outputs
• Can operate using single power supply (logic system) in range from 1.7 to 3.6 V.
• Selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width
modulation)
• Serial data input and 8-bit parallel data input (i80 series interface and M68 series interface)
• Dot display RAM: 128 x 128 x 2 bits
• On-chip booster: Switchable from x2 to x9 modes
• Selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display)
• Duty settings: 1/92 to 1/1 duty
• On-chip voltage divider resistor
• On-chip oscillator
ORDERING INFORMATION
Part Number
Package
µPD16488AP
Chip
µPD16488AW
Wafer
Remark Purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15745EJ2V0DS00 (2nd Edition)
Date Published December 2001 NS CP(K)
The mark  shows major revised points.
2001
µPD16488A
TABLE OF CONTENTS
1. BLOCK DIAGRAM....................................................................................................................................... 5
2. PIN CONFIGURATION (PAD LAYOUT) ..................................................................................................... 6
3. PIN FUNCTIONS.......................................................................................................................................... 9
3.1 Power Supply System Pins ................................................................................................................................ 9
3.2 Logic System Pins ............................................................................................................................................ 10
3.3 Driver-Related Pins........................................................................................................................................... 13
3.4 Test Pins........................................................................................................................................................... 13
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS...................................... 14
5. DESCRIPTION OF FUNCTIONS............................................................................................................... 15
5.1 CPU Interface .................................................................................................................................................... 15
5.1.1
Selection of interface type ...................................................................................................................... 15
5.1.2
Parallel interface..................................................................................................................................... 15
5.1.3
Serial interface........................................................................................................................................ 16
5.1.4
Chip select.............................................................................................................................................. 16
5.1.5
Display data RAM and on-chip register access ...................................................................................... 16
5.2 Display Data RAM ............................................................................................................................................. 19
5.2.1
Display data RAM................................................................................................................................... 19
5.2.2
X address circuit ..................................................................................................................................... 19
5.2.3
Column address circuit ........................................................................................................................... 21
5.2.4
Y address circuit ..................................................................................................................................... 21
5.2.5
Common scan circuit .............................................................................................................................. 21
5.2.6
Display start line set ............................................................................................................................... 21
5.2.7
Display data latch circuit ......................................................................................................................... 21
5.3 Blink/Reverse Display Circuit.......................................................................................................................... 22
5.4 Oscillator........................................................................................................................................................... 24
5.5 Display Timing Generator................................................................................................................................ 28
5.6 Power Supply Circuit ....................................................................................................................................... 30
5.6.1
Booster ................................................................................................................................................... 30
5.6.2
Voltage regulator .................................................................................................................................... 32
5.6.3
Use of op amp for level power supply control ......................................................................................... 35
5.6.4
Application examples of power supply circuits........................................................................................ 36
5.7 LCD Display Drivers ......................................................................................................................................... 39
2
5.7.1
Full-dot pulse width modulation .............................................................................................................. 39
5.7.2
Full-dot frame rate control....................................................................................................................... 44
Data Sheet S15745EJ2V0DS
µPD16488A
5.7.3
Line shift driver ....................................................................................................................................... 45
5.7.4
Display size settings ............................................................................................................................... 47
5.7.5
Setting of LCD AC driver's inversion cycle and AC driver's inversion position........................................ 47
5.8 Display Modes .................................................................................................................................................. 49
5.8.1
Partial display mode ............................................................................................................................... 49
5.8.2
Monochrome (black/white) display ......................................................................................................... 51
5.9 Reset.................................................................................................................................................................. 53
6. COMMAND REGISTERS........................................................................................................................... 54
6.1 Control Register 1 (R0)...................................................................................................................................... 55
6.2 Control Register 2 (R1)...................................................................................................................................... 56
6.3 Reset Command (R2)......................................................................................................................................... 57
6.4 X Address Register (R3).................................................................................................................................... 57
6.5 Y Address Register (R4).................................................................................................................................... 57
6.6 Duty Setting Register (R5) ................................................................................................................................ 58
6.7 AC Driver Inversion Cycle Register (R6).......................................................................................................... 59
6.8 AC Driver Inversion Position Shift Register (R7) ............................................................................................ 59
6.9 Partial AC Driver Inversion Cycle Register (R8).............................................................................................. 60
6.10 Partial AC Driver Inversion Position Shift Register (R9) .............................................................................. 60
6.11 Partial Display Mode Setting Register (R10) ................................................................................................. 61
6.12 Display Memory Access Register (R11)......................................................................................................... 61
6.13 Display Start Line Setting Register (R12) ...................................................................................................... 62
6.14 Blink X Address Register (R13) ...................................................................................................................... 62
6.15 Blink Start Line Address Register (R14) ........................................................................................................ 62
6.16 Blink End Line Address Register (R15) ......................................................................................................... 62
6.17 Blink Data Memory Access Register (R16).................................................................................................... 63
6.18 Inverted X Address Register (R17) ................................................................................................................. 63
6.19 Inversion Start Line Address Register (R18) ................................................................................................. 63
6.20 Inversion End Line Address Register (R19) .................................................................................................. 64
6.21 Inverted Data Memory (R20)............................................................................................................................ 64
6.22 Partial Start Line Address Register (R21)...................................................................................................... 64
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26) .............................................................................................. 65
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30) .................................................................................. 65
6.25 Power System Control Register 1 (R32) ........................................................................................................ 66
6.26 Power System Control Register 2 (R33) ........................................................................................................ 67
6.27 Power System Control Register 3 (R34) ........................................................................................................ 68
6.28 Electronic Volume Register (R35) .................................................................................................................. 69
6.29 Partial Electronic Volume Register (R36) ...................................................................................................... 69
6.30 Boost Adjustment Register (R37)................................................................................................................... 69
6.31 RAM Test Mode Setting Register (R44).......................................................................................................... 70
6.32 Signature Read Register (R45) ....................................................................................................................... 70
Data Sheet S15745EJ2V0DS
3
µPD16488A
7. LIST OF µPD16488A REGISTERS ........................................................................................................... 71
8. POWER SUPPLY SEQUENCE ................................................................................................................. 72
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON → Display ON) .................. 72
8.2 Power OFF Sequence (When Using On-Chip Power Supply) ........................................................................ 73
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON) ................... 73
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply) ................................................ 74
8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF) ............................................................................... 75
9. USE OF RAM TEST MODE ....................................................................................................................... 76
10. ELECTRICAL SPECIFICATIONS............................................................................................................ 77
11. CPU INTERFACE (REFERENCE EXAMPLE) ........................................................................................ 87
4
Data Sheet S15745EJ2V0DS
µPD16488A

1. BLOCK DIAGRAM
SEG128
SEG1
COM1
COM92
Common driver
Segment driver
Data
register
/RES
/CS1
CS2
C86
PSX
/RD(E)
/WR(R,/W)
D7(SI)
D6(SCL)
D5 to D0
RS
M/S
FR
FRSYNC
DOF
SIGIN1
SIGIN2
TSTIFS
TSTRTST
TSTVIHL
TESTOUT
OSCIN1
OSCIN2
OSCOUT
OSCSYNC
CLS
Segment
G/S and blink
control
Display data latch
Common
timing
generator
Display data RAM
(128 x 128 x 2 bits)
I/O
buffer
Address decoder
Command decoder
Register
Segment
G/S and blink
timer
Timing generator
Oscillator
circuit
D/A converter
C1 , C1
+
DC/DC
converter
Op amp
LCD voltage generator
+
C9 , C9
C1A
VOUT
VRS
IRS
VR
AMPOUTP AMPOUT
VLCD
VLC1
VLC2
VLC3
VLC4
VDD1 VDD2 VSS
Remark /xxx indicates active low signals.
Data Sheet S15745EJ2V0DS
5
µPD16488A
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size
: 3.0 x 11.4 mm2
Chip
: 485 µm TYP.
403
372
A1
A4
1
371
Pad type A
: Pad size (AI) : 53 x 73 µm2
Bump size
: 45 x 60 µm2
Bump height : 17 µm TYP.
Pad type B
: Pad size (AI) : 118 x 73 µm2
Bump size : 110 x 60 µm2
Bump height : 17 µm TYP.
Alignment Mark Coordinate
Mark Center Coordinate
X [µm]
Y [µm]
M1
−1200.00
5300.00
M2
−1200.00
−5300.00
M3
1275.00
−5475.00
M4
1275.00
5475.00
Shape of Alignment Mark (unit: µm)
A1,A2
Y
50
A3
A4
50
163
197
A3
A1
164
6
196
Data Sheet S15745EJ2V0DS
50
100
50
100
100
50
X
100

50
100
100
µPD16488A
•　µPD16488A Pad Layout (1/2)
Pad
No.
Pin Name
Pad
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VSS
VRS
VRS
AMPOUTP
AMPOUTP
AMPOUT
AMPOUT
VR
VR
VLC4
VLC4
VLC3
VLC3
VLC2
VLC2
VLC1
VLC1
VLCD
VLCD
VSS
VOUT
VOUT
VSS
C9C9C9+
C9+
C8C8C8+
C8+
C7C7C7+
C7+
C6C6C6+
C6+
C5C5C5+
C5+
C4C4C4+
C4+
C3C3C3+
C3+
C2C2C2+
C2+
C1C1C1+
C1+
C1A
C1A
VDD2
VDD2
VDD2
VDD1
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
Y [µ m]
X [µ m]
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
5284.00
5154.00
5024.00
4894.00
4796.50
4590.00
4530.00
4470.00
4410.00
4350.00
4290.00
4230.00
4170.00
4110.00
4050.00
3990.00
3930.00
3870.00
3810.00
3750.00
3690.00
3630.00
3570.00
3510.00
3450.00
3390.00
3330.00
3270.00
3210.00
3150.00
3090.00
3030.00
2970.00
2910.00
2850.00
2790.00
2730.00
2670.00
2610.00
2550.00
2490.00
2430.00
2370.00
2310.00
2250.00
2190.00
2130.00
2070.00
2010.00
1950.00
1890.00
1830.00
1770.00
1710.00
1650.00
1590.00
1530.00
1470.00
1410.00
1350.00
1290.00
1230.00
1170.00
1110.00
1050.00
990.00
930.00
870.00
810.00
750.00
Pad
No.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Pin Name
Pad
Type
VDD1
VDD1
VSS
VSS
VSS
CLS
CLS
VDD1
M/S
M/S
VSS
C86
C86
PSX
PSX
VDD1
IRS
IRS
VSS
/CS1
/CS1
CS2
CS2
VDD1
/RES
/RES
RS
RS
VSS
/WR (R,/W )
/WR (R,/W )
/RD (E)
/RD (E)
VDD1
D7
D7
D6
D6
DUMMY
D5
D5
D4
D4
DUMMY
D3
D3
D2
D2
DUMMY
D1
D1
D0
D0
DUMMY
FRSYNC
FRSYNC
FR
FR
DUMMY
DOF
DOF
OSCIN1
OSCIN1
OSCIN2
OSCIN2
OSCOUT
OSCOUT
DUMMY
OSCSYNC
OSCSYNC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
X [µ m]
Y [µ m]
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
Data Sheet S15745EJ2V0DS
690.00
630.00
570.00
510.00
450.00
390.00
330.00
270.00
210.00
150.00
90.00
30.00
-30.00
-90.00
-150.00
-210.00
-270.00
-330.00
-390.00
-450.00
-510.00
-570.00
-630.00
-690.00
-750.00
-810.00
-870.00
-930.00
-990.00
-1050.00
-1110.00
-1170.00
-1230.00
-1290.00
-1350.00
-1410.00
-1470.00
-1530.00
-1590.00
-1650.00
-1710.00
-1770.00
-1830.00
-1890.00
-1950.00
-2010.00
-2070.00
-2130.00
-2190.00
-2250.00
-2310.00
-2370.00
-2430.00
-2490.00
-2550.00
-2610.00
-2670.00
-2730.00
-2790.00
-2850.00
-2910.00
-2970.00
-3030.00
-3090.00
-3150.00
-3210.00
-3270.00
-3330.00
-3390.00
-3450.00
Pad
No.
Pin Name
Pad
Type
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
DUMMY
DUMMY
VSS
SIGIN1
SIGIN1
VDD1
SIGIN2
SIGIN2
VSS
TESTOUT
TESTOUT
TSTIFS
TSTIFS
TSTRTST
TSTRTST
TSTVIHL
TSTVIHL
VSS
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
X [µ m]
Y [µ m]
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1172.50
-1075.00
-965.00
-905.00
-845.00
-785.00
-725.00
-665.00
-605.00
-545.00
-485.00
-425.00
-365.00
-305.00
-245.00
-185.00
-125.00
-65.00
-5.00
55.00
115.00
175.00
235.00
295.00
355.00
415.00
475.00
535.00
595.00
655.00
771.00
906.00
1041.00
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
-3510.00
-3570.00
-3630.00
-3690.00
-3750.00
-3810.00
-3870.00
-3930.00
-3990.00
-4050.00
-4110.00
-4170.00
-4230.00
-4290.00
-4350.00
-4410.00
-4470.00
-4530.00
-4796.50
-4894.00
-5024.00
-5154.00
-5284.00
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5257.50
-5160.00
-5100.00
-5040.00
-4980.00
-4920.00
-4860.00
-4800.00
-4740.00
-4680.00
-4620.00
-4560.00
-4500.00
-4440.00
7
µPD16488A
•　µPD16488A Pad Layout (2/2)
Pad
No.
Pin Name
Pad
Type
Pad Coordinate
Y [µ m]
X [µ m]
Pad
No.
Pin Name
Pad
Type
Pad Coordinate
X [µ m]
Y [µ m]
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
DUMMY
SEG128
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
-4380.00
-4320.00
-4260.00
-4200.00
-4140.00
-4080.00
-4020.00
-3960.00
-3900.00
-3840.00
-3780.00
-3720.00
-3660.00
-3600.00
-3540.00
-3480.00
-3420.00
-3360.00
-3300.00
-3240.00
-3180.00
-3120.00
-3060.00
-3000.00
-2940.00
-2880.00
-2820.00
-2760.00
-2700.00
-2640.00
-2580.00
-2520.00
-2460.00
-2400.00
-2340.00
-2280.00
-2220.00
-2160.00
-2100.00
-2040.00
-1980.00
-1920.00
-1860.00
-1800.00
-1740.00
-1680.00
-1620.00
-1560.00
-1500.00
-1440.00
-1380.00
-1320.00
-1260.00
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
-180.00
-120.00
-60.00
0.00
60.00
120.00
180.00
240.00
300.00
360.00
420.00
480.00
540.00
600.00
660.00
720.00
780.00
840.00
900.00
960.00
1020.00
1080.00
1140.00
1200.00
1260.00
1320.00
1380.00
1440.00
1500.00
1560.00
1620.00
1680.00
1740.00
1800.00
1860.00
1920.00
1980.00
2040.00
2100.00
2160.00
2220.00
2280.00
2340.00
2400.00
2460.00
2520.00
2580.00
2640.00
2700.00
2760.00
2820.00
2880.00
2940.00
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
-1200.00
-1140.00
-1080.00
-1020.00
-960.00
-900.00
-840.00
-780.00
-720.00
-660.00
-600.00
-540.00
-480.00
-420.00
-360.00
-300.00
-240.00
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
DUMMY
DUMMY
COM46
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
3000.00
3060.00
3120.00
3180.00
3240.00
3300.00
3360.00
3420.00
3480.00
3540.00
3600.00
3660.00
3720.00
3780.00
3840.00
3900.00
3960.00
8
Data Sheet S15745EJ2V0DS
Pad
No.
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
Pin Name
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DUMMY
DUMMY
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
Pad Coordinate
X [µ m]
Y [µ m]
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1041.00
906.00
771.00
595.00
535.00
475.00
415.00
355.00
295.00
235.00
175.00
115.00
55.00
-5.00
-65.00
-125.00
-185.00
-245.00
-305.00
-365.00
-425.00
-485.00
-545.00
-605.00
-665.00
-725.00
-785.00
-845.00
-905.00
-965.00
-1075.00
-1172.50
4020.00
4080.00
4140.00
4200.00
4260.00
4320.00
4380.00
4440.00
4500.00
4560.00
4620.00
4680.00
4740.00
4800.00
4860.00
4920.00
4980.00
5040.00
5100.00
5160.00
5257.50
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
µPD16488A
3. PIN FUNCTIONS
3.1
Power Supply System Pins
Symbol
VDD1
Name
Pad No.
I/O
Logic power supply
70-72, 78, 86, 94,
−
Power supply pin for logic circuit
67-69
−
Power supply pin for booster
Logic and driver
6, 25, 28, 73 to 75, 81,
−
Ground pin for logic and driver circuits
ground pin
89, 99, 143, 149, 158
−
Power supply pin for driver. Output pin for on-chip booster.
pin
VDD2
Boost circuit
Description
104, 146
power supply pin
VSS
VOUT
Driver power
26, 27
Connect a 1 µF boost capacitor between this pin and the GND
supply pin
pin.
If not using the on-chip booster, a direct driver power supply can
be input.
VLCD,
Reference power
24, 23,
VLC1 to VLC4
supply pins for
22 to 15
−
These are reference power supply pins for the LCD driver.
Connect a capacitor between these pins and the GND pin if an
internal bias has been selected.
driver
C1+, C1−
Boost capacitor
64, 63, 62, 61
C2+, C2−
connection pins (1)
−
These are capacitor connection pins for the booster. When
60, 59, 58, 57
using the on-chip booster, connect a 1 µF capacitor between
−
C3 , C3
56, 55, 54, 53
positive (+) and negative (-) pins.
C4+, C4−
52, 51, 50, 49
C5+, C5−
48, 47, 46, 45
C6+, C6−
44, 43, 42, 41
+
+
−
C7 , C7
40, 39, 38, 37
C8+, C8−
36, 35, 34, 33
C9+, C9−
32, 31, 30, 29
C1A
Boost capacitor
connection pin (2)
65, 66
−
This is a capacitor connection pin for boost adjustment. When
using the on-chip booster, connect a 1 µF capacitor between
this pin and the GND pin.
Data Sheet S15745EJ2V0DS
9
µPD16488A
3.2
Logic System Pins
(1/3)
Symbol
PSX
Name
Data transfer
Pad No.
I/O
Description
84, 85
Input
This pin is used to select between parallel data input and serial
selection
data input.
PSX = H: Parallel data input
PSX = L: Serial data input
/CS1,
Chip select
CS2
90, 91,
Input
92, 93
These pins are used for chip select signals. When /CS1 = L
(CS2 = H), the chip is active and can perform data input/output
operations including command and data I/O.
/RD
Read
(E)
(enable)
102, 103
Input
When i80 series parallel data transfer (/RD) has been selected,
the signal at this pin is used to enable read operations. Data is
output to the data bus only when this pin is L.
When M68 series parallel data transfer (E) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the falling edge of this signal.
/WR
Write
(R,/W)
(read/write)
100, 101
Input
When i80 series parallel data transfer (/WR) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the rising edge of this signal.
When 68 series parallel data transfer (R,/W) has been selected,
this pin is used to determine the direction of data transfer.
L: Write
H: Read
C86
Interface selection
82, 83
Input
This pin is used to switch between interface modes (i80 series
CPU or M68 series CPU).
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
D0 to D5,
Data bus
D6 (SCL)
(serial clock)
115 to 118,
connects to an 8-bit or 16-bit standard CPU bus.
D7 (SI)
(serial input)
120 to 123
When the serial interface has been selected (PSX = L), D6
105 to 108, 110 to 113,
I/O
These pins comprise an 8-bit bidirectional data bus that
functions as a serial clock input pin (SCL) and D7 functions as a
serial data input pin (SI). In either case, pins D0 to D5 are in
high impedance mode.
When the chip is not selected, D0 to D7 are in high impedance
mode.
RS
Index
97, 98
Input
Usually, this pin is connected to the LSB of the standard CPU
register/data,
address bus and is used to distinguish between data from index
command
registers and data/commands.
selection
RS = H: Indicates that data from D0 to D7 is data/command
RS = L : Indicates that data from D0 to D7 is index register
contents
/RES
Reset
95, 96
Input
When /RES is low, an internal reset is performed. The reset
operation is executed at the /RES signal level.
10
Data Sheet S15745EJ2V0DS
µPD16488A
(2/3)
Symbol
CLS
Name
Select clock
Pad No.
I/O
Description
76, 77
Input
This pin is used to select whether or not to use the divider within
division
the display clock oscillator.
CLS = H: Use divider
CLS = L: Do not use divider
When using an external clock, the CLS = L setting is input via
the OSCIN1 and OSCIN2 pins as normal and partial clocks
respectively.
When CLS = H, clock input is via the OSCIN1 pin only.
FR
Frame signal
127, 128
I/O
This pin is used as I/O pin for the LCD's AC conversion signal.
M/S = H: Output
M/S = L: Input
When using the µPD16488A in master/slave mode, both FR
pins must be connected.
FRSYNC
Frame
125, 126
I/O
This pin is used as I/O pin for the LCD's AC conversion
synchronization
synchronization signal.
signal
M/S = H: Output
M/S = L: Input
When the µPD16488A is used in master/slave mode, both
FRSYNC pins must be connected.
DOF
Display blink
130, 131
I/O
This pin is used to control the LCD's display blink function.
M/S = H: Output
M/S = L: Input
When the µPD16488A is used in master/slave mode, both DOF
pins must be connected.
M/S
Master/slave
79, 80
Input
This pin is used to select between master and slave operation
modes. In master operation mode, it outputs the timing signal
required by the LCD driver and in slave operation mode it inputs
this timing signal from an external source for use in LCD display
synchronization.
M/S = H: Master operation mode
M/S = L: Slave operation mode
Settings dependent on the M/S mode are listed in the following
chart.
Power
supply circuit
FR
FRSYNC
DOF
H
Valid
Output
Output
Output
L
Invalid
Input
Input
Input
M/S
IRS
VLCD regulation
87, 88
Input
This pin is used to select the resistor that is used for VLCD
voltage regulation.
IRS = H: Uses internal resistor
IRS = L: Does not use internal resistor. The VLCD voltage level
is regulated using the external voltage division resistor that is
connected to the VR pin.

This pin is valid only in master operation mode. In slave
operation mode, this pin is fixed high or low level.
SIGIN1,
Signature setting
144, 145,
SIGIN2
pins
147, 148
Input
These pins can be used to set a unique signature for the IC. The
signal set via these pins can subsequently be read from the
signature read register (R45).
Data Sheet S15745EJ2V0DS
11
µPD16488A
(3/3)
Symbol
OSCIN1
Name
Oscillation signal
Pad No.
I/O
132, 133
Input
pins
OSCIN2
Description
A resistor can be inserted between OSCIN1-OSCOUT, and
OSCIN2-OSCOUT. When using an external oscillator, a clock
134, 135
Input
signal is input via the OSCIN pins according to the CLS pin's
status and the OSCOUT pin is left unconnected.
OSCOUT
136, 137
Output
The wiring between OSCIN1-OSCOUT and OSCIN2-OSCOUT must
139, 140
Output
Display clock output pin.
be as short as possible, and use after proper evaluation.
OSCSYNC
Display clock
output
See 5. 4 Oscillator concerning use or this pin when the
µPD16488A is in master or slave operation mode.
12
Data Sheet S15745EJ2V0DS
µPD16488A
3.3
Driver-Related Pins
Symbol
SEG1 to
Pad No.
I/O
Segment
Name
347-220
Output
Segment output pins
Description
Common
166 to 192, 200 to 218,
Output
Common output pins
Input
VRS is an op amp input pin for regulating the driving voltage of
SEG128
COM1 to
COM92
350 to 368, 375 to 401
VRS
Op amp input pin
7, 8
for regulating the
the LCD. This is a reference voltage input for the LCD voltage
driving voltage of
regulation amplifier.
the LCD
When using the internal drive circuit (i.e., when OP1 = 1), we
recommend inserting a 0.1 to 1 µF capacitor between this pin
and GND.
VR
Input pin for the op
13, 14
Input
VR is an input for the op amp's feedback connection. Insert this
amp's feedback
pin between GND and AMPOUT when using the feedback resistor
connection
for this input.
This pin is valid only when not using an internal resistor for VLCD
voltage regulation (i.e., when IRS = L). This pin cannot be used
when using the internal resistor for VLCD voltage regulation (i.e.,
when IRS = H).
AMPOUT
Op amp output
9, 10
Output
These are op amp output pins for regulating the driving voltage
of the LCD. When not using an internal resistor for VLCD voltage
regulation (i.e., when IRS = L), these outputs are connected to
AMPOUTP
the LCD drive voltage regulation resistor (see 5.6.2 Voltage
11, 12
regulator).
We recommend inserting a 0.01 to 0.1 µF capacitor between
these pins in order to stabilize the internal op amp's output.
DUMMY
Dummy pin
1 to 5, 109, 114, 119,
−
124, 129, 138, 141,
Dummy pin.
These pins are not connected inside IC. Usually, leave these
142, 159 to 165,
pins open.
193 to 199, 219, 348,
349, 369 to 374, 402,
403
3.4
Test Pins
Symbol
TSTIFS
Name
Test input
I/O
152, 153,
Input
Description
These pins are used to set a test mode for the IC.
Normally, connect these pins to VSS.
154, 155,
TSTRTST
156, 157
TSTVIHL
TESTOUT
Pad No.
Test output
150, 151
Output
These pins are used when the IC is in test mode.
Usually, leave them open.
Data Sheet S15745EJ2V0DS
13
µPD16488A
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are described below.
Pin Name
Input Type
Input/output
Recommended Connection of Unused Pins
Notes
PSX
Schmitt trigger
Input
Mode setting pin.
Note 1
/CS1
Filter
Input
Connect to VSS.
−
CS2
Filter
Input
Connect to VDD1.
−
/RD(E)
Filter
Input
Connect to VDD1 (i80 series interface), connect to VDD1
−
or VSS (serial interface).
/WR(R,/W)
Filter
Input
C86
Schmitt trigger
D0 to D5
Filter
Input
Input/output
Connect to VDD1 or VSS (serial interface).
Mode setting pin.
−
Note 1
−
Leave open
D6(SCL)
Filter
Input/output
−
D7(SI)
Filter
Input/output
−
−
RS
Filter
Input
Register setting pin.
/RES
Schmitt trigger
Input
Connect to VDD1.
−
CLS
Schmitt trigger
Input
Mode setting pin
Note 1
FR
CMOS
Input/output
Leave open (using master mode, M/S = H).
−
FRSYNC
CMOS
Input/output
Leave open (using master mode, M/S = H).
−
DOF
CMOS
Input/output
Leave open (using master mode, M/S = H).
M/S
Schmitt trigger
Input
Mode setting pin.
Note 1
IRS
Schmitt trigger
Input
Mode setting pin.
Note 1
SIGIN1
Schmitt trigger
Input
Connect to VDD1 or VSS.
−
SIGIN2
Schmitt trigger
Input
Connect to VDD1 or VSS.
−
OSCIN1
Schmitt trigger
Input
OSCIN2
Schmitt trigger
Input
−
Note 2
−
−
−
Connect to VDD1 or VSS (CLS = H)
−
OSCOUT
−
Output
Leave open (when using external clock)
−
OSCSYNC
−
Output
Leave open
−
TSTIFS
Schmitt trigger
Input
Connect to VSS (during normal use)
−
TSTRTST
Schmitt trigger
Input
Connect to VSS (during normal use)
−
TSTVIHL
Schmitt trigger
Input
Connect to VSS (during normal use)
−
TESTOUT
－
Output
Leave open
Notes 1. Connect to either VDD1 or VSS, depending on the mode setting.
2. Input either VDD1 or VSS output from CPU, depending on the mode setting.
14
Data Sheet S15745EJ2V0DS
µPD16488A
5. DESCRIPTION OF FUNCTIONS
5.1
CPU Interface
5.1.1 Selection of interface type
The µPD16488A chip transfers data using an 8-bit bidirectional data bus (D7 to D0) or a serial data input (SI). Setting the
polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the
following table.
PSX
H: Parallel input
L: Serial input
CS
RS
/RD
/WR
C86
D7
D6
CS
RS
/RD
/WR
C86
D7
D6
D5 to D0
SCL
Hi-Z Note2
CS
RS
Note1 Note1 Note1
SI
D5 to D0
Notes 1. Fixed as either High or Low.
2. Hi-Z: High impedance
5.1.2 Parallel interface
When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection
to an i80 series or M68 series CPU (see table below).
C86
/CS1
CS2
RS
/RD
/WR
D7 to D0
H: M68 series CPU
/CS1
CS2
RS
E
R,/W
D7 to D0
L: i80 series CPU
/CS1
CS2
RS
/RD
/WR
D7 to D0
The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the
following table.

Common
M68
RS
R,/W
/RD
i80
/WR
Function
1
1
0
1
Reads display data and registers
1
0
1
0
Writes display data and registers
0
1
0
1
Prohibited
0
0
1
0
Writes to index register
Data Sheet S15745EJ2V0DS
15
µPD16488A
5.1.3 Serial interface
When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and
serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial
clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to
parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the
data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read
at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal
chart is shown below.
Figure 5-1. Serial Interface Signal Chart
CS2 = H
/CS1
SI
SCL
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RS
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.
2. The data read function is disabled during serial interface mode.
3. When using SCL wiring, take care concerning the possible effects of terminating reflection and
noise from external sources. We recommend checking operation with the actual device.
5.1.4 Chip select
The µPD16488A has two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only
when /CS1 = L and CS2 = H. When chip select is inactive, P0 to P7 are set to high impedance (invalid) and input of RS, /RD,
or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset.
5.1.5 Display data RAM and on-chip register access
Because only the required cycle time (tcyc) is satisfied when accessing the µPD16488A from the CPU, high-speed data
transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when
data is read, there is no need for dummy data except in the display memory access register (R11).
In other words, dummy data is required only when reading data from the display memory access register (R11).
Figure 5-2 illustrates this relationship.
16
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-2. Write and Read (1/2)
Write
<CPU>
/WR
DATA
N
N+1
<Internal timing>
N+2
N+3
Latch
BUS
holder
N
N+1
N+2
N+3
Write
signal
Read (display memory access register (R11))
<CPU>
/WR
/RD
DATA
N
n
N
n+1
<Internal timing>
Address
preset
Read
signal
Column
address
Preset N
BUS
holder
n
N
Address set
#n
N+2
Increment N + 1
Dummy read
Data Sheet S15745EJ2V0DS
n+1
Data read
#n
n+2
Data read
#n + 1
17
µPD16488A
Figure 5-2. Write and Read (2/2)
Read (other than display memory access register)
<CPU>
/WR
/RD
DATA
IRn
IR address
set #n
18
IRn data
IRn register
data read
IRn+1
IR address
set #n + 1
Data Sheet S15745EJ2V0DS
IRn + 1
Data
IRn + 1 register
data read
µPD16488A
5.2
Display Data RAM
5.2.1 Display data RAM
This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits (32 x 8 bits) x 128 bits. Any
specified bit can be accessed by selecting the corresponding X address and Y address. D0 to D7 are the display data sent
from the CPU, and correspond to SEGx on the LCD display (see Figure 5-3).
The CPU writes data to and reads data from the display RAM via the I/O buffer, and these read/write operations are
independent of the signal read operations for the LCD driver. Accordingly, there are no adverse effects (such as flicker) in
the LCD display when display data RAM is accessed asynchronously.
Figure 5-3. Display Data RAM
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
Pixel 3
D0
Pixel 1
Pixel 2
Pixel 4
LCD panel
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 1
Pixel 2
Pixel 3
Pixel 4
X address 00H
X address 01H
SEG1 SEG2
D7 D6 D5 D4
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
COM0
COM1
COM2
COM3
COM4
Display data
LCD display
5.2.2 X address circuit
As shown in Figure 5-4, the display data RAM's X address is specified via the X address register (R3). When using X
address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is
incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set
back to 00H.
For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is
incremented after each read or write operation and the X address is set back to 00H.
Data Sheet S15745EJ2V0DS
19
µPD16488A
D4
D3
D2
D1
0
0
0
0
1
01H
0
0
0
0
0
00H
D0
1
1
1
1
1
1FH
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
COM output
Yaddress
D7 D6 D5 D4 D3 D2 D1 D0
COM1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
Start
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
92-line
COM83
COM84
COM85
COM86
COM87
COM88
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
COM89
COM90
COM91
COM92
20
Column
Address
D0
ADC
D0
78H 07H
SEG8
0
79H 06H
SEG7
1
7AH 05H
SEG6
LCD
output
7BH 04H
SEG5
SEG128 00H 7FH
7CH 03H
SEG4
Data Sheet S15745EJ2V0DS
SEG127 01H 7EH
7DH 02H
SEG3
SEG126 02H 7DH
7EH 01H
SEG2
SEG125 03H 7CH
7FH 00H
7FH
SEG1
X address
Figure 5-4. Configuration of X Address Register
µPD16488A
5.2.3 Column address circuit
When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in
Figure 5-4.
As is shown in Table 5-1, the correspondence between the display RAM's column address and segment output can be
inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the constraints
on chip layout when assembling the LCD module.
Table 5-1. Relationship between Column Address and SEG Output
SEG Output
SEG1
SEG128
ADC
0
00H
→
Column address
→
7FH
(D1)
1
7FH
←
Column address
←
00H
5.2.4 Y address circuit
As is shown in Figure 5-4, the Y address register (R4) is used to specify the display data RAM's Y address. When using
Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address
is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set
back to 00H.
5.2.5 Common scan circuit
The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control
register 1 (R0), as shown in Table 5-2.
For example, when using 1/80 duty, when COMR = L the scan direction is COM1 → COM80 and when COMR = H,
the scan direction is COM80 → COM1 using the COM80 to COM1 pins.

Table 5-2. Relationship between Common Scan Circuit and Scan Direction
COMR
0
COM1
→
COM92
(D0)
1
COM92
→
COM1
5.2.6 Display start line set
As is shown in Figure 5-4, display start line set specifies the Y address that corresponds to the COM1 output for displaying
the contents of display data RAM. The display start line setting register (R12) is used to specify the top line in the display.
The screen can be scrolled, overwritten, etc. A 7-bit display start address is set to the display start line setting register.
5.2.7 Display data latch circuit
The display data latch circuit is used for temporary storage of data that is output to the LCD driver from the display data RAM.
The display scan command that sets normal or reverse display mode and the display ON/OFF command control latched
data so that there is no effect on the data in the display data RAM.
Data Sheet S15745EJ2V0DS
21
µPD16488A
5.3
Blink/Reverse Display Circuit
The µPD16488A enables blinking display and reverse display in designated parts of the full dot display. A blinking display
is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at approximately 1 Hz and
reverse display is achieved by inverting the display level value.
The area designated for blinking is specified via the blink start/end line address registers (R14 and R15), the blink X
address register (R13), and the blink data memory access register (R16).
First, the blinking display's start and end line addresses are selected via the blink start/end line address registers. Next,
the blink X address register (R13) and the blink data memory (R16) are used to select the column for the blinking display.
The inversion start/end line address registers (R18 and R19), the inverted X address register (R17), and the inverted data
memory access register (R20) are used to select the reverse display area.
First, the inversion start/end line address registers (R18 and R19) are set to select the line addresses where the reverse
display will start and end. Next, the inverted X address register (R17) and the inverted data memory access register (R20)
are used to select the column for the reverse display. The specified blink/inverted X address is incremented (by 1) with
each input of blink/reverse display data.
The blink RAM and inversion RAM, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking
display and reverse display respectively. To access the desired bit, simply specify the corresponding X address. The
blink/reverse data (data bits D0 to D7 sent from the CPU) correspond to SEGx on the LCD display, as shown in Figure 5-5.
After the area and data settings are complete, the BLD bit and IVD bit in the control register 1 (R0) are set to H, at which
point the blinking and/or reverse display of data begins. Figure 5-6 illustrates the relationship between the start line address,
end line address, blink/reverse data, and LCD display.
Table 5-3. Inversion Manipulation and Display
Original Level
After Inversion
Four-level gray scale display mode
0, 0
1, 1
0, 1
1, 0
1, 0
0, 1
1, 1
0, 0
B/W display mode
1
0
0
1
D3
0
0
1
D2
0
0
1
D1
D0
0
0
1
0
00H
1
01H
1
0FH
22
Data Sheet S15745EJ2V0DS
Column
address
ADC
0
1
D0 D0
LCD
output
SEG128 00H 7FH
SEG127 01H 7EH
SEG126 02H 7DH
SEG125 03H 7CH
SEG124 04H 7BH
SEG123 05H 7AH
SEG122 08H 79H
D7 D6 D5 D4 D3 D2 D1 D0
SEG121 07H 78H
77H 08H
SEG9
SEG16 70H 0FH
78H 07H
SEG8
SEG15 71H 0EH
79H 06H
SEG7
SEG14 72H 0DH
7AH 05H
SEG6
SEG13 73H 0CH
7BH 04H
SEG5
SEG12 74H 0BH
7CH 03H
SEG4
SEG11 75H 0AH
7DH 02H
SEG3
SEG10 76H 09H
7FH 00H
7EH 01H
SEG2
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SEG1
X address
Figure 5-5. Correspondence Between Blink/Reverse Data and Segments
µPD16488A
Figure 5-6. Setting Image of Blink/Reverse Display Area
Blink/revese
data
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
001 100 10 00 10 01 10 00 01 01 00 00 10 01 10 0 001 01 00 0 011 00 10 0 011 0010 0 001 0100
Start line
End line
Blinking or reverse display pixels.
Example of sequence for setting blink/reverse display
Start
Blink/inversion start line
address register
Blink/inversion end line
address register
Blink/inverted
X address register
Blink/inverted
data memory access register
Data
Write completed ?
No
Yes
Control register 1
(BLD, IVD = H)
End
Data Sheet S15745EJ2V0DS
23
µPD16488A
5.4
Oscillator
The µPD16488A include a CR-type oscillator (R external) for normal and partial display, which generates the display
clocks.
The clocks from this oscillator are controlled via the CLS pin and the DTY flag in the control register 2 (R1). The clock
configuration for the display can be set to suit the target system.
The functions of this circuit are described below.
•The oscillator for normal and partial display is enabled only when resistors RN and RP have been connected.
The DTY flag in the control register 2 (R1) and the CLS pin status are used to switch between the oscillation
clocks for normal display and partial display modes.
•The divider divides the external clock that has been input for the normal oscillator and the normal display into a
clock for partial display. The external clock that is input for the partial oscillator and partial display is also
divided for the partial display.
•The division level is automatically set for the divider based on the relationship between the ON/OFF status of
the divider setting pin (CLS pin) and the duty of the specified partial display, as shown in Table 5-4.
Figure 5-7. Oscillator Block
Selected via DTY/CLS
OSCIN1
OSCIN2
Normal display/
partial display
oscillator
Signal to select division level
for partial display
OSCOUT
MUX
TOSCSYNC
To graphic driver
Partial display
divider
Normal/partial signal
CLS
The relationship between the frame frequency (fFRAME), oscillation frequency (fOSCIN1), and setting duty (in normal display
mode) is described below.
fFRAME = fOSCIN1 ÷ 8 ÷ N (in four-level gray scale display mode)
fFRAME = fOSCIN1 ÷ 4 ÷ N (in B/W display mode)
N = 1/N duty (setting duty)
24
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-4. Setting of Division Level for Partial Display and Static Icon Display
In four-level gray scale display mode (GRAY = L, control register 2 (R1))
Display
Mode
Normal
Display
Duty Ratio
1/1 to 1/80
Partial
Display
Duty Ratio
Division
Source
OSCIN1
/OSCIN2
1/38
1/25
1/12
1/38
1/25
1/12
OSCIN1
Divider
Normal/Partial
ON/OFF
Select DTY
CLS
L (Normal)
OSCIN2
L(OFF)
H (Partial)
1/38
Four-level
gray scale
GRAY = L
OSCIN1
H(ON)
1/12
1/38
1/25
1/12
1/38
1/25
1/12
1/81 to 1/92
OSCIN1
L (Normal)
Partial frame frequency: fOSCIN2 /8 /38
1/1
Partial frame frequency: fOSCIN2 /8 /25
1/2
Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12
1/2
Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38
1/2
Partial frame frequency: fOSCIN1 /2(division ratio) /8 /25
1/4
Partial frame frequency: fOSCIN1 /4(division ratio) /8 /12
−
H(ON)
OSCIN2
L(OFF)
1/12
H (Partial)
1/38
1/25
1/1
L(OFF)
1/38
1/25
−
H(ON)
1/12
1/25
Comments
L(OFF)
1/38
1/25
Partial
Division
Ratio
OSCIN1
H(ON)
1/12
1/1
Partial frame frequency: fOSCIN2 /8 /38
1/1
Partial frame frequency: fOSCIN2 /8 /25
1/2
Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12
1/2
Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38
1/4
Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25
1/8
Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12
In black/white display mode (GRAY = H, control register 2 (R1))
Display
Mode
Normal
Display
Duty Ratio
Partial
Display
Duty Ratio
Division
Source
OSCIN1
/OSCIN2
Divider
Normal/Partial
ON/OFF
Select DTY
CLS
Partial
Division
Ratio
Comments
1/38
1/25
1/12
1/38
L(OFF)
L (Normal)
OSCIN1
1/25
−
H(ON)
1/12
1/1 to 1/80
1/38
1/25
OSCIN2
L(OFF)
1/12
H (Partial)
1/38
1/25
B/W
1/12
1/38
1/25
1/12
1/38
1/25
1/12
GRAY = H
1/81 to 1/92
OSCIN1
H(ON)
OSCIN1
L (Normal)
OSCIN2
L(OFF)
H (Partial)
1/38
1/25
1/1
Partial frame frequency: fOSCIN2 /4 /25
1/2
Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12
1/2
Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38
1/2
Partial frame frequency: fOSCIN1 /2(division ratio) /4 /25
1/4
Partial frame frequency: fOSCIN1 /4(division ratio) /4 /12
−
H(ON)
1/12
1/12
Partial frame frequency: fOSCIN2 /4 /38
L(OFF)
1/38
1/25
1/1
OSCIN1
H(ON)
1/1
Partial frame frequency: fOSCIN2 /4 /38
1/1
Partial frame frequency: fOSCIN2 /4 /25
1/2
Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12
1/2
Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38
1/4
Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25
1/8
Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12
Data Sheet S15745EJ2V0DS
25
µPD16488A
Table 5-5 shows the relationship between the CLS pin, resistors RN and RP, and the display clock circuit.
Table 5-5. Relationship between CLS Pin/Resistors and Display Clock Circuit
RN
Connection
RP
Connection
CLS
Clock for Normal Display
Clock for Partial Display
Use Example
(Figure 5-8)
Connected
Connected
L
Internal oscillator
Internal oscillator
(A)
Connected
Not connected
H
Internal oscillator
Divided from oscillator clock
(B)
Not connected
Connected
L
External clock
Internal oscillator
(C)
Not connected
Not connected
L
External clock
External clock
(D)
Not connected
Not connected
H
External clock
Divided from external clock
(E)
Figure 5-8. Clock Use Examples
(A)
(B)
OSCIN1
RN
OSCIN2
OSCIN1
H or L
RN
OSCIN2
RP
OSCOUT
OSCOUT
(D)
(C)
fN
fN
OSCIN1
OSCIN1
fP
OSCIN2
OSCIN2
RP
OSCOUT
(E)
fN
OSCIN1
H or L
Open
26
OSCIN2
OSCOUT
Data Sheet S15745EJ2V0DS
Open
OSCOUT
µPD16488A
Figure 5-9. Master/Slave Connection Examples
(A)
Master
Slave
(M/S = H)
(M/S = L, CLS = L)
OSCSYNC
OSCIN1
OSCIN2
Open
OSCOUT
(B)
Master
Slave
(M/S = H)
(M/S = L, CLS = H)
OSCIN1
OSCSYNC
H or L
OSCIN2
Open
OSCOUT
Data Sheet S15745EJ2V0DS
27
µPD16488A
5.5
Display Timing Generator
The display clock generates timing signals for the line address circuit and the display data latch circuit.
Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver
output pins.
Reading of the display data is completely independent of the CPU's accessing of the display data RAM. Consequently,
there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed
asynchronously in relation to the LCD contents.
The internal common timing is generated from the display clock. As shown in Figure 5-10, a driver waveform based on
the frame AC drive method is generated for the LCD driver.
If a multiple set of µPD16488A chips are used, the display timing signals (FR and FRSYNC) for the slave side must be
supplied from the master side.
Table 5-6. Relationship Between Operation Mode and FR, FRSYNC
28
Operation Mode
FR
FRSYNC
Master (M/S = H)
Output
Output
Slave (M/S = L)
Input
Input
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-10. Driver Waveform Based on Frame AC Drive Method
1frame
1 2 3 4 5 6 7 8
90 91 92
1 2 3 4 5 6 7 8
90 91 92
OSCSYNC
FRSYNC
FR
RAM
DATA
VLCD
VLC1
VLC2
SEG1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM2
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM92
VLC3
VLC4
VSS
Data Sheet S15745EJ2V0DS
29
µPD16488A
5.6
Power Supply Circuit
The power supply circuit supplies the voltage needed to drive the LCD. It includes a booster, voltage regulator, and
voltage follower.
In the power supply circuit, the power system control register 1 (R32) is used to control the ON/OFF status of the power
supply circuit's booster, voltage regulator (also called V regulator), and voltage follower (V/F). This makes it possible to
jointly use an external power supply together with certain functions of the on-chip power supply. Table 5-7 shows the
function that controls the 3-bit data in the power system control register 1 (R32) and Table 5-8 shows a reference chart of
combinations.
Table 5-7. Control Values of Bits in Power System Control 1
Status
Item
1
0
ON
OFF
OP2
Booster control bit
OP1
Voltage regulator (V regulator) control bit
ON
OFF
OP0
Voltage follower (V/F) control bit
ON
OFF
Table 5-8. Reference Chart of Combinations
Use Status
<1> Use on-chip power supply
OP2 OP1 OP0
1
1
1
Booster V Regulator
enable
V/F
External
Power Supply
Input
Boost-Related Note
System Pins
enable
enable
VDD2
Used
<2> Use V regulator and V/F only
0
1
1
disable
enable
enable
VOUT
Not connected
<3> Use V/F only
0
0
1
disable
disable
enable
VOUT, AMPOUT
Not connected
<4> Use external power supply only
0
0
0
disable
disable
disable
VOUT,
Not connected
VLCD to VLC4
Note The boost-related system pins are indicated as pins C1+, C1− to C9+, C9−, and C1A.
5.6.1 Booster
A booster that boosts the LCD driving voltage by 2 to 9 times is incorporated in the power supply circuit.
Since the booster uses signals from the on-chip oscillator, either the oscillator must be operating or a display clock must be
input from an external source.
The booster uses pins C1+, C1− to C9+, C9− for normal boost and pins C1A and VDD2 for boost regulation. The wire
impedance should be kept as low as possible. The number of boost levels is set using the FBS2, FBS1, and FBS0 flags in
the power system control 3 (R34), as shown in Table 5-9.
Caution If a capacitor is connected to a boost-related system pin that is not for one of these set boost levels,
current consumption may increase. Therefore, do not connect any capacitors beyond the number of
set boost levels. This also applies for the CA1 pin, used to regulate the boost levels.
Figure 5-11 describes the connection method for boost levels and capacitors.
The partial booster is settings are made using the BST1 and BST0 flags in the power system control 3 (R34), as shown in
Table 5-10.
30
Data Sheet S15745EJ2V0DS
µPD16488A
C2−
C3+
C3−
C4+
C4−
C5+
C5−
C6+
C6−
C7+
C7−
C8+
C8−
C9+
C9−
C1A
C2−
C3+
C3−
C4+
C4−
C5+
C5−
C6+
C6−
C7+
C7−
C8+
C8−
C9+
C9−
C1A
C2−
C3+
C3−
C4+
C4−
C5+
C5−
C6+
C6−
C7+
C7−
C8+
C8−
C9+
C2−
C3+
C3−
C4+
C4−
C5+
C5−
C6+
C6−
C7+
C7−
C8+
C8−
C9+
C2−
C3+
C3−
C4+
C4−
C5+
C5−
C6+
C6−
C7+
C7−
C8+
C2−
C3+
C3−
C4+
C4−
C5+
C5−
C6+
C6−
C7+
C7−
C8+
9x boost mode
8x boost mode
7x boost mode
6x boost mode
C8−
C9+
C9−
C1A
C9−
C1A
5x boost mode
open
C8−
C9+
open
C9−
C1A
open
C9−
C1A
open
C1−
C2+
C1−
C2+
C1−
C2+
C1−
C2+
C1−
C2+
C1−
C2+
open
C1+
C1+
C1+
C1+
C1+
C1+
Figure 5-11. Connection Method for Boost Levels and Capacitors
open
4x boost mode
Table 5-9. Boost Level Settings for Normal Display's Booster
FBS2
FBS1
FBS0
Boost Level
0
0
0
4x
0
0
1
5x
0
1
0
6x
0
1
1
7x
1
0
0
8x
1
0
1
9x
1
1
0
Prohibited
1
1
1
Prohibited
Table 5-10. Boost Level Settings for Partial Display's Booster
BST1
BST0
Boost Level
0
0
2x
0
1
3x
1
0
4x
1
1
Prohibited
Data Sheet S15745EJ2V0DS
31
µPD16488A
5.6.2 Voltage regulator
The boost voltage from VOUT is supplied to the voltage regulator and output as the LCD drive voltage VLCD.
Since the µPD16488A has a 256-step electronic volume function and an on-chip resistor for VLCD voltage regulation, a
small number of components can be used to configure a highly accurate voltage regulator.
(1) When using an on-chip resistor for VLCD voltage regulation
The on-chip resistor for VLCD voltage regulation and the electronic volume function can be used to regulate the contrast of
the LCD contents by controlling the LCD drive voltage VLCD using commands only. In such cases, no external resistor is
needed.
If VLCD < VOUT, then the value for VLCD can be determined from the following equation.
Example Equation VLCD < VOUT
VLCD = (1 + Rb ) VEV
Ra
VLCD = (1 + Rb ) (1 − α ) VREG
Ra
384
Remark VEV = (1 − α ) VREG
384
Figure 5-12. When Using On-Chip Resistor for VLCD Voltage Regulation
+
VEV (Constant voltage source +
electronic volume)
VLCD
Rb
Ra
VREG is the IC's on-chip constant voltage source, for which three types of temperature characteristic curves are available.
These temperature characteristic curves can be adjusted via settings in the power system control register 1 (R32) (TSC1,
TCS0), as shown in Table 5-11.
Table 5-11 shows the VREG voltage when TA = 25°C.
Table 5-11. VREG Voltage When TA = 25°°C
Status
Internal power supply
TCS1
TCS0
Temperature Curve (%/°C)
VREG (TYP.) (V)
0
0
−0.06
1.04
0
1
−0.08
0.98
1
0
−0.09
0.93
1
1
−0.12
0.85
α is the electronic volume register (R35) value. Any of 256 statuses can be set as the fetched status for α corresponding
to the data set to the 8-bit electronic control register. α values based on settings in the electronic volume register (R35:
normal display mode) and the partial electronic volume register (R36: partial display mode) are listed in Table 5-12.
32
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-12. α Values Based on Settings in Electronic Volume Register
Register
α
EV7
EV6
EV5
EV4
EV3
EV2
EV1
EV0
PEV7
PEV6
PEV5
PEV4
PEV3
PEV2
PEV1
PEV0
0
0
0
0
0
0
0
0
384
0
0
0
0
0
0
0
1
254
0
0
0
0
0
0
1
0
253
0
0
0
0
0
0
1
1
252
:
:
1
1
1
1
1
1
0
1
2
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
Rb/Ra is an on-chip resistance factor used for the VLCD voltage regulator. This factor can be controlled at eight levels
based on settings in power control register 2 (R33) (VRR2, VRR1, VRR0: normal display mode and PVR2, PVR1, PVR0:
partial display mode). Reference voltage values (1 + Rb/Ra) are determined based on 4-bit data set to VLCD's on-chip
resistance factor register, as shown in Table 5-13.
Table 5-13. Determination of Reference Voltage Values Based on Settings of
On-Chip Resistor for VLCD Voltage Regulation
Register
VRR2
VRR1
VRR0
PVR2
PVR1
PVR0
0
0
0
0
0
1
8
0
1
0
12
0
1
1
13
1
0
0
16
1
0
1
19
1
1
0
21
1
1
1
24
Data Sheet S15745EJ2V0DS
1+Rb/Ra
5
33
µPD16488A
(2) When using an external resistor (instead of using the on-chip resistor for VLCD voltage regulation)
Instead of using only the on-chip resistor setting for VLCD voltage regulation (IRS = L), resistors (Ra', Rb' and Rc') can be
added between VSS and VR, between AMPOUTP and AMPOUT, and between VR and AMPOUT to set the LCD drive voltage
VLCD. In such cases, the electronic volume function can be used to control the LCD drive voltage VLCD and to regulate the
contrast of the LCD contents via commands.
In addition, the µPD16488A enable selection between two display values (for normal display and partial display).
The
value is set using an external division resistor and is automatically selected by the DTY flag in the control register 2 (R1).
The VLCD value can be determined using Example 1 (DTY = 0) and Example 2 (DTY = 1) if it is within the range of VLCD <
VOUT.
Example 1. DTY = 0, normal display mode
VLCD = (1 + Rb′ ) VEV
Ra′
VLCD = (1 + Rb′ ) (1 − α ) VREG
Ra′
384
Remark VEV (1 −
α ) VREG
384
Example 2. DTY = 1, partial display mode
Rb′ × Rc ) VEV
Ra′(Rb′ + Rc)
VLCD = (1+ Rb′ × Rc ) (1 − α ) VREG
384
Ra′(Rb′ + Rc)
VLCD = (1+
Remark VEV = (1 −
α ) VREG
384
Figure 5-13. When Using External Resistor
+
VLCD
A
VR
AMPOUT
B
Normal/partial VLC1 regulation
select circuit
AMPOUTP
Rb'
Rc
Ra'
34
A
B
Normal display mode
(DTY = 0)
A
B
Partial display mode
(DTY = 1)
Data Sheet S15745EJ2V0DS
µPD16488A
5.6.3 Use of op amp for level power supply control
Although the µPD16488A includes a circuit designed for low power consumption (HPM1, HPM0 = 0, 0), display quality
problems may occur when a large-load LCD panel is used. In such cases, the display quality and power consumption
level can be improved by setting. The HPM1 and HPM0 flags in the power system control register 1 (R32) to "0, 1" to
"1, 1" to switch to the op amp driver capacity for mode settings shown in Table 5-14. Check the actual display quality before
deciding which mode to set.
If setting high power mode still does not sufficiently improve the display quality, the LCD drive voltage must be provided
from an external power source.
Table 5-14. Op Amp Mode Setting
HPM1
HPM0
Mode Setting
0
0
Normal mode
0
1
Low power mode
1
0
High power mode
1
1
For power ON mode
Data Sheet S15745EJ2V0DS
35
µPD16488A
5.6.4 Application examples of power supply circuits
Figures 5-14 to 5-19 show application examples of power supply circuits.
Figure 5-14. IRS = H, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
VDD1
VDD2
VRS
VOUT
VR
Open
AMPOUTP
C1+
AMPOUT
C1 C2+
VLCD
C2 C3+
VLC1
C3 -
VLC2
C4+
VLC3
C4 C5+
VLC4
C5 -
C6+
C6 C7+
C9+
C9 C1A
C7 C8+
C8 VSS
Figure 5-15. IRS = L, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
VRS
VDD1
VDD2
VOUT
AMPOUTP
Rc
VR
Rb'
C1+
C1 C2+
C2 C3+
C3 -
AMPOUT
VLCD
VLC1
VLC2
C4+
C4 C5+
VLC3
VLC4
C5 -
C6+
C6 C7+
C7 C8+
C9+
C9 C1A
C8 VSS
36
Data Sheet S15745EJ2V0DS
Ra'
µPD16488A
Figure 5-16. IRS = H, [OP2, OP1, OP0] = [0, 1, 1]
VRS
VDD1
VDD2
VR
Open
VOUT
AMPOUTP
C1+
C1 C2+
C2 C3+
C3 C4+
Open
C4 C5+
AMPOUT
VLCD
VLC1
VLC2
VLC3
VLC4
C5 C6+
C6 C7+
C7 C8+
C9+
Open
C9 C1A
C8 VSS
Figure 5-17. IRS = L, [OP2, OP1, OP0] = [0, 0, 1]
VRS
Open
VR
Open
VDD1
VDD2
VOUT
C1+
AMPOUTP
C1 C2+
AMPOUT
C2 C3+
C3 C4+
Open
C4 C5+
VLCD
VLC1
VLC2
VLC3
VLC4
C5 C6+
C6 C7+
C7 C8+
C9+
C9 C1A
Open
C8 VSS
Data Sheet S15745EJ2V0DS
37
µPD16488A
Figure 5-18. IRS = L, [OP2, OP1, OP0] = [0, 0, 0]
VDD1
VDD2
VRS
VOUT
AMPOUTP
VR
Open
AMPOUT
C1+
C1 C2+
VLCD
C2 C3+
VLC1
C3 -
VLC2
C4+
Open
VLC3
C4 C5+
VLC4
C5 C6+
C6 C7+
C9+
Open
C9 C1A
C7 C8+
C8 VSS
Figure 5-19. Master/Slave Connection Example
VRS
VDD1
VDD2
VDD1
VDD2
VRS
VR
VR
Open
VOUT
AMPOUTP
AMPOUTP
AMPOUT
AMPOUT
C1 +
VOUT
C1+
−
C1
+
C2
C1−
C2+
VLCD
VLCD
VLC1
VLC1
VLC2
VLC2
VLC3
VLC3
VLC4
VLC4
−
C2
C3+
−
C3
+
C4
Open
Master
Slave
−
C4
+
C5
−
−
C7
C8+
+
C9
−
C9
C1A
C9+
Open
C9 −
C1A
−
C4 −
C5 +
C6 −
+
C7
−
C7
C8 +
C8 −
VSS
C8
VSS
38
−
C3
C4 +
C5 −
+
C6
C5
C6 +
C6 −
C7 +
C2−
C3+
Data Sheet S15745EJ2V0DS
Open
µPD16488A
5.7
LCD Display Drivers
µPD16488A includes a full dot driver. The full dot driver has a 33-level gray-scale palette (eight levels of pulse width
modulation plus four-frame rate control), from which four levels of gray scale can be selected and registered as the IC's
output gray-scale palette (refer to 6.23 Gary scale registers 1 to 4 (R23 to R26)).
5.7.1 Full-dot pulse width modulation
The µPD16488A's pulse width modulator divides the normal LCD display signal's segment pulse width by eight and
outputs in synch with the dot output timing based on the ratio (1/8 to 8/8 pulses) for the gray-scale palette that has been
selected via a command.
Figure 5-20. Full-Dot Pulse Width Modulation
1 frame
1 2 3 4 5 6 7 8
90 91 92
1 2 3 4 5 6 7 8
90 91 92
VLCD
VLC1
VLC2
SEG1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM1
VLC3
VLC4
VSS
Enlarged section
1
2
3
8/8
6/8
4/8
1/8
VLCD
VLC1
VLC2
Caution There is no pulse width modulation for common outputs.
Data Sheet S15745EJ2V0DS
39
µPD16488A
The output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines,
as shown in Figure 5-21. The pulse rising edge and falling edge combinations for each frame are listed in Table 5-15.
Figure 5-21. Example of Pulse Width Modulated Output
1 frame
1
2
3
4
5
6
7
8
9 10 11 12
90 91 92
VLCD
VLC1
VLC2
VLC3
VLC4
VSS
4/8
40
1
2
3
8/8
8/8
8/8
3/8
4/8
Data Sheet S15745EJ2V0DS
1
2
3
4
5
6
7
8
µPD16488A
Table 5-15. Example of Pulse Width Modulated Output (1/3)
Gray-scale
COM
level
1, 2 Frames
3, 4 Frames
5, 6 Frames
7, 8 Frames
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
0
4n+1
4n+2
4n+3
4n+4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4n+1
4n+2
4n+3
4n+4
↑1
0
0
0
↓1
0
0
0
0
0
0
↑1
0
0
0
↓1
0
↓1
0
0
0
↑1
0
0
0
0
↓1
0
0
0
↑1
0
2
4n+1
↑1
↓1
0
0
↑1
↓1
0
0
4n+2
4n+3
4n+4
↓1
0
0
↑1
0
0
0
↓1
↑1
0
↑1
↓1
↓1
0
0
↑1
0
0
0
↓1
↑1
0
↑1
↓1
3
4
5
4n+1
↑1
↓1
↓1
↑1
↑1
↓1
0
0
4n+2
↓1
↑1
0
0
↓1
↑1
↑1
↓1
4n+3
↑1
↓1
↓1
↑1
0
0
↓1
↑1
4n+4
0
0
↑1
↓1
↓1
↑1
↑1
↓1
4n+1
↑1
↓1
↓1
↑1
↑1
↓1
↓1
↑1
4n+2
↓1
↑1
↑1
↓1
↓1
↑1
↑1
↓1
4n+3
4n+4
↑1
↓1
↓1
↑1
↓1
↑1
↑1
↓1
↑1
↓1
↓1
↑1
↓1
↑1
↑1
↓1
4n+1
4n+2
↑2
↓1
↓2
↑1
↓1
↑1
↑1
↓1
↑1
↓2
↓1
↑2
↓1
↑1
↑1
↓1
4n+3
4n+4
↑1
↓1
↓1
↑1
↓1
↑2
↑1
↓2
↑1
↓1
↓1
↑1
↓2
↑1
↑2
↓1
4n+1
↑2
↓2
↓1
↑1
↑2
↓2
↓1
↑1
4n+2
4n+3
4n+4
↓2
↑1
↓1
↑2
↓1
↑1
↑1
↓2
↑2
↓1
↑2
↓2
↓2
↑1
↓1
↑2
↓1
↑1
↑1
↓2
↑2
↓1
↑2
↓2
7
4n+1
4n+2
4n+3
4n+4
↑2
↓2
↑2
↓1
↓2
↑2
↓2
↑1
↓2
↑1
↓2
↑2
↑2
↓1
↑2
↓2
↑2
↓2
↑1
↓2
↓2
↑2
↓1
↑2
↓1
↑2
↓2
↑2
↑1
↓2
↑2
↓2
8
4n+1
↑2
↓2
↓2
↑2
↑2
↓2
↓2
↑2
4n+2
↓2
↑2
↑2
↓2
↓2
↑2
↑2
↓2
4n+3
4n+4
↑2
↓2
↓2
↑2
↓2
↑2
↑2
↓2
↑2
↓2
↓2
↑2
↓2
↑2
↑2
↓2
9
4n+1
4n+2
4n+3
4n+4
↑3
↓2
↑2
↓2
↓3
↑2
↓2
↑2
↓2
↑2
↓2
↑3
↑2
↓2
↑2
↓3
↑2
↓3
↑2
↓2
↓2
↑3
↓2
↑2
↓2
↑2
↓3
↑2
↑2
↓2
↑3
↓2
10
4n+1
4n+2
4n+3
4n+4
↑3
↓3
↑2
↓2
↓3
↑3
↓2
↑2
↓2
↑2
↓3
↑3
↑2
↓2
↑3
↓3
↑3
↓3
↑2
↓2
↓3
↑3
↓2
↑2
↓2
↑2
↓3
↑3
↑2
↓2
↑3
↓3
6
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
Data Sheet S15745EJ2V0DS
41
µPD16488A
Table 5-15. Example of Pulse Width Modulated Output (2/3)
Gray-scale
COM
level
11
12
13
1, 2 Frames
3, 4 Frames
5, 6 Frames
7, 8 Frames
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
4n+1
↑3
↓3
↓3
↑3
↑3
↓3
↓2
↑2
4n+2
↓3
↑3
↑2
↓2
↓3
↑3
↑3
↓3
4n+3
↑3
↓3
↓3
↑3
↑2
↓2
↓3
↑3
4n+4
↓2
↑2
↑3
↓3
↓3
↑3
↑3
↓3
4n+1
↑3
↓3
↓3
↑3
↑3
↓3
↓3
↑3
4n+2
↓3
↑3
↑3
↓3
↓3
↑3
↑3
↓3
4n+3
4n+4
↑3
↓3
↓3
↑3
↓3
↑3
↑3
↓3
↑3
↓3
↓3
↑3
↓3
↑3
↑3
↓3
4n+1
↑4
↓4
↓3
↑3
↑3
↓3
↓3
↑3
4n+2
↓3
↑3
↑3
↓3
↓4
↑4
↑3
↓3
4n+3
4n+4
↑3
↓3
↓3
↑3
↓3
↑4
↑3
↓4
↑3
↓3
↓3
↑3
↓4
↑3
↑4
↓3
4n+1
↑4
↓4
↓3
↑3
↑4
↓4
↓3
↑3
4n+2
↓4
↑4
↑3
↓3
↓4
↑4
↑3
↓3
4n+3
↑3
↓3
↓4
↑4
↑3
↓3
↓4
↑4
4n+4
↓3
↑3
↑4
↓4
↓3
↑3
↑4
↓4
4n+1
↑4
↓4
↓4
↑4
↑4
↓4
↓3
↑3
4n+2
↓4
↑4
↑3
↓3
↓4
↑4
↑4
↓4
4n+3
↑4
↓4
↓4
↑4
↑3
↓3
↓4
↑4
4n+4
↓3
↑3
↑4
↓4
↓4
↑4
↑4
↓4
4n+1
↑4
↓4
↓4
↑4
↑4
↓4
↓4
↑4
4n+2
4n+3
4n+4
↓4
↑4
↓4
↑4
↓4
↑4
↑4
↓4
↑4
↓4
↑4
↓4
↓4
↑4
↓4
↑4
↓4
↑4
↑4
↓4
↑4
↓4
↑4
↓4
4n+1
4n+2
↑5
↓4
↓5
↑4
↓4
↑4
↑4
↓4
↑4
↓5
↓4
↑5
↓4
↑4
↑4
↓4
4n+3
4n+4
↑4
↓4
↓4
↑4
↓4
↑5
↑4
↓5
↑4
↓4
↓4
↑4
↓5
↑4
↑5
↓4
4n+1
4n+2
↑5
↓5
↓5
↑5
↓4
↑4
↑4
↓4
↑5
↓5
↓5
↑5
↓4
↑4
↑4
↓4
4n+3
4n+4
↑4
↓4
↓4
↑4
↓5
↑5
↑5
↓5
↑4
↓4
↓4
↑4
↓5
↑5
↑5
↓5
19
4n+1
4n+2
4n+3
4n+4
↑5
↓5
↑5
↓4
↓5
↑5
↓5
↑4
↓5
↑4
↓5
↑5
↑5
↓4
↑5
↓5
↑5
↓5
↑4
↓5
↓5
↑5
↓4
↑5
↓4
↑5
↓5
↑5
↑4
↓5
↑5
↓5
20
4n+1
4n+2
↑5
↓5
↓5
↑5
↓5
↑5
↑5
↓5
↑5
↓5
↓5
↑5
↓5
↑5
↑5
↓5
4n+3
4n+4
↑5
↓5
↓5
↑5
↓5
↑5
↑5
↓5
↑5
↓5
↓5
↑5
↓5
↑5
↑5
↓5
4n+1
4n+2
4n+3
4n+4
↑6
↓5
↑5
↓5
↓6
↑5
↓5
↑5
↓5
↑5
↓5
↑6
↑5
↓5
↑5
↓6
↑5
↓6
↑5
↓5
↓5
↑6
↓5
↑5
↓5
↑5
↓6
↑5
↑5
↓5
↑6
↓5
14
15
16
17
18
21
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
42
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-15. Example of Pulse Width Modulated Output (3/3)
Gray-scale
COM
level
22
23
24
25
26
27
28
29
30
31
32
1, 2 Frames
3, 4 Frames
5, 6 Frames
7, 8 Frames
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
SEG Odd
Numbered
SEG Even
Numbered
4n+1
↑6
↓6
↓5
↑5
↑6
↓6
↓5
↑5
4n+2
4n+3
↓6
↑5
↑6
↓5
↑5
↓6
↓5
↑6
↓6
↑5
↑6
↓5
↑5
↓6
↓5
↑6
4n+4
↓5
↑5
↑6
↓6
↓5
↑5
↑6
↓6
4n+1
↑6
↓6
↓6
↑6
↑6
↓6
↓5
↑5
4n+2
4n+3
4n+4
↓6
↑6
↓5
↑6
↓6
↑5
↑5
↓6
↑6
↓5
↑6
↓6
↓6
↑5
↓6
↑6
↓5
↑6
↑6
↓6
↑6
↓6
↑6
↓6
4n+1
4n+2
↑6
↓6
↓6
↑6
↓6
↑6
↑6
↓6
↑6
↓6
↓6
↑6
↓6
↑6
↑6
↓6
4n+3
4n+4
↑6
↓6
↓6
↑6
↓6
↑6
↑6
↓6
↑6
↓6
↓6
↑6
↓6
↑6
↑6
↓6
4n+1
↑7
↓7
↓6
↑6
↑6
↓6
↓6
↑6
4n+2
4n+3
↓6
↑6
↑6
↓6
↑6
↓6
↓6
↑6
↓7
↑6
↑7
↓6
↑6
↓7
↓6
↑7
4n+4
↓6
↑6
↑7
↓7
↓6
↑6
↑6
↓6
4n+1
↑7
↓7
↓6
↑6
↑7
↓7
↓6
↑6
4n+2
↓7
↑7
↑6
↓6
↓7
↑7
↑6
↓6
4n+3
↑6
↓6
↓7
↑7
↑6
↓6
↓7
↑7
4n+4
↓6
↑6
↑7
↓7
↓6
↑6
↑7
↓7
4n+1
↑7
↓7
↓7
↑7
↑7
↓7
↓6
↑6
4n+2
↓7
↑7
↑6
↓6
↓7
↑7
↑7
↓7
4n+3
↑7
↓7
↓7
↑7
↑6
↓6
↓7
↑7
4n+4
↓6
↑6
↑7
↓7
↓7
↑7
↑7
↓7
4n+1
↑7
↓7
↓7
↑7
↑7
↓7
↓7
↑7
4n+2
↓7
↑7
↑7
↓7
↓7
↑7
↑7
↓7
4n+3
↑7
↓7
↓7
↑7
↑7
↓7
↓7
↑7
4n+4
↓7
↑7
↑7
↓7
↓7
↑7
↑7
↓7
4n+1
4n+2
8
↓7
8
↑7
↓7
↑7
↑7
↓7
↑7
8
↓7
8
↓7
↑7
↑7
↓7
4n+3
↑7
↓7
↓7
↑7
↑7
↓7
8
8
4n+4
↓7
↑7
8
8
↓7
↑7
↑7
↓7
4n+1
8
8
↓7
↑7
8
8
↓7
↑7
4n+2
4n+3
4n+4
8
↑7
↓7
8
↓7
↑7
↑7
8
8
↓7
8
8
8
↑7
↓7
8
↓7
↑7
↑7
8
8
↓7
8
8
4n+1
8
8
8
8
8
8
↓7
↑7
4n+2
4n+3
8
8
8
8
↑7
8
↓7
8
8
↑7
8
↓7
8
8
8
8
4n+4
↓7
↑7
8
8
8
8
8
8
4n+1
8
8
8
8
8
8
8
8
4n+2
4n+3
4n+4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
Data Sheet S15745EJ2V0DS
43
µPD16488A
5.7.2 Full-dot frame rate control
When combined with pulse width modulation as described in Table 5-15, the µPD16488A's frame speed is based on 8frame cycles. The subsampling pattern is output based on the palette stored in the IC.
Full-Dot Gray-Scale Palette (Output Pulse Width: x/8 Pulses)
Gray Scale
Frames
1
2
3
4
5
6
7
8
Level 0
0
0
0
0
0
0
0
0
Level 1
1
1
0
0
0
0
0
0
Level 2
1
1
0
0
1
1
0
0
Level 3
1
1
1
1
1
1
0
0
Level 4
1
1
1
1
1
1
1
1
Level 5
2
2
1
1
1
1
1
1
Level 6
2
2
1
1
2
2
1
1
Level 7
2
2
2
2
2
2
1
1
Level 8
2
2
2
2
2
2
2
2
Level 9
3
3
2
2
2
2
2
2
Level 10
3
3
2
2
3
3
2
2
Level 11
3
3
3
3
3
3
2
2
Level 12
3
3
3
3
3
3
3
3
Level 13
4
4
3
3
3
3
3
3
Level 14
4
4
3
3
4
4
3
3
Level 15
4
4
4
4
4
4
3
3
Level 16
4
4
4
4
4
4
4
4
Level 17
5
5
4
4
4
4
4
4
Level 18
5
5
4
4
5
5
4
4
Level 19
5
5
5
5
5
5
4
4
Level 20
5
5
5
5
5
5
5
5
Level 21
6
6
5
5
5
5
5
5
Level 22
6
6
5
5
6
6
5
5
Level 23
6
6
6
6
6
6
5
5
Level 24
6
6
6
6
6
6
6
6
Level 25
7
7
6
6
6
6
6
6
Level 26
7
7
6
6
7
7
6
6
Level 27
7
7
7
7
7
7
6
6
Level 28
7
7
7
7
7
7
7
7
Level 29
8
8
7
7
7
7
7
7
Level 30
8
8
7
7
8
8
7
7
Level 31
8
8
8
8
8
8
7
7
Level 32
8
8
8
8
8
8
8
8
Comments
OFF data
50%
100%
Remark The gradation in the Comments column are images of the gray-scale level.
44
Data Sheet S15745EJ2V0DS
µPD16488A
5.7.3 Line shift driver
If the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the LCD's full
screen, problems such as flickering may occur on the LCD panel. The µPD16488A provides a line shift driver as a
countermeasure against such screen image problems.
Using 8 frames per cycle, the segment PWM output timing is shifted among the common outputs, as shown in Table 5-16
below.
Table 5-16. Line Shift Driver
Turn 1
Turn 2
Frame
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
COM1
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
COM2
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
COM3
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
COM4
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
COM5
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
COM6
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
COM7
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
COM8
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
COM9
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
COM10
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Remark Fx: Pulse width modulated output frame (See 5.7.2 Full-dot frame rate control).
Figure 5-22. Full Dot Frame Rate Control
First frame
1
2
3
4
5
Second frame
91
92
1
2
ON
OFF
ON
OFF
ON
OFF
COM1
COM2
COM3
ON
OFF
ON
OFF
COM4
COM5
COM91
COM92
ON
OFF
ON
OFF
SEG1
8
1
5
3
7
1
5
3
7
2
6
SEG2
8
1
5
3
7
1
5
3
7
2
6
SEG3
8
1
5
3
7
1
5
3
7
2
6
SEG4
8
1
5
3
7
1
5
3
7
2
6
SEG5
8
1
5
3
7
1
5
3
7
2
6
Remark Numerical values in the segment data correspond to the gray-scale palette's frame numbers.
Data Sheet S15745EJ2V0DS
45
µPD16488A
Figure 5-23. Line Shift Driver Image
Turn 1, first frame
SEG1
SEG3
SEG2
SEG5
SEG4
SEG7
SEG6
SEG127
SEG8
COM1
F1
COM2
F5
COM3
F3
COM4
F7
COM5
F1
COM90
F5
COM91
F3
COM92
F7
SEG126
SEG128
Turn 1, second frame
SEG1
SEG3
SEG2
46
SEG5
SEG4
SEG7
SEG6
SEG127
SEG8
COM1
F2
COM2
F6
COM3
F4
COM4
F8
COM5
F2
COM90
F6
COM91
F4
COM92
F8
Data Sheet S15745EJ2V0DS
SEG126
SEG128
µPD16488A
5.7.4 Display size settings
The µPD16488A can be set for any duty value from 1/1 to 1/92. This duty setting can be made via bits DT6 to DT0 in the
duty setting register (R5), as shown in Table 5-17.
Table 5-17. Duty Settings
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
:
1
1
1
0
0
0
0
1
1
1
0
1
1/1
1/2
1/3
1/4
:
1/90
1/91
1/92
1
0
1
1
1
0
0
prohibited
Caution The duty setting can not be over 1/92 duty (5CH). If 1/92 duty is exceeded, operation is not guaranteed.
5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position
The µPD16488A enable any setting to be made for the AC driver's inversion position and the inversion position shift
amount for each displayed frame via settings made in the AC driver inversion cycle register (R6) and the AC driver
inversion position shift register (R7) for normal display mode or via settings made in the partial AC driver inversion cycle
register (R8) and the partial AC driver inversion position shift register (R9) for partial display mode.
In normal display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed
in Table 5-18, based on the NID6 to NID0 bit settings in the AC driver inversion cycle register (R6).
If the screen display size has been changed via settings made in the duty setting register (R5), the NIDn values are
automatically overwritten by values from the corresponding DTYn bits.
The shift amount for each displayed frame can be set as shown in Table 5-19 via settings made to bits MSD6 to MSD0 in
the AC driver inversion position shift register (R7).
Table 5-18. Settings of AC Driver Inversion Cycle Register (R6)
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Inverted Lines
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
:
1
1
1
0
0
0
0
1
1
1
0
1
1
2
3
4
:
90
91
92
1
0
1
1
1
0
0
prohibited
Caution The inversion line can not be over 92-inversion line (5CH). If 92-inversion line is exceeded, operation is
not guaranteed.
Data Sheet S15745EJ2V0DS
47
µPD16488A
Table 5-19. Settings of AC Driver Inversion Position Shift Register
MSD6
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
1
0
1
1
0
0
1
89
1
0
1
1
0
1
0
90
1
0
1
1
0
1
1
91
1
0
1
1
1
0
0
prohibited
:
:
Caution The inversion position shift amount can not be over 91 (5CH). If 91 is exceeded, operation is not guaranteed.
In partial display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in
Table 5-20, based on the PID5 to PID0 bit settings in the partial AC driver inversion cycle register (R8).
The shift amount for each displayed frame can be set as shown in Table 5-21 via settings made to bits PSD5 to PSD0 in
the partial AC driver inversion position shift register (R9).
Table 5-20. Settings of Partial AC Driver Inversion Cycle Register (R8)
PID5
PID4
PID3
PID2
PID1
PID0
Inverted Lines
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
1
0
0
0
1
1
36
1
0
0
1
0
0
37
1
0
0
1
0
1
38
:
:
Table 5-21. Setting of Partial AC Driver Inversion Position Shift Register (R9)
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
:
:
1
0
0
0
1
1
35
1
0
0
1
0
0
36
1
0
0
1
0
1
37
Be sure to maintain the following relationship among the display size, AC inversion cycle, and AC inversion position.
Display size (duty) ≥ AC inversion cycle ≥ AC inversion shift amount
Caution Setting a small inversion cycle will cause a reduction in the IC's display drive capacity and an increase
in the current consumption. We therefore recommend determining the inversion cycle after making a
thorough evaluation of the actual LCD panel.
48
Data Sheet S15745EJ2V0DS
µPD16488A
5.8
Display Modes
5.8.1 Partial display mode
The µPD16488A includes a function for outputting a display that uses only part of the LCD panel. The duty setting for
partial display mode can be selected as 1/12, 1/25, or 1/38. Parts of the LCD panel that are outside of the specified display
area are scanned with non-select waveforms. The partial start line address register (R21) is used to select which part of
the LCD panel to use for the partial display. The display area starts from the start line address and includes the number of
lines (12, 25, or 38 lines) that has been specified via the partial display mode setting (R10).
When entering this mode, the booster is set to the boost level number that has been set via the power system control
register 3 (partial display boost register) (R34) and the display start line is fixed as 00H. In addition, the bias level is
automatically changed to the value that has been set via the partial display mode setting (R10). The relationship between
the oscillator's frequency and the frame frequency in partial mode is also automatically changed.
Figure 5-24 shows the mutual relationship between the partial line start address and the LCD display.
When using the partial display mode, the blinking and reverse display functions can be used in the same way as during
full-dot display mode.
Caution The LCD driver voltage is lower in partial display mode, because the duty is lower than in normal display
mode. There may be restrictions on the usable duty depending on the LCD panel characteristics.
We recommend determining the partial duty after making a thorough evaluation of the actual LCD panel.
Figure 5-24. Relationship Between Partial Line Start Address and LCD Display
(in Partial Display Mode)
00H
01H
02H
03H
...
1DH
1EH
1FH
Display start line
(00H)
12, 25, or 38 lines
Partial display
start line
Non-display areas
Caution In partial display mode, the display start line setting register (R12) command is ignored.
When switching from normal display mode to partial display mode or from partial display mode to normal display mode, if
an electric charge remains in the smoothing capacitor that is connected between the LCD drive voltage pins (VLCD, VLC1 to
VLC4) and the VSS pin, troubles such as a brief all-black display may occur during the mode switching operation. To avoid
such troubles, we recommend using the following power-on sequence.
Data Sheet S15745EJ2V0DS
49
µPD16488A
(1) Normal display → partial display switch sequence
DISP = 0
R0
Display OFF
R32
High power mode settings
R1
Control register 2: switch DTY flag
↓
HPM1 = 1, HPM0 = 0
↓
Switch display mode
↓
700 ms (stabilization time for LCD drive voltage and
Wait time
booster)Note
↓
HPM1 = X, HPM0 = X
R32
(to mode used during normal display)
↓
DISP = 1
Note
High power mode settings
R0
Display ON, internal operations status
This 700 ms wait time indicates the time for the VLCD level to change from 15 V to 6 V and thus varies according to
the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend
determining the wait time after making a thorough evaluation of the actual device.
(2) Partial display → Normal display switch sequence
DISP = 0
R0
Display OFF
R32
Power ON mode settings
R1
Control register 2: switch DTY flag
↓
HPM1 = 1, HPM0 = 1
↓
Switch display mode
↓
400 ms (stabilization time for LCD drive voltage and
Wait time
booster)Note
↓
HPM1 = X, HPM0 = X
R32
(to mode used during normal display)
↓
DISP = 1
Note
High power mode settings
R0
Display ON, internal operations status
This 400 ms wait time indicates the time for the VLCD level to change from 6 V to 15 V and thus varies according to
the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend
determining the wait time after making a thorough evaluation of the actual device.
50
Data Sheet S15745EJ2V0DS
µPD16488A
5.8.2 Monochrome (black/white) display
The µPD16488A provides both a four-level gray scale display mode and a monochrome display mode.
To switch to the monochrome display mode, set GRAY = H. The display RAM for one screen of monochrome display
mode contents is configured as 128 bits x 128 bits (16 x 8 bits). When using these IC's in monochrome display mode, two
screens of data can be written to the display RAM and the two screens can be switched by setting the DSEL bit in the
control register 2 (R1). Screen 1 is displayed on the LCD panel when DSEL = L and screen 2 is displayed when DSEL = H.
When writing data, the display RAM uses the same X address (00H to 0FH) and Y address and the BWW bit value in the
control register 2 (R1) determines which of the two screens the data will be written to: when BWW = L, data is written to
screen 1 and when BWW = H, data is written to screen 2, as shown in Figure 5-25.
When accessing a specified bit, specify both the X address and Y address. The display data in D0 to D7 (sent from the
CPU) corresponds to the SEGx portions of the LCD display, as shown in Figure 5-26. Figure 5-27 shows the relationship
between the display data in monochrome display mode and the page/column addresses.
Figure 5-25. Display RAM Image in Monochrome (Black/White) Mode
00H
0FH
00H
Screen 1
DSEL = L (during display)
BWW = L (during write)
0FH
Screen 2
DSEL = H (during display)
BWW = H (during write)
Figure 5-26. Relationship Between Display Data and LCD Display
Data
7
0
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
0
5
0
0
1
0
0
0
0
0
4
0
0
0
1
0
0
0
0
3
0
0
0
0
1
0
0
0
2
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
7
1
0
0
1
0
0
1
0
6
1
0
0
1
0
0
1
0
5
1
0
0
1
0
0
1
0
4
1
0
0
1
0
0
1
0
3
0
0
0
0
0
0
0
0
2
0
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
Display data
LCD display
Data Sheet S15745EJ2V0DS
51
µPD16488A
Figure 5-27. Relation Between the Display Data and X/Y Address
D4
D3
D2
D1
0
0
0
0
1
01H
0
0
0
0
0
00H
D0
0
1
1
1
1
0FH
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
COM output
Yaddress
D7 D6 D5 D4 D3 D2 D1 D0
COM1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
Start
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
92-line
COM83
COM84
COM85
COM86
COM87
COM88
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
COM89
COM90
COM91
COM92
52
Column
Address
ADC
0
D0
78H 07H
SEG8
1
79H 06H
SEG7
D0
7AH 05H
SEG6
LCD
output
7BH 04H
SEG5
SEG128 00H 7FH
7CH 03H
SEG4
Data Sheet S15745EJ2V0DS
SEG127 01H 7EH
7DH 02H
SEG3
SEG126 02H 7DH
7EH 01H
SEG2
SEG125 03H 7CH
7FH 00H
7FH
SEG1
X address
(in Monochrome Display Mode)
µPD16488A
5.9
Reset
In the µPD16488A, a reset is executed when the /RES input is at low level or when a reset command is entered. The IC
is reset to its default settings. These default settings are listed in the table below.
/RES
Reset Command
Control register 1
Register
R0
Number
Enabled (DISP flag only)
Enabled
Control register 2
R1
Enabled (IDIS flag only)
X address register
R3
Disabled
Y address register
R4
Duty setting register
R5
AC driver inversion cycle register
R6
EnabledNote2
AC driver inversion position shift register
R7
Partial AC driver inversion cycle register
R8
Enabled
Partial AC driver inversion position shift register
R9
Partial display mode setting register
R10
Display memory access register Note1
R11
Disabled
Display start line setting register
R12
Enabled
Blink X address register
R13
Blink start line address register
R14
Blink end line address register
R15
Blink data memory access register Note1
R16
Disabled
Inverted X address register
R17
Enabled
Inversion start line address register
R18
Inversion end line address register
Inverted data memory access register
R19
Note1
R20
Disabled
Partial start line address register
R21
Enabled
Gray scale data register 1 (0, 0)
R23
Gray scale data register 2 (0, 1)
R24
Gray scale data register 3 (1, 0)
R25
Gray scale data register 4 (1, 1)
R26
Partial gray scale data register 1 (0, 0)
R27
Partial gray scale data register 2 (0, 1)
R28
Partial gray scale data register 3 (1, 0)
R29
Partial gray scale data register 4 (1, 1)
R30
Power system control register 1
R32
Power system control register 2
R33
Power system control register 3
R34
Electronic volume register
R35
Partial electronic volume register
R36
Boost adjustment register
R37
RAM test mode setting register
R44
Signature read register
R45
Disabled
Enabled: Default value is input, Disabled: Default value is not input
Notes 1. When using the /RES pin to reset, the contents of memory are not retained. Use the reset command to reset
if the memory contents need to be retained.
2. Be sure to set this register again after input the reset command.
Cautions 1. Using the /RES pin to reset initializes the shift clock counter.
2. Always input the reset command as the first command after power ON.
Data Sheet S15745EJ2V0DS
53
µPD16488A
6. COMMAND REGISTERS
The µPD16488A uses a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals. Command
interpretation and execution is performed using internal timing that does not depend on any external clock. Therefore,
processing is very fast and there is usually no need to check for a busy status.
The i80 series CPU interface activates read commands using a low pulse input to the /RD pin and activates write
commands using a low pulse input to the /WR pin. The M68 series CPU interface sets read mode using a high level input
to the R,/W pin and sets write mode using a low level input to the same pin. It activates both read and write commands
using a high-level pulse input to the E pin.
Command descriptions using an i80 series CPU interface are shown as follows. The M68 series CPU interface differs
from the i80 series CPU interface in that /RD (E) is at high level during status read and display data read operations, as
shown in the following command descriptions and command table.
If the serial interface has been selected, data is input sequentially starting from D7.
54
Data Sheet S15745EJ2V0DS
µPD16488A
6.1 Control Register 1 (R0)
This command specifies the µPD16488A's general operation modes.
RS
E
/RD
R,/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
RMW
DISP
STBY
BLD
IVD
HALT
ADC
COMR
Flag
Function
RMW
0: Address is incremented after both write access and read access.
1: Read/modify/write mode
(Address is incremented only after write access)
DISP
0: Display OFF (All LCD output pins output the VSS level and oscillator and DC/DC converter are operating)
1: Display ON
STBY
0: Normal operation
1: Internal operation and oscillation are stopped. Display is OFF.
BLD
The blinking dots are specified via the blink start/end line address registers and data is set to blink data RAM.
0: Stop blinking
1: Start blinking
IVD
The number of inverted dots is specified via the inversion start/end line address registers and data is set to
inverted data RAM.
0: Stop inversion
1: Start inversion
HALT
0: Start internal operation
1: Stop internal operation (since different display modes are used, when switching between partial and normal
display modes, the LCD output pins all output the VSS level and the oscillator is operating, but the DC/DC
converter is stopped)
ADC Note
The column address corresponding to the SEG outputs (see Table 6-1) for displaying the contents of the display
data RAM.
COMR
Note
This inverts (reverses) the scan direction for common outputs. (See Table 6-2)
Note The reset command must be executed before changing this flag's setting.
Table 6-1. Relationship between Display RAM Column Address and SEG Outputs
SEG Output
ADC
(D1)
SEG1
SEG128
0
00H
→
Column addresses
→
7FH
1
7FH
←
Column addresses
←
00H
Table 6-2. Relationship between Common Scan Circuit and Scan Direction
COM Output
COMR
(D0)
Scan Direction
0
COM1
→
COM92
1
COM92
→
COM1
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Data Sheet S15745EJ2V0DS
55
µPD16488A
6.2 Control Register 2 (R1)
This command specifies the µPD16488A's general operation modes.
RS
E
/RD
R,/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
FDM
−
−
DSEL
BWW
GRAY
DTY
INC
Flag
Function
FDM
Settings for full screen display mode
0: Normal operation
1: Full screen display (set entire screen to ON) (When using four-level gray scale, gray-scale level 32 is output
for full screen display).
DSEL
Selects display screen during monochrome display mode.
0: Screen 1
1: Screen 2
BWW
Selects data write screen during monochrome display mode.
0: Screen 1
1: Screen 2
GRAY Note
0: 4-level gray scale display mode
1: Monochrome display mode
DTY Note
0: Normal display mode (1/1 to 1/128 duty)
1: Partial display mode (1/12, 1/25, or 1/38 duty, 1/5 or 1/6 bias)
INC
0: Increments X address at each access
1: Increments Y address at each access
Note The HALT command must be executed before changing this flag's setting.
Table 6-3. Relationship between IC's Functions and Display Modes
Item
Normal Display Mode (DTY = 0)
Partial Display Mode (DTY = 1)
Duty
1/1 to 1/92 duty
↔
1/12, 1/25, or 1/38 duty
Booster
×4, ×5, ×6, ×7, ×8, ×9
↔
×2, ×3, ×4
Bias level
1/11, 1/12, 1/10, 1/9, 1/8, 1/7
↔
1/5, 1/6
Gray scale data
Uses levels set to the gray scale data
↔
Uses levels set to the partial gray scale
registers (R23 to R26)
data registers (R27 to R30)
(1+Rb/Ra)
Uses values of VRR2 to VRR0 in the power
VLCD regulator resistance
system control register 2 (R33)
↔
Uses values of PVR2 to PVR0 in the power
system control register 2 (R33)
factor
Electronic volume
↔
Uses value from the electronic volume
register (R35)
volume register (R36)
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
56
Uses value from the partial electronic
Data Sheet S15745EJ2V0DS
µPD16488A
6.3 Reset Command (R2)

When this command is input, the IC's registers (R0 to R44) are reset to their initial values. However, the contents of
memory are retained.
Always input the reset command as the first command after power application.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
1
6.4 X Address Register (R3)
The X address register specifies the X address in the display RAM accessed by the CPU. This address is automatically
incremented each time the display RAM is accessed (INC = 0, RMW = 0).
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
XA4
XA3
XA2
XA1
XA0
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
D3
D2
D1
D0
0
0
0
0
0
6.5 Y Address Register (R4)
The Y address register specifies the Y address in the display RAM accessed by the CPU. This address is automatically
incremented each time the display RAM is accessed (INC = 1, RMW = 0).
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
YA6
YA5
YA4
YA3
YA2
YA1
YA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
Data Sheet S15745EJ2V0DS
57
µPD16488A
6.6 Duty Setting Register (R5)
The display duty can be set to any duty ratio between 1/1 and 1/92, as is shown in Table 6-4.
Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
Also, be sure to set this register again after input the reset command.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Table 6-4. Duty Setting Register (R5) Settings
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
:
1
1
1
0
0
0
0
1
1
1
0
1
1/1
1/2
1/3
1/4
:
1/90
1/91
1/92
1
0
1
1
0
0
0
inhibited
Caution The display size can not be over 1/92 duty ( 5CH). If 1/92 duty is exceeded, operation is not guaranteed.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
58
Data Sheet S15745EJ2V0DS
µPD16488A
6.7 AC Driver Inversion Cycle Register (R6)
The AC driver's line position for normal display mode can be set as shown in Table 6-5.
When a DTYn value is changed in the duty setting register (R5), the NIDn value is automatically overwritten by the DTYn value.
Be sure to set this register again after input the reset command.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Table 6-5. AC Driver Inversion Cycle Register (R6) Settings
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Inversion Line
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
:
1
1
1
0
0
0
0
1
1
1
0
1
1
2
3
4
:
90
91
92
1
0
1
1
1
0
0
Inhibited
Caution The inversion line can not be over 92 (5CH). If 92-line is exceeded, operation is not guaranteed.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
6.8 AC Driver Inversion Position Shift Register (R7)
This register shifts the inversion position for each frame in normal display mode by the shift amount shown in Table 6-6.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
MSD6
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Table 6-6. AC Driver Inversion Position Shift Register (R7) Settings
MSD5
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
1
0
1
1
0
0
1
89
1
0
1
1
0
1
0
90
1
0
1
1
0
1
1
91
1
0
1
1
1
0
0
92
:
:
Caution The inversion position shift amount can not be over 91 (5CH). If 91 is exceeded, operation is not guaranteed.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
Data Sheet S15745EJ2V0DS
59
µPD16488A
6.9 Partial AC Driver Inversion Cycle Register (R8)
The AC driver's line position can be set as shown in Table 6-7.
When a PDTn value is changed in the partial display mode setting register (R10), the PIDn value is automatically
overwritten by the PDTn value.
RS
1
D7
−
D6
−
D5
D4
D3
D2
D1
D0
PID5
PID4
PID3
PID2
PID1
PID0
Table 6-7. Partial AC Driver Inversion Cycle Register (R8) Settings
PID5
PID4
PID3
PID2
PID1
PID0
Inversion Line
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
1
0
0
0
1
1
36
1
0
0
1
0
0
37
1
0
0
1
0
1
38
:
:
Default settings (initial values set by reset command)
D7
−
D6
−
D5
D4
D3
D2
D1
D0
1
0
0
1
0
1
6.10 Partial AC Driver Inversion Position Shift Register (R9)
This register shifts the inversion position for each frame by the shift amount shown in Table 6-8.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Table 6-8. Partial AC Driver Inversion Position Shift Register (R9) Settings
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
1
0
0
0
1
1
35
1
0
0
1
0
0
36
1
0
0
1
0
1
37
:
:
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
0
0
0
0
0
60
Data Sheet S15745EJ2V0DS
µPD16488A
6.11 Partial Display Mode Setting Register (R10)
This command specifies the operation mode to be used in the µPD16488A's partial display mode.
Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
PBIS
−
PDT1
PDT0
Flag
Function
PBIS
Sets bias level for partial display mode
0: 1/5 bias
1: 1/6 bias
PDT1, PDT0

PDT1
PDT0
0
0
Duty in partial display mode
1/38 duty
0
1
1/25 duty
1
0
1/12 duty
1
1
Prohibited
Caution With the setting of 1/12 duty, the level voltage (VLCn) for driving liquid crystal pannel may not reach the
set value depending on the panel used. Thoroughly evaluate the relationship between the duty and
driving voltage with the actual system.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
0
−
0
0
6.12 Display Memory Access Register (R11)
The display memory access register is used when accessing the display RAM. When this register is write-accessed, data
is written directly to the display RAM. When this register is read-accessed, data from the display RAM is first latched to this
register before being sent to the bus during the next read operation. Accordingly, one dummy read access is required after
display RAM access has been set.

When using reset command to reset, the contents of memory are retained.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
D6
D5
D4
D3
D2
D1
D0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
Data Sheet S15745EJ2V0DS
61
µPD16488A
6.13 Display Start Line Setting Register (R12)
Display start line set specifies the top line in the display.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
DSL6
DSL5
DSL4
DSL3
DSL2
DSL1
DSL0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
6.14 Blink X Address Register (R13)
The blink X address register specifies the X address of the blink data RAM accessed by the CPU. This address is
automatically incremented each time the blink data RAM is accessed.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
BXA3
BXA2
BXA1
BXA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
0
0
0
0
6.15 Blink Start Line Address Register (R14)
The blink start line address register specifies the start line address of the display RAM accessed when the CPU uses blink
display mode. The range of blinking lines is determined based on the contents of this register and the blink end line
address register.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
−
BSL6
BSL5
BSL4
BSL3
BSL2
BSL1
BSL0
−
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
6.16 Blink End Line Address Register (R15)
The blink end line address register specifies the end line address of the display RAM accessed when the CPU uses blink
display mode. The range of blinking lines is determined based on the contents of this register and the blink start line
address register.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
−
BEL6
BEL5
BEL4
BEL3
BEL2
BEL1
BEL0
−
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
62
Data Sheet S15745EJ2V0DS
µPD16488A
6.17 Blink Data Memory Access Register (R16)
The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data
is written directly to the blink data RAM.

When using reset command to reset, the contents of memory are retained.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
D6
D5
D4
D3
D2
D1
D0
Data
Status
0
Normal
1
Blink
Default settings (initial values set by reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
6.18 Inverted X Address Register (R17)
The inverted X address register specifies the X address in the inverted data RAM accessed by the CPU. This address is
incremented each time the inversion RAM is accessed.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
D2
D1
D0
IXA3
IXA2
IXA1
IXA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
0
0
0
0
6.19 Inversion Start Line Address Register (R18)
The inversion start line address register specifies the start line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion end line address register.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
ISL6
ISL5
ISL4
ISL3
ISL2
ISL1
ISL0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
Data Sheet S15745EJ2V0DS
63
µPD16488A
6.20 Inversion End Line Address Register (R19)
The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion start line address register.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
−
IEL6
IEL5
IEL4
IEL3
IEL2
IEL1
IEL0
−
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
6.21 Inverted Data Memory Access Register (R20)
The inverted data memory access register is used when accessing the inverted data RAM. When this register is
accessed, the data is written directly to the inverted data RAM.

When using reset command to reset, the contents of memory are retained.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
D7
D6
D5
D4
D3
D2
D1
D0
−
Data
Status
0
Normal
1
Inverted
Default settings (initial values set by reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
6.22 Partial Start Line Address Register (R21)
The partial start line address register specifies the start line address in the display RAM accessed by the CPU when using
partial display mode. The partial display area is determined as the number of lines specified in the partial display mode
setting register (R10), starting from this start line address.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
−
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
−
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
0
0
0
0
64
Data Sheet S15745EJ2V0DS
µPD16488A
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26)
The gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. Use of
this register optimizes the gray scale display.
Rx
Data
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R23
0, 0
1
−
−
GD5
GD4
GD3
GD2
GD1
GD0
−
R24
0, 1
1
−
−
GD5
GD4
GD3
GD2
GD1
GD0
−
−
GD5
GD4
GD3
GD2
GD1
GD0
−
−
GD5
GD4
GD3
GD2
GD1
GD0
−
R25
1, 0
1
−
R26
1, 1
1
−
D7
D6
D5
D4
D3
D2
D1
D0
Gray scale level
Disable
Disable
0
0
0
0
0
0
Level 0
Disable
Disable
0
0
0
0
0
1
Level 1
Disable
Disable
0
0
0
0
1
0
Level 2
Disable
Disable
0
0
0
0
1
1
Level 3
Disable
Disable
0
1
1
1
1
1
Level 31
Disable
Disable
1
0
0
0
0
0
Level 32
:
:
Default settings (initial values set by reset command, for all gray scale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
0
0
0
0
0
0
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30)
The partial gray scale data registers specify the gray scale level when using partial four-level gray scale display mode.
Use of this register optimizes the gray scale display.
Rx
Data
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R27
0, 0
1
−
−
PGD5
PGD4
PGD3
PGD2
PGD1
PGD0
−
R28
0, 1
1
−
−
PGD5
PGD4
PGD3
PGD2
PGD1
PGD0
−
R29
1, 0
1
−
−
PGD5
PGD4
PGD3
PGD2
PGD1
PGD0
−
R30
1, 1
1
−
−
PGD5
PGD4
PGD3
PGD2
PGD1
PGD0
−
D7
D6
D5
D4
D3
D2
D1
D0
Gray scale level
Disable
Disable
0
0
0
0
0
0
Level 0
Disable
Disable
0
0
0
0
0
1
Level 1
Disable
Disable
0
0
0
0
1
0
Level 2
Disable
Disable
0
0
0
0
1
1
Level 3
:
:
Disable
Disable
0
1
1
1
1
1
Level 31
Disable
Disable
1
0
0
0
0
0
Level 32
Default settings (initial values set by reset command, for all partial gray scale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
0
0
0
0
0
0
Data Sheet S15745EJ2V0DS
65
µPD16488A
6.25 Power System Control Register 1 (R32)
This command sets the µPD16488A's power system mode.
RS
E
/RD
R,/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
HPM1
HPM0
−
TCS1
TCS0
OP2
OP1
OP0
Flag
Function
HPM1, HPM0
These flags set the driver mode as shown in Table 6-9.
TCS1, TCS0
These flags set the value for selecting the VREG voltage's temperature curve, as shown in Table 6-10.
OP2 to OP0
These flags control the booster's ON/OFF status, the voltage regulator (V regulator) and voltage follower (V/F).
The functions controlled via these three bits by the power control setting command are listed in Table 6-11.
Table 6-9. Driver Mode Setting
HPM1
HPM0
0
0
Normal mode
Mode Setting
0
1
Low-power mode
1
0
High-power mode
1
1
Power activation mode
Table 6-10. Selection VREG Voltage's Temperature Curve Value
TCS1
TCS0
Temperature gradient (%/°C)
VREG (TYP.) (V)
0
0
−0.06
1.04
0
1
−0.08
0.98
1
0
−0.09
0.93
1
1
−0.12
0.85
Table 6-11. Detailed Description of Functions Controlled by Flags of Power System Control 1
Status
Item
0
OFF
OP2
Booster control flag
ON
OP1
V regulator control flag
ON
OFF
OP0
Voltage follower control flag
ON
OFF
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
−
0
0
1
1
1
66
1
Data Sheet S15745EJ2V0DS
µPD16488A
6.26 Power System Control Register 2 (R33)
This command is used to control the on-chip register for VLCD voltage regualation.
RS
E
/RD
R,/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
1
0
−
VRR2
VRR1
VRR0
−
PVR2
PVR1
PVR0
−
Flag
Function
VRR2 to VRR0
When using normal display mode, power system control 2 (VLCD regulator resistance factor setting command) can
be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown
in Table 6-12 as reference values for (1 + Rb/Ra).
PVR2 to PVR0
When using partial display mode, power system control 2 (VLCD regulator resistance factor setting command) can
be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown
in Table 6-12 as reference values for (1 + Rb/Ra).
Table 6-12. Reference Values for VLCD Internal Resistance Factor Regulator Register
Register
VRR2
VRR1
VRR0
PVR2
PVR1
PVR0
0
0
0
0
0
1
8
0
1
0
12
0
1
1
13
1
0
0
16
1
0
1
19
1
1
0
21
1
1
1
24
1+Rb/Ra
5
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
0
0
0
−
0
0
0
Data Sheet S15745EJ2V0DS
67
µPD16488A
6.27 Power System Control Register 3 (R34)
This command sets the power system mode, including the bias setting for the µPD16488A's normal display mode and the
number of boost levels for partial display mode.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
BIS2
BIS1
BIS0
FBS2
FBS1
FBS0
BST1
BST0
−
Flag
Function
BIS2 to BIS0 Note
These three flags select the bias ratio as shown below.
BIS2
BIS1
BIS0
Bias ratio
0
0
0
1/12 bias
0
0
1
1/11 bias
0
1
0
1/10 bias
0
1
1
1/9 bias
1
0
0
1/8 bias
1
0
1
1/7 bias
1
1
0
Prohibited
1
1
1
Prohibited
When partial display mode is set, the bias ratio set by the partial mode setting register (R10) is automatically
selected.
Note
FBS2 to FBS0
BST1, BST0
The number of boost levels in booster for normal display mode is selected as shown below.
FBS2
FBS1
FBS0
Boost level
0
0
0
x4
0
0
1
x5
0
1
0
x6
0
1
1
x7
1
0
0
x8
1
0
1
x9
1
1
0
Prohibited
1
1
1
Prohibited
The number of boost levels in the booster for partial display mode is selected as shown below.
BST1
BST0
Boost level
0
0
x2
0
1
x3
1
0
x4
1
1
Prohibited
Note Be sure to execute the HALT command before changing these flag settings.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
68
Data Sheet S15745EJ2V0DS
µPD16488A
6.28 Electronic Volume Register (R35)
The electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display
mode. Any value among 256 steps can be selected.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
EV7
EV6
EV5
EV4
EV3
EV2
EV1
EV0
−
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
6.29 Partial Electronic Volume Register (R36)
The partial electronic volume register specifies the electronic volume value for adjusting the contrast when using partial
display mode. Any value among 256 steps can be selected.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
PEV7
PEV6
PEV5
PEV4
PEV3
PEV2
PEV1
PEV0
−
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
6.30 Boost Adjustment Register (R37)
The voltage (range: 1/8 VDD2 to 7/8 VDD2) set to this register is applied to the boost level set for the booster.
RS
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
−
−
−
−
−
DDC2
DDC1
DDC0
−
Table 6-13. Boost Adjustment Register (R37) Settings
DDC2
DDC1
DDC0
Boost Adjustment Voltage
0
0
0
Regulator Circuit Stopped
0
0
1
1/8 VDD2
0
1
0
2/8 VDD2
0
1
1
3/8 VDD2
1
0
0
4/8 VDD2
1
0
1
5/8 VDD2
1
1
0
6/8 VDD2
1
1
1
7/8 VDD2
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
0
0
0
Data Sheet S15745EJ2V0DS
69
µPD16488A
6.31 RAM Test Mode Setting Register (R44)
The RAM test mode setting register directly writes the data for each type of display mode to the display RAM, as shown in
Table 6-15.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
RTS3
RTS2
RTS1
RTS0
Table 6-15. RAM Test Mode Setting Register (R44) Setting
RTS3
RTS2
RTS1
RTS0
Write Data
0
0
0
0
Normal operation
0
1
0
0
Displays list of gray scales
1
0
0
0
all 00/pixel
1
0
0
1
all 11/pixel
1
0
1
0
Checker pattern: 00/11
1
0
1
1
Checker pattern: 11/00
1
1
0
0
Checker pattern: 01/10
1
1
0
1
Checker pattern: 10/01
1
1
1
0
Vertical striped pattern: 00/11
1
1
1
1
Horizontal striped pattern: 00/11
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
0
0
0
0
6.32 Signature Read Register (R45)
This command is used to read the IC signature set via the SIGIN1 and SIGIN2 pins. This is a read-only register.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
−
−
SIGIN2
SIGIN1
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
70
Data Sheet S15745EJ2V0DS
µPD16488A
7. LIST OF µPD16488A REGISTERS
CS RS 5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Remark
Index Register
4 3 2 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Register Name
IR
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
Index Register
Control register 1
Control register 2
Reset command
X address register
Y address register
Duty setting register
AC driver inversion cycle register
AC driver inversion position shift register
Partial AC driver inversion cycle register
Partial AC driver inversion potision shift register
Partial display mode setting register
Display memory access register
Display start line setting register
Blink X address register
Blink start line address register
Blink end line address register
Blink data memory access register
Inverted X address register
Inversion start line address register
Inversion end line address register
Inverted data memory access register
Partial start line address register
R/W
7
6
5
Data Bits
4
3
2
1
0
W
IR5
IR4
IR3
IR2
IR1
IR0
R/W RMW DISP STBY BLD IVD HALT ADC COMR
R/W FDM
DSEL BWW GRAY DTY INC
CRES
W
R/W
XA4 XA3 XA2 XA1 XA0
R/W
YA6 YA5 YA4 YA3 YA2 YA1 YA0
R/W
DT6 DT5 DT4 DT3 DT2 DT1 DT0
R/W
NID6 NID5 NID4 NID3 NID2 NID1 NID0
W
MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0
W
PID4 PID3 PID2 PID1 PID0
W
PSD4 PSD3 PSD2 PSD1 PSD0
R/W
PBIS
PDT1 PDT0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
DSL6 DSL5 DSL4 DSL3 DSL2 DSL1 DSL0
R/W
BXA3 BXA2 BXA1 BXA0
R/W
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
R/W
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
R/W
IXA3 IXA2 IXA1 IXA0
R/W
ISL6 ISL5 ISL4 ISL3 ISL2 ISL1 ISL0
R/W
IEL6 IEL5 IEL4 IEL3 IEL2 IEL1 IEL0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
Gray scale data register 1 (0, 0)
Gray scale data register 2 (0, 1)
Gray scale data register 3 (1, 0)
Gray scale data register 4 (1, 1)
Patial gray scale data register 1 (0, 0)
Patial gray scale data register 2 (0, 1)
Patial gray scale data register 3 (1, 0)
Patial gray scale data register 4 (1, 1)
W
W
W
W
W
W
W
W
Power system control register 1
Power system control register 2
Power system control register 3
Electronic volume register
Partial electronic volume register
Boost adjustment register
W
W
W
W
W
W
RAM test mode setting register
Signature read register
W
R
HPM1 HPM0
VRR2
BIS2 BIS1
EV7 EV6
PEV7 PEV6
GD5
GD5
GD5
GD5
PGD5
PGD5
PGD5
PGD5
GD4
GD4
GD4
GD4
PGD4
PGD4
PGD4
PGD4
GD3
GD3
GD3
GD3
PGD3
PGD3
PGD3
PGD3
GD2
GD2
GD2
GD2
PGD2
PGD2
PGD2
PGD2
GD1
GD1
GD1
GD1
PGD1
PGD1
PGD1
PGD1
GD0
GD0
GD0
GD0
PGD0
PGD0
PGD0
PGD0
VRR1
BIS0
EV5
PEV5
TCS1
VRR0
FBS2
EV4
PEV4
TSC0 OP2
PVR2
FBS1 FBS0
EV3 EV2
PEV3 PEV2
DDC2
OP1
PVR1
BST1
EV1
PEV1
DDC1
OP0
PVR0
BST0
EV0
PEV0
DDC0
RTS3 RTS2 RTS1 RTS0
SIG2 SIG1
: Not to use these registers.
Data Sheet S15745EJ2V0DS
71
µPD16488A
8. POWER SUPPLY SEQUENCE
The µPD16488A includes power supply circuitry, such as a booster and a voltage follower. When a reset is performed
using the /RES pin, the reset function is restricted so as to prevent operation faults that may occur due to noise effects, etc.
When electric charge remains in the smoothing capacitor that is connected between the VSS pin and the voltage pins
related to the LCD driver (VLCD, VLC1 to VLC4), troubles such as a brief all-black display screen may occur when the power is
switched ON or OFF. The following power-on sequence is recommended as a means to avoid such troubles when
switching the power ON or OFF.
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON → Display ON)
Turn power ON when /RES pin = L
↓
Power supply stabilization
↓
/RES pin = H
↓
Command reset
↓
Control register 1
DISP = 0, HALT = 1
↓

R2
Wait at least 50 µs before command input
Register reset
R0
Display OFF, internal operations stopped
IC functions set via command input
• Control register 1
(DISP = 0, HALT = 1 status is retained)
• Control register 2
• Power control register 1
(HPM1, HPM0 = 1, 1)
• Power control registers 2, 3
• Electronic volume register
• Partial electronic volume register
Specification of power activation mode
• Boost adjustment register
↓
User-specified settings via command input
Duty setting register (R5)
AC driver inversion cycle register (R6)
Function settings for gray scale data, etc.
↓
Initialization complete
↓
Control register 1
DISP = 0, HALT = 0
↓
Make sure to set the duty setting register (R5) and AC
driver inversion cycle register (R6)
R0
LCD display screen settings
• Display start line setting register
• Write screen data, etc. + wait time
↓
Power system control register 1
(Mode except HPM1, HPM0 (1, 1))
↓
Control register 1
DISP = 1, HALT = 0
Note
Display OFF, internal operations started
After internal operations are started, wait at least 400 ms
before turning on the LCD display Note.
Cancels V/F mode for power activation
R0
Display ON, internal operation start mode
This 400 ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the
actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)).
72
Data Sheet S15745EJ2V0DS
µPD16488A
8.2 Power OFF Sequence (When Using On-Chip Power Supply)
Operation mode
↓
DISP = 0, HALT = 0
R0
Display OFF, internal operation start mode
R32
Sets high power mode
R35
[EV7, EV6, EV5, EV4, EV3, EV2, EV1, EV0]
= [0, 0, 0, 0, 0, 0, 0, 0]
R36
[PEV7, PEV6, PEV5, PEV4, PEV3, PEV2, PEV1, PEV0]
= [0, 0, 0, 0, 0, 0, 0, 0]
↓
HPM1 = 1, HPM0 = 0
↓
Set electronic volume register
↓
Set partial electronic volume register
Wait at least 1200 ms before power OFF Note.
↓
Power supply OFF
Note
This 1200 ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. NEC recommends determining the wait time after making a thorough evaluation of the
actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (power ON → power OFF)).
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON)
VDD1, VDD2 power ON, VOUT = Hi-Z
Logic power ON when /RES pin = L
↓
Power supply stabilization
↓

/RES pin = H
↓
Command reset
R2
Wait at least 50 µs befor command input
Register reset
R0
Display OFF, internal operations stopped
↓
DISP = 0, HALT = 1
↓
Power system control register 1 (R32) :
[OP2, OP1, OP0] = [0 ,0 ,X]
Initialization via command input (user-specified)
Selection of IC functions, etc.
↓
DISP = 0, HALT = 0
R0
Display OFF, internal operations started
↓
VOUT power supply ON
External LCD driver power supply ON
↓
Stabilization of external LCD driver power supply
↓
DISP = 1, HALT = 0
R0
Display ON, internal operations started
Data Sheet S15745EJ2V0DS
73
µPD16488A
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply)
Operation mode
↓
DISP = 0, HALT = 0
R0
Display OFF, internal operation start mode
↓
VOUT = Hi-Z
External driver power supply OFF
↓
DISP = 0, HALT = 1
R0
Display OFF, internal operations stopped
↓
Logic power supply OFF
74
VDD1, VDD2, power supply OFF
Data Sheet S15745EJ2V0DS
µPD16488A
8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)
0 VDD
VOUT
/RES pin = 0
Power ON
/RES pin = 1
DISP = 0, HALT = 1
Default settings
HPM = 3
HALT = 0
400 ms
Select HPM = 0 to 2
DISP = 1
Normal display
DISP = 0
HPM = 2
DTY = 1
700 ms
VLCD = 15V 6V
Select HPM = 0 to 2
DISP = 1
Partial display
DISP = 0
HPM = 3
DTY = 0
400 ms
Select HPM = 0 to 2
DISP = 1
Normal display
DISP = 0
HPM = 2
EV = 0
1200 ms
Power OFF
Dotted line: VOUT
Solid line: VLCD
Conditions:
VDD: VDD1 = VDD2 = 3.0 V
Boost levels: x6 (in normal display mode), x3 (in partial display mode)
Capacitors: VLCn pin to Cn+/− pin = 1 µF,
AMPOUT pin, AMPOUTP pin, VRS pin = 0.1 µF
Caution Connect a capacitor of less than 0.1 µF to both AMPOUT and AMPOUTP pins.
Data Sheet S15745EJ2V0DS
75
µPD16488A
9. USE OF RAM TEST MODE
The µPD16488A has a test mode for writing nine types of screen data to display RAM. When using the test mode, be sure
to execute via the sequence shown below. If executing the test mode by some other sequence, troubles may appear in the
screen display.
Operation mode
↓
Control register 1
DISP = 0, STBY = 1
R0
Display OFF, set to standby
R44
Select RAM write data
R0
Display OFF, cancel standby
↓
Set RAM test mode
↓
Control register 1
DISP = 0, STBY = 0
↓
After internal operations are started, wait at least 1 sec
before turning on the LCD display Note.
Wait time
↓
Control register 1
DISP = 1
R0
Display ON
↓
Settings complete
Note
This 1 sec wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the
actual device.
76
Data Sheet S15745EJ2V0DS
µPD16488A
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C, VSS = 0 V)
Parameter
Symbol
Ratings
Unit
Logic system supply voltage
VDD1
−0.3 to +4.0
V
Booster supply voltage
VDD2
−0.3 to +4.0
V
Driver supply voltage
VOUT
−0.3 to +20.0
V
Driver reference supply input voltage
VLCD, VLC1 to VLC4
−0.3 to VOUT+0.3
V
Logic system input voltage
VIN1
−0.3 to VDD1+0.3
V
Logic system output voltage
VOUT1
−0.3 to VDD1+0.3
V
Logic system input/output voltage
VI/O1
−0.3 to VDD1+0.3
V
Driver system input voltage
VIN2
−0.3 to VOUT+0.3
V
Driver system output voltage
VOUT2
−0.3 to VOUT+0.3
V
Operating ambient temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Logic system supply voltage
VDD1
1.7
3.6
V
Booster supply voltage
VDD2 Note1
2.4
3.6
V
Note2
Driver system supply voltage
VOUT
5.5
18.0
V
Logic system input voltage
VIN
0
VDD1
V
Driver system supply voltage
VLCD, VLC1 to VLC4 Note2
0
VOUT
V
VOUT − 0.5
V
Maximum setting for LCD driver voltage
VLCD
Note3
Notes 1. VDD1 must be less than or equal to VDD2
2. This item is the recommended parameter when the LCD has an external driver.
3. This item is the recommended parameter when an on-chip power supply circuit drives the LCD.
Cautions 1. When using an external LCD driver, be sure to maintain these relations:
VSS < VLC4 < VLC3 < VLC2 < VLC1 < VLCD ≤ VOUT.
2. Maintain the relations shown in 8. POWER SUPPLY SEQUENCE when turning the power ON or OFF.
3. When using an external resister (when not using an on-chip resister for VLCD adjustment), maintain
supply of a voltage between 1.0 V and the VDD1 voltage to the VR and VRS pins.
Data Sheet S15745EJ2V0DS
77
µPD16488A
Electrical Characteristics 1
(Unless Otherwise Specified, TA = −40 to +85°°C, VDD1 = 1.7 to 3.6 V, VDD2 = 2.4 to 3.6 V)
Parameter
High-level input voltage
Symbol
Conditions
VIH
MIN.
TYP.Note1
MAX.
0.8 VDD1
Unit
V
Low-level input voltage
VIL
High-level input current
IIH1
Except for D7 (SI), D6 (SCL) and D5 to D0
0.2 VDD1
V
1
µA
Low-level input current
IIL1
Except for D7 (SI), D6 (SCL) and D5 to D0
High-level output voltage
VOH
IOUT = −1 mA except OSCOUT
−1
µA
Low-level output voltage
VOL
IOUT = 1 mA except OSCOUT
0.5
V
High-level leakage current
ILOH
D7 (SI), D6 (SCL) and D5 to D0,
10
µA
−10
µA
4
kΩ
4
kΩ
VDD1 − 0.5
V
VIN/OUT = VDD1
Low-level leakage current
ILOL
D7 (SI), D6 (SCL) and D5 to D0,
VIN/OUT = VSS
Common output ON resistance RCOM
VLCn → COMn, VOUT = 15 V, VLCD = 12 V,
1/10 bias, |IO| = 50 µA
Segment output ON resistance RSEG
VLCn → SEGn, VOUT = 15 V, VLCD = 12 V,
1/10 bias, |IO| = 50 µA
Driver voltage (boost voltage)
VOUT
In x5 boost mode, VDD = 3.0 V,
13.8
V
16.6
V
Checker pattern display
In x6 boost mode, VDD = 3.0 V,
Checker pattern display

Reference voltage
VREG Note2 VDD = 3.0 V, TA = 85°C, TSC1,TSC0 = 1,1
0.720
0.790
0.860
V
(temperature characteristic curves:−0.12%/°C)
Oscillation frequency
fOSCNote3
VDD1 = 3.0 V, TA = 25°C, 1/92 duty,
26.9
kHz
10.6
kHz
in B/W mode, R = 1100 kΩ
VDD1 = 3.0 V, TA = 25°C, 1/38 duty,
in B/W mode, R = 3 MΩ
Notes 1. TYP. values are reference values when TA = 25°C (except VREG).

2. The reference voltage values when TA = 25°C are shown below:
MIN. = 0.775 V, TYP.= 0.850 V, MAX. = 0.925 V

3. The oscillation frequency varies according to the parasitic capacitance of the wiring capacitance. We therefore
recommend determining the oscillation resister’s value after making a thorough evaluation of the actual device.
78
Data Sheet S15745EJ2V0DS
µPD16488A
Electrical Characteristics 2
(Unless Otherwise Specified, TA = −40 to +85°°C)
Parameter
Current consumption
Symbol
IDD11
(normal mode)
Conditions
Frame frequency = 70 Hz,
MIN.
TYP.Note
MAX.
Unit
160
220
µA
210
310
µA
270
390
µA
325
480
µA
115
155
µA
165
230
µA
95
140
µA
105
160
µA
10
µA
B/W all display OFF data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Current consumption
IDD12
(high-power mode)
Frame frequency = 70 Hz,
B/W all display OFF data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Current consumption
IDD13
(low-power mode)
Frame frequency = 70 Hz,
B/W all display OFF data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Current consumption
IDD21
(partial display mode)
Frame frequency = 70 Hz,
B/W all display OFF data output,
1/38 duty, VDD1 = VDD2 = 3.0 V,
in x3 boost mode, VLCD = 7.0 V, normal mode
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/38 duty, VDD1 = VDD2 = 3.0 V,
VLCD = 7.0 V, in x3 boost mode, normal mode
Current consumption
IDD22
VDD1 = VDD2 = 3.0 V
(standby mode)
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15745EJ2V0DS
79
µPD16488A
Required Timing Conditions (Unless Otherwise Specified, TA = −30 to +85°°C)
(1) i80 CPU interface
RS
tAS8
tf
tAH8
tr
/CS1
(CS2 = H)
tCYC8
tCCLW, tCCLR
/WR, /RD
tCCHR, tCCHW
tDS8
tDH8
D0 to D7
(Write)
tOH8
tACC8
D0 to D7
(Read)
When VDD1 = 1.7 V to 2.0 V
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH8
RS
0
ns
Address setup time
tAS8
RS
0
ns
System cycle time
tCYC8
1000
ns
Control low-level pulse width (/WR) tCCLW
/WR
160
ns
Control low-level pulse width (/RD)
tCCLR
/RD
430
ns
Control high-level pulse width (/WR) tCCHW
/WR
160
ns
Control high-level pulse width (/RD) tCCHR
/RD
160
ns
Data setup time
tDS8
D0 to D7
160
ns
Data hold time
tDH8
D0 to D7
0
ns
/RD access time
tACC8
D0 to D7, CL = 100 pF
0
470
ns
Output disable time
tOH8
D0 to D7, CL = 5 pF, R = 3 kΩ
0
170
ns
Note TYP. values are reference values when TA = 25°C.
80
Data Sheet S15745EJ2V0DS
µPD16488A
When VDD1 = 2.0 to 2.5 V
Parameter
Symbol
Conditions
Address hold time
tAH8
RS
Address setup time
tAS8
RS
System cycle time
tCYC8
MIN.
TYP.Note
MAX.
0
Unit
ns
0
ns
600
ns
Control low-level pulse width (/WR) tCCLW
/WR
120
ns
Control low-level pulse width (/RD)
tCCLR
/RD
240
ns
Control high-level pulse width (/WR) tCCHW
/WR
120
ns
Control high-level pulse width (/RD) tCCHR
/RD
120
ns
Data setup time
tDS8
D0 to D7
120
ns
Data hold time
tDH8
D0 to D7
0
/RD access time
tACC8
D0 to D7, CL = 100 pF
0
280
ns
Output disable time
tOH8
D0 to D7, CL = 5 pF, R = 3 kΩ
0
170
ns
MAX.
Unit
ns
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Symbol
Conditions
MIN.
TYP.Note
Address hold time
tAH8
RS
0
ns
Address setup time
tAS8
RS
0
ns
System cycle time
tCYC8
250
ns
Control low-level pulse width (/WR) tCCLW
/WR
60
ns
Control low-level pulse width (/RD)
tCCLR
/RD
120
ns
Control high-level pulse width (/WR) tCCHW
/WR
60
ns
Control high-level pulse width (/RD) tCCHR
/RD
60
ns
Data setup time
tDS8
D0 to D7
60
ns
Data hold time
tDH8
D0 to D7
0
ns
/RD access time
tACC8
D0 to D7, CL = 100 pF
0
140
ns
Output disable time
tOH8
D0 to D5, CL = 5 pF, R = 3 kΩ
0
70
ns
MAX.
Unit
Note TYP. values are reference values when TA = 25°C.
/CS1
(CS2 = H)
tRD
/RD
(VDD1 = 1.8 to 3.6 V)
Parameter
Chip select disable time
Symbol
tRD
Conditions
/RD-CS
MIN.
TYP.Note
10
ns
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
81
µPD16488A
(2) M68 CPU interface
RS
R,/W
tAS6
tf
tr
tAH6
/CS1
(CS2 = H)
tCYC6
tEWHR, tEWHW
E
tEWLR, tEWLW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
When VDD1 = 1.7 to 2.0 V
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH6
RS
0
Address setup time
tAS6
RS
0
ns
ns
System cycle time
tCYC6
1000
ns
Data setup time
tDS6
D0 to D7
160
ns
Data hold time
tDH6
D0 to D7
0
ns
Access time
tACC6
D0 to D7, CL = 100 pF
0
470
ns
Output disable time
tOH6
D0 to D7, CL = 5 pF, R = 3 kΩ
0
170
ns
Read
tEWHR
E
430
ns
Write
tEWHW
E
160
ns
Read
tEWLR
E
160
ns
Write
tEWLW
E
160
ns
Enable high pulse width
Enable low pulse width
Note TYP. values are reference values when TA = 25°C.
82
Data Sheet S15745EJ2V0DS
µPD16488A
When VDD1 = 2.0 to 2.5 V
Parameter
Symbol
Conditions
Address hold time
tAH6
RS
Address setup time
tAS6
RS
System cycle time
tCYC6
MIN.
TYP.Note
MAX.
0
Unit
ns
0
ns
600
ns
ns
Data setup time
tDS6
D0 to D7
120
Data hold time
tDH6
D0 to D7
0
Access time
tACC6
D0 to D7, CL = 100 pF
0
280
ns
0
170
ns
Output disable time
ns
tOH6
D0 to D7, CL = 5 pF, R = 3 kΩ
tEWHR
E
240
ns
Write
tEWHW
E
120
ns
Read
tEWLR
E
120
ns
tEWLW
E
120
ns
Enable high pulse width
Read
Enable low pulse width
Write
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH6
RS
0
ns
Address setup time
tAS6
RS
0
ns
System cycle time
tCYC6
250
ns
Data setup time
tDS6
D0 to D7
60
ns
Data hold time
tDH6
D0 to D7
0
Access time
tACC6
D0 to D7, CL = 100 pF
0
140
ns
0
70
ns
Output disable time
Enable high pulse width
Enable low pulse width
ns
tOH6
D0 to D7, CL = 5 pF, R = 3 kΩ
Read
tEWHR
E
120
ns
Write
tEWHW
E
60
ns
Read
tEWLR
E
60
ns
Write
tEWLW
E
60
ns
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signals (tr and tf) are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) ≤ (tCYC6 − tEWLW − tEWHW) or (tr + tf) ≤ (tCYC6 − tEWLR −
tEWHR).
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
83
µPD16488A
(3) Serial interface
tCSS
tCSH
/CS1
(CS2 = H)
tSAS
tSAH
RS
tSCYC
tSLW
SCL
tf
tSHW
tr
tSDS
tSDH
SI
When VDD1 = 1.7 to 2.5 V
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Serial clock cycle
tSCYC
SCL
250
ns
SCL high-level pulse width
tSHW
SCL
100
ns
SCL low-level pulse width
tSLW
SCL
100
ns
Address hold time
tSAH
RS
150
ns
Address setup time
tSAS
RS
150
ns
Data setup time
tSDS
SI
100
ns
Data hold time
tSDH
SI
100
ns
CS - SCL time
tCSS
CS
150
ns
tCSH
CS
150
ns
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Serial clock cycle
tSCYC
SCL
150
ns
SCL high-level pulse width
tSHW
SCL
60
ns
SCL low-level pulse width
tSLW
SCL
60
ns
Address hold time
tSAH
RS
90
ns
Address setup time
tSAS
RS
90
ns
Data setup time
tSDS
SI
60
ns
Data hold time
tSDH
SI
60
ns
CS - SCL time
tCSS
CS
90
ns
tCSH
CS
90
ns
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
84
Data Sheet S15745EJ2V0DS
µPD16488A
(4) Common
Parameter
Clock input 1
Symbol
fN
Conditions
MIN.
When using OSCIN1, external clock, and
TYP.Note
MAX.
Unit
26.9
150
kHz
53.8
150
kHz
10.6
50
kHz
21.3
50
kHz
TYP.Note
MAX.
Unit
50
200
ns
TYP.Note
MAX.
Unit
20
80
ns
on-chip divider, 1/92 duty, B/W mode
When using OSCIN1, external clock, and
on-chip divider, 1/92 duty,
four-level gray scale mode
Clock input 2
fP
When using OSCIN2, external clock for
partial display mode, but not using on-chip
divider, B/W mode
When using OSCIN2, external clock for
partial display mode, but not using on-chip
divider, four-level gray scale mode
Note TYP. values are reference values when frame frequency = 70 Hz.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
(a) Display control output timing
OSCSYNC
tDFR
FR
(VDD1 = 1.7 to 2.5 V)
Parameter
FR delay time
Symbol
tDFR
Conditions
MIN.
FR, CL = 50 pF
Note TYP. values are reference values when TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
FR delay time
Symbol
tDFR
Conditions
FR, CL = 50 pF
MIN.
Note TYP. values are reference values when TA = 25°C.
Caution All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
85
µPD16488A
(b) Reset timing
tRW
/RES
tR
Internal
status
During reset
Reset complete
When VDD1 = 1.7 to 2.5 V
Parameter
Symbol
Reset time
tR
Reset low pulse width
tRW
Conditions
/RES
MIN.
TYP.Note
MAX.
Unit
50
µs
µs
50
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Symbol
Reset time
tR
Reset low pulse width
tRW
Conditions
/RES
50
Note TYP. values are reference values when TA = 25°C.
Caution All timing is rated based on 20% or 80% of VDD1.
86
MIN.
Data Sheet S15745EJ2V0DS
TYP.Note
MAX.
Unit
50
µs
µs
µPD16488A
11. CPU INTERFACE (REFERENCE EXAMPLE)
The µPD16488A can be connected to either an i80 series CPU or an M68 series CPU. Also, if a serial interface
connection is used, the number of signal lines can be reduced.
If several µPD16488A chip is used, the display area can be enlarged. When using this method, use the chip select signal
to select and access the ICs.
(1) M68 series CPU
VCC
RS
A0
VDD1
A1 to A15
Decoder
C86
/CS1
CPU
D0 to D7
D0 to D7
E
E
R/W
R,/W
/RES
/RES
µPD16488A
VIMA
PSX
VSS
GND
/RESET
(2) i80 series CPU
VCC
RS
A0
VDD1
A1 to A7
CPU
Decoder
C86
/CS1
D0 to D7
D0 to D7
/RD
/RD
/WR
/WR
/RES
/RES
µPD16488A
/IORQ
PSX
VSS
GND
/RESET
Data Sheet S15745EJ2V0DS
87
µPD16488A
(3) When using serial interface
RS
A0
A1 to A7
Decoder
Open
CPU
VDD1
C86
/CS1
D0 to D5
Port1
SI(D7)
/Port2
SCL(D6)
µPD16488A
VCC
PSX
/RES
/RES
VSS
GND
/RESET
88
Data Sheet S15745EJ2V0DS
H or L
µPD16488A
[MEMO]
Data Sheet S15745EJ2V0DS
89
µPD16488A
[MEMO]
90
Data Sheet S15745EJ2V0DS
µPD16488A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15745EJ2V0DS
91