NEC UPD16682AP

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16682A
1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
DESCRIPTION
The µ PD16682A is a LCD controller/driver that includes enough RAM capacity to drive full-dot LCD displays. Each
chip can drive a full-dot LCD display consisting of up to 132 x 65 dots.
This chip is suitable for cellular phones, Japanese or Chinese-language pagers, and other devices that display
Japanese or Chinese characters using either 16 x 16 or 12 x 12 dots per character.
FEATURES
• LCD controller/driver with on-chip display RAM
• Able to operate using +3-V single power supply
• On-chip booster circuit: switchable between 3x and 4x modes
• RAM for dot displays: 132 x 65 bits
• Outputs : 132 segments, 65 commons
• Serial or 8-bit parallel data inputs (switchable between 80 and 68 series CPUs)
• On-chip divider resistor
• Selectable bias settings (can be set as 1/9 or 1/7 bias)
• On-chip oscillation circuit
★ ORDERING INFORMATION
Remark
Part number
Package
µ PD16682AW
Wafer
µ PD16682AP
Chip
Purchasing the above products in term of chips per requires an exchange of other documents as well,
including a memorandum on the product quality. Therefore those who are interested in this regard are
advised to contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S14402EJ1V0DS00 (1st edition)
Date Published February 2001 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999
COM63
COMS
SEG0
SEG131
Remark /xxx indicates active low signals.
VDD
VDD'
VSS
VSS'
CLS
Common Driver
Segment Driver
P,/S
132
1. BLOCK DIAGRAM
2
COM0
/CS1
65 bits Register
CS2
/RD(E)
132 bits latch
132
/WR(R,/W)
D7 (SI)
D6(SCL)
I/O
Buffer
Data
Register
Data Sheet S14402EJ1V0DS
D5 to D0
Display Data RAM
132 x 65 bits
A0
C86
Address Decoder
/RESET
TESTOUT
TEST3
TEST4, TEST5
Command Decoder
TCS1
Timing Generator
TCS2
FRS
FR
CL
/DOF
M,/S
D/A Converter
VRS
C1
−
C2−
−
C3
DC/DC
Converter
OP Amp
LCD Voltage Generator
VDD2
IRS
VLCD
VR
HPM
VLC1
VLC2
VLC3
VLC4
VLC5
µPD16682A
+
C1 ,
+
C2 ,
+
C3 ,
µPD16682A
2. PIN CONFIGURATION (Pad Layout)
Chip Size : 2.66 x 9.84 mm
2
258
125
259
124
X
Y
293
90
1
89
Data Sheet S14402EJ1V0DS
3
µPD16682A
Table 2–1. Pad Layout (1/3)
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
4
Pad Name
DUMMY1
FRS
FR
CL
/DOF
TESTOUT
VSS’
/CS1
CS2
VDD’
/RESET
A0
VSS’
/WR(R,/W)
/RD(E)
VDD’
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VLCD
VLCD
VLCD
C1+
C1+
C1–
C1–
C2+
C2+
C2–
C2–
C3+
C3+
C3–
C3–
VDD’
VDD’
VRS
VRS
VSS’
VSS’
X [µm]
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
Y [µm]
3984.44
3862
3772
3682
3592
3502
3412
3322
3232
3142
3052
2962
2872
2782
2692
2602
2512
2422
2332
2242
2152
2062
1972
1882
1792
1702
1612
1522
1432
1342
1252
1162
1072
982
892
802
712
622
532
442
352
262
172
82
–8
–98
–188
–278
–368
–458
–548
–638
–728
–818
–908
–998
–1088
–1178
Pad
Type
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Pad
No.
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Pad Name
VLC5
VLC5
VLC4
VLC4
VLC3
VLC3
VLC2
VLC2
VLC1
VLC1
VR
VR
VSS’
VSS’
TCS1
TCS2
TEST3
TEST4
TEST5
VDD’
M,/S
CLS
VSS’
C86
P,/S
VDD’
HPM
VSS’
IRS
VDD’
DUMMY2
DUMMY3
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
Data Sheet S14402EJ1V0DS
X [µm]
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1197.68
–1032.44
–940
–880
–820
–760
–700
–640
–580
–520
–460
–400
–340
–280
–220
–160
–100
–40
20
80
140
200
260
320
380
440
500
560
Y [µm]
–1268
–1358
–1448
–1538
–1628
–1718
–1808
–1898
–1988
–2078
–2168
–2258
–2348
–2438
–2528
–2618
–2708
–2798
–2888
–2978
–3068
–3158
–3248
–3338
–3428
–3518
–3608
–3698
–3788
–3878
–4000.44
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
Pad
Type
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
µPD16682A
Table 2–1. Pad Layout (2/3)
Pad
No.
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
Pad Name
COM5
COM4
COM3
COM2
COM1
COM0
COMS
DUMMY4
DUMMY5
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
X [µm]
620
680
740
800
860
920
980
1072.6
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
Y [µm]
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4787.68
–4022.84
–3930.4
–3870.4
–3810.4
–3750.4
–3690.4
–3630.4
–3570.4
–3510.4
–3450.4
–3390.4
–3330.4
–3270.4
–3210.4
–3150.4
–3090.4
–3030.4
–2970.4
–2910.4
–2850.4
–2790.4
–2730.4
–2670.4
–2610.4
–2550.4
–2490.4
–2430.4
–2370.4
–2310.4
–2250.4
–2190.4
–2130.4
–2070.4
–2010.4
–1950.4
–1890.4
–1830.4
–1770.4
–1710.4
–1650.4
–1590.4
–1530.4
–1470.4
–1410.4
–1350.4
–1290.4
–1230.4
–1170.4
–1110.4
–1050.4
Pad
Type
A
A
A
A
A
A
A
C
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad
No.
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
Pad Name
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
Data Sheet S14402EJ1V0DS
X [µm]
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
Y [µm]
–990.4
–930.4
–870.4
–810.4
–750.4
–690.4
–630.4
–570.4
–510.4
–450.4
–390.4
–330.4
–270.4
–210.4
–150.4
–90.4
–30.4
29.6
89.6
149.6
209.6
269.6
329.6
389.6
449.6
509.6
569.6
629.6
689.6
749.6
809.6
869.6
929.6
989.6
1049.6
1109.6
1169.6
1229.6
1289.6
1349.6
1409.6
1469.6
1529.6
1589.6
1649.6
1709.6
1769.6
1829.6
1889.6
1949.6
2009.6
2069.6
2129.6
2189.6
2249.6
2309.6
2369.6
2429.6
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
5
µPD16682A
★
Table 2–1. Pad Layout (3/3)
Pad
No.
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
6
Pad Name
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
DUMMY6
DUMMY7
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
DUMMY8
X [µm]
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1197.68
1032.44
940
880
820
760
700
640
580
520
460
400
340
280
220
160
100
40
–20
–80
–140
–200
–260
–320
–380
–440
–500
–560
–620
–680
–740
–800
–860
–920
–980
–1072.6
Y [µm]
2489.6
2549.6
2609.6
2669.6
2729.6
2789.6
2849.6
2909.6
2969.6
3029.6
3089.6
3149.6
3209.6
3269.6
3329.6
3389.6
3449.6
3509.6
3569.6
3629.6
3689.6
3749.6
3809.6
3869.6
3929.6
4022.2
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
4787.68
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
Remark
Data Sheet S14402EJ1V0DS
Pad Type A:
Pad size (Al): 47 x 105 µm (TYP.)
2
Bump size: 35 x 92.5 µm (TYP.)
2
Bump height: 17 µm (TYP.)
Pad Type B:
Pad size (Al): 75 x 105 µm (TYP.)
2
Bump size: 67 x 92.5 µm (TYP.)
2
Bump height: 17 µm (TYP.)
Pad Type C:
Pad size (Al): 118 x 105 µm (TYP.)
2
Bump size: 110 x 92.5 µm (TYP.)
2
Bump height: 17 µm (TYP.)
µPD16682A
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Pin Symbol
Pin Name
Pad No.
I/O
Description
VDD
Logic power supply pins
25 to 27
—
Power supply pins for logic. Apply the logic power supply
voltage from an external source.
VDD2
Booster circuit power
supply pins
28 to 31
—
Power supply pins for booster circuit. Apply the booster
circuit power supply voltage from an external source.
VSS
Logic/driver ground pins
32 to 37
—
Ground pins for logic and driver circuit. Connect these
pins to an external ground.
VLCD
Driver power supply pins
38 to 40
—
Power supply pins for driver. Output pins for internal
booster circuit.
Connect a 1-µF capacitor for boosting between these pins
and the GND pins.
If not using the internal booster circuit, a direct driver
power supply can be input.
VDD’
Power supply pins for fixed
mode pins
VSS’
Ground pins for fixed
mode pins
VLC1 to VLC5
+
−
+
−
+
−
C1 , C1
C2 , C2
10,16,53,54,
—
These power supply pins are used to set the mode pins as
fixed.
—
These ground pins are used to set the mode pins as fixed.
78,84,88
7,13,57,58,
71,72,81,86
Reference power supply
pins for driver
59 to 68
—
These are reference power supply pins for the LCD driver.
Connect a smoothing capacitor if an internal bias has
been selected.
Capacitor connection pins
41 to 52
—
These are capacitor connection pins for the booster
circuit. Connect a 1-µF capacitor.
C3 , C3
Data Sheet S14402EJ1V0DS
7
µPD16682A
3.2 Logic System Pins (1/3)
Pin Symbol
P,/S
Pin Name
Select data input
Pad No.
I/O
83
Input
Description
This pin is used to select between parallel data input and serial
data input.
P,/S = H : Parallel data input
P,/S = L : Serial data input
This setting cannot be switched after power-on. For details, see
5. DESCRIPTION OF FUNCTIONS.
/CS1,CS2
Chip select
8,9
Input
These pins are used for the chip select signal. When /CS1 = L
and CS2 = H, this signal is active and can be used for I/O of data
and commands.
/RD(E)
Read (enable)
15
Input
• When connected to 80 series CPU : active low
This pin connects the 80 series CPU’s RD signal. Data bus
output status is set when this signal is low.
• When connected to 68 series CPU : active high
It is used as the enable clock input pin for the 68 series CPU.
/WR(R,/W)
Write (read/write)
14
Input
• When connected to 80 series CPU: active low
This pin connects the 80 series CPU's /WR signal. Signals on
the data bus are latched at the rising edge of the /WR signal.
• When connected to 68 series CPU
This pin is an input pin for read/write control signals.
R,/W = H : Read
R,/W = L : Write
C86
Interface select
82
Input
This pin is used to select the CPU interface.
C86 = H : 68 series CPU interface
C86 = L : 80 series CPU interface
D0 to D5
Data bus
17 to 22
D6 (SCL)
Data bus/serial clock
23
D7 (SI)
Data bus/serial data input
24
A0
Data command
12
Input When used with a parallel interface, these pins correspond to
/Output data bus bits D0 to D5.
When used with a serial interface, they are pulled down
internally.
Input When used with a parallel interface, this pin corresponds to data
/Output bus bit D6.
When used with a serial interface, it is a serial clock input pin.
Input
When used with a parallel interface, this pin corresponds to data
/Output bus bit D7.
When used with a serial interface, it is a serial data input pin.
Input
This pin is connected to the LSB in the ordinary CPU address
bus to distinguish between data and commands.
A0 = H : Indicates that display data exists in bits D0 to D7.
A0 = L : Indicates that display control commands exist in bits D0
to D7.
TESTOUT
Test output
6
Output This pin is used as a test output. Leave this pin open when used
for this purpose.
/RESET
Reset
11
Input
This pin is used to perform an internal reset when at low level.
CLS
Clock select
80
Input
This pin is used to select the valid/invalid setting for the display
clock’s on-chip oscillation circuit.
CLS = H : On-chip oscillation circuit is valid
CLS = L : On-chip oscillation circuit is invalid (external input)
When CLS = L, a display clock is input via the CL pin.
8
Data Sheet S14402EJ1V0DS
µPD16682A
3.2 Logic System Pins (2/3)
Pin Symbol
Pin Name
Pad No.
I/O
Description
FR
Frame signal
3
Input This pin is used as an I/O pin for the LCD’s AC conversion
/Output signal.
This pin is used (along with the FRS pin) for the static drive.
FRS
Static signal
2
Output This pin is used as an output pin for the static drive.
M,/S
Master/Slave
79
This pin is used (along with the FR pin) for the static drive.
Input
This pin is used to select master or slave operation mode.
Timing signals required for the LCD are output during master
mode and are input during slave mode to ensure synchronization
of the LCD block.
M,/S = H: Master operation mode
M,/S = L: Slave operation mode
Note the settings below, based on the status of the M,/S and
CLS pins.
M,/S
H
L
CL
Display clock input
4
CLS
CL
FR
FRS
/DOF
Circuit
Power
supply
circuit
H
Valid
Valid
L
Invalid
Valid
H
Invalid Invalid
Input
Input
Hi-Z
Input
L
Invalid Invalid
Input
Input
Hi-Z
Input
Oscillation
Output Output Output Output
Input
Output Output Output
Input
This pin is used as the display clock I/O pin. Note the settings
/Output below, based on the status of the M,/S and CLS pins.
M,/S
CLS
CL
H
H
Output
L
Input
H
Input
L
Input
L
When using this pin in master or slave mode, connect it to the
corresponding CL pin.
/DOF
Blink control
5
Input
/Output
This pin is used to control blinking in the LCD.
M,/S = H : Output
M,/S = L : Input
When using this pin in master or slave mode, connect it to the
corresponding /DOF pin.
HPM
Power supply circuit select
pin for LCD driver
85
Input
This pin is used as a power control pin of the power supply circuit
for the LCD driver.
HPM = H : Normal mode
HPM = L : High-power mode
IRS
Select pin for VLC1
regulating resistor
87
Input
This pin is used to select the resistor that is used to regulate the
VLC1 voltage.
IRS = H : Select on-chip resistor
IRS = L : Do not select on-chip resistor. The VLC1 voltage is
regulated via the VR pin and an external divided
resistor.
Use of the on-chip resistor cannot be selected or deselected via
a hard reset or via a reset command. Instead, use this pin to
select the setting.
Data Sheet S14402EJ1V0DS
9
µPD16682A
3.2 Logic System Pins (3/3)
Pin Symbol
★ TCS1,TCS2
TEST3
Pin Name
Temperature gradient
select
Test pins
TEST4,TEST5 Test pins
10
Pad No.
I/O
73,74
Input
Description
These pins are used to select temperature gradient.
Note the temperature gradient below, based on the status of the
TCS1, TCS2.
75
76,77
Input
TCS2
TCS1
Temperature gradient (% / °C)
L
L
–0.09
L
H
0
H
L
–0.05
H
H
–0.14
These are test pins for IC tests. Normally, these pins should be
left open.
Output These are test pins for IC tests. Normally, these pins should be
left open.
Data Sheet S14402EJ1V0DS
µPD16682A
3.3 Driver System Pins
Pin Symbol
Pin Name
SEG0 to SEG131
Segment
COM0 to COM63
Common
Pad No.
I/O
Description
126 to 257
Output
Segment output pins
91 to 122,
Output
Common output pins
123,292
Output
Common output pins for indicator
55,56
Input
260 to 291
COMS
Indicator common
VRS
Op amp inputs
The same signal is output from pin 2.
These are input pins for the op amp that regulates the LCD
driver voltage.
Leave the VRS pin open when using the on-chip power supply.
69,70
VR
When not using the on-chip power supply, a reference voltage
VREG must be input.
When using an external power supply, connect the VR pin to a
resistor used to regulate the LCD voltage.
DUMMY1 to
DUMMY8
Dummy pins
1,89,90,124,125,
258,259,293
—
Since these pins are not connected to any internal circuits, they
should be left open when they are not being used.
Data Sheet S14402EJ1V0DS
11
µPD16682A
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in the following
table.
I/O
Pin Name
Recommended Connection of Unused Pins
Notes
P,/S
Input
Mode setting pin
1
/CS1
Input
Connect to VSS
CS2
Input
Connect to VDD
/RD(E)
Input
Connect to VDD (80 series interface),
/WR (R,/W)
Input
Connect to VDD or VSS (serial interface)
C86
Input
Mode setting pin
1
D0 to D5
Input/Output
Leave open (when using serial interface)
2
D6 (SCL)
Input/Output
D7 (SI)
Input/Output
A0
Input
Data/command setting pin
3
TESTOUT
Output
Leave open
/RESET
Input
Connect to VDD
CLS
Input
Mode setting pin
FR
Input/Output
Leave open (when using master mode, M,/S = H)
FRS
Output
Leave open
/DOF
Input/Output
Leave open (when using master mode, M,/S = H)
M,/S
Input
Mode setting pin
1
CL
Input/Output
Display clock
4
HPM
Input
Mode setting pin
1
IRS
Input
Mode setting pin
1
TCS1
Input
Mode setting pin
1
TCS2
Input
Mode setting pin
1
TEST3
Input
Leave open
2
TEST4
Output
Leave open
TEST5
Output
Leave open
connect to VDD or VSS (serial interface)
1
Notes 1. Connect to VDD or VSS according to the selected mode.
2. These pins are pulled down to VSS in the IC.
3. Input CPU output from VDD or VSS according to the selected register.
4. This pin is an output when M,/S = H and CLS = H but should otherwise be used to input the display clock.
12
Data Sheet S14402EJ1V0DS
µPD16682A
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface
5.1.1 Select interface type
The µ PD16682A transfers data either via an 8-bit bidirectional data bus (D7 to D0) or via a serial data input (SI).
The P,/S pin can be set to either high or low levels to select 8-bit parallel data input or serial data input, as shown
in the table below.
P,/S
/CS1
CS2
A0
/RD
/WR
C86
D7
D6
D5 - D0
H: Parallel input
/CS1
CS2
A0
/RD
/WR
C86
D7
D6
D5 -D0
L: Serial input
/CS1
CS2
A0
Note 1
Note 1
Note1
SI
SCL
Note2
Notes 1. Fix this pin as either H or L.
2. High impedance
5.1.2 Parallel interface
If the parallel interface has been selected (P,/S = H), setting the C86 pin either high or low determines whether to
connect directly to the 80 series CPU or the 68 series CPU, as shown in the table below.
P,/S
/CS1
CS2
A0
/RD
D7 - D0
H: 68 series CPU bus
/CS1
CS2
A0
E
D7 - D0
L: 80 series CPU bus
/CS1
CS2
A0
/RD
D7 - D0
The data bus signal can be identified according to the combination of A0, /RD(E), and /WR (R,/W) signals, as
shown in the table below.
Common
68 Series
A0
R,/W
H
H
80 Series
Function
/RD
/WR
H
L
H
Read display data
L
H
L
Write display data
L
H
L
H
Read status
L
L
H
L
Write control data (command)
Data Sheet S14402EJ1V0DS
13
µPD16682A
(1) 80 Series Parallel Interface
When 80 series parallel data transfer has been selected, data is written to the µ PD16682A at the rising edge of the
/WR signal. The data is output to the data bus when the /RD signal is L.
Figure 5–1 80 Series Interface Data Bus Status
/CS1
(CS2=H)
/WR
/RD
Hi-Z
Hi-Z
Valid data
DBn
Data write
Data read
(2) 68 Series Parallel Interface
When 68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the
R,/W signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H,
outputs valid data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the
R,/W signal (R,/W = L)
Figure 5–2 68 Series Interface Data Bus Status
/CS1
(CS2=H)
R,/W
Hi-Z
E
Hi-Z
DBn
14
Hi-Z
Invalid data
Valid data
Data Sheet S14402EJ1V0DS
µPD16682A
5.1.3 Serial interface
If the serial interface has been selected (P,/S = L) and if the chip is in the active state (/CS1 = L and CS2 = H),
both serial data input (SI) and serial clock input (SCL) can be received. The serial interface includes an 8-bit shift
register and a 3-bit counter. Serial data is captured at the rising edge of the serial clock and is clocked in via the
serial data input pins in sequence from D7 to D0. At the rising edge of the eighth serial clock, data is converted to
8-bit parallel data.
Input via the A0 pin can be used to determine whether the input serial data is display data or a command (display
data when A0 = H, command when A0 = L). The timing for reading and identifying input via A0 occurs at the rising
edge of the “eighth x n” serial clock once the chip’s status is active.
A serial interface signal chart is shown below.
Figure 5–3. Serial Interface chart
/CS1
CS2
SI
SCL
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A0
Remarks 1. When the chip’s status is inactive, the shift register and counter are both reset to their initial
values.
2. Data cannot be read when using the serial interface.
3. For the SCL signal, caution is advised concerning the wire’s terminating reflection and noise from
external sources. We recommend to check the operation on the actual equipment.
5.1.4 Chip select
The µ PD16682A has two chip select pins (/CS1 and CS2). The CPU interface or serial interface can be used
only when /CS1 = L and CS2 = H.
When the chip select pin is inactive, D7 to D0 are set to high impedance (invalid) and input of A0, /RD, or /WR is
invalid. If the serial interface has been selected, the shift register and counter are both reset.
5.1.5 Display data RAM and internal register access
Access to the µ PD16682A from the CPU supports high-speed data transfers since the cycle time (tCYC) is met
and there is no need for wait time.
When data transfer occurs between the µ PD16682A and the CPU, the data is held in a bus holder belonging to
the internal data bus and is written to the display data RAM before the next data write cycle. When the CPU reads
the contents of the display data RAM, the data read during the first data read cycle (dummy cycle) is first held in
the bus holder and is read from the bus holder to the system bus during the next data read cycle.
Note with caution that, due to constraints on the read sequence for the display data RAM, when the address is
set, the data is not output from the address specified by the next read command but rather is output to the address
specified during the second data read operation. Consequently, one dummy read operation is strictly required after
setting an address or after a write cycle. Figure 5–4 illustrates this situation.
Data Sheet S14402EJ1V0DS
15
µPD16682A
Figure 5–4. Write and Read Operations
Writing
CPU
/WR
DATA
N
N+1
Internal Timing
N+2
N+3
Latch
BUS
N
Holder
N+1
N+2
N+3
Write
Signal
Reading
CPU
/WR
/RD
DATA
N
N
n
n+1
Internal Timing
Address
Preset
Read
Signal
Column
Preset N
Address
BUS
N
Holder
Address Set
#n
16
increment N+1
n
Dummy
Read
Data Sheet S14402EJ1V0DS
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
µPD16682A
6. DISPLAY DATA RAM
6.1 Display Data RAM
This is the RAM that is used to store the display’s dot data. The RAM configuration is 65 (8 pages x 8 bits + 1) x
132 bits. Any specified bit can be accessed by selecting the corresponding page address and column address.
As is shown in Figure 6–1 below, the display data (D7 to D0) from the CPU corresponds to the common direction in
the LCD, so that if a multiple set of µ PD16682A chips is used, there are fewer constraints on transfers of display
data and relatively more freedom for display configurations.
The CPU accesses the display data RAM for read/write operations via the I/O buffer, and these operations are
independent of the LCD driver signal read operations. Therefore, there are absolutely no adverse effects (such as
flicker) in the display when display data RAM is accessed asynchronously in relation to the LCD contents.
Figure 6–1. LCD Data and LCD Display
LCD data
LCD display
D0
0
1
1
1
0
COM0
D1
1
0
0
0
0
COM1
D2
0
0
0
0
0
COM2
D3
0
1
1
1
0
COM3
D4
1
0
0
0
0
COM4
...
...
6.2 Page Address Circuit
The page address set command specifies the page address in the display data RAM, as is shown in Figure 6–2. To
access a different page, simply specify a different page address using this command.
Page address 8 (D3,D2,D1,D0 = 1,0,0,0) is a RAM area that is used exclusively for indicator, so only display data D0
is valid.
6.3 Column Address Circuit
The column address set command specifies the column address in the display data RAM, as is shown in Figure
6–2. The specified column address is incremented each time a display data read or write command is input, so the
CPU is able to successively access display data.
Incrementation of the column address stops at 83H. The column address and page address are mutually
independent, which means that to switch from column 83H on page 0 to column 00H on page 1, both the page
address and column address must be separately specified again.
Also, as is shown in Table 6–1, the ADC command (segment driver direction select command) can be used to invert
the correspondence between the display data RAM’s column address and segment output. This reduces the number
of IC layout constraints that are imposed when setting up the LCD module.
Table 6–1. Relation between Display Data RAM Column Address and Segment Output
SEG Output
SEG0
SEG131
ADC
“0”
00H
→
Column Address
→
83H
(D0)
“1”
83H
←
Column Address
←
00H
Data Sheet S14402EJ1V0DS
17
µPD16682A
6.4 Line Address Circuit
As is shown in Figure 6–2, the line address circuit specifies the line address that corresponds to a COM output for
displaying the contents of display data RAM. The display start line address set command usually specifies the
highest line in the display (corresponding to the COM0 output when in normal mode or the COM63 output when in
inverted mode). Thus, there are 65 lines in the direction of incrementation of line address starting from the specified
display start line address.
The screen can be scrolled by dynamically changing the line address via the display start line address set
command.
Figure 6–2. Specification of Display Start Line Address in Display Data RAM
Page Address
D3 D2 D1 D0 Data
1
1
0
0
0
Page7
Page8
ADC
1
Note COMS accesses the 65th line regardless of the display start line address.
18
Data Sheet S14402EJ1V0DS
Column
Address
1
0
0
Page6
D0 D0
0
1
1
Out
1
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS Note
Start
LCD
0
Page5
SEG131 00 83
1
SEG130 01 82
0
SEG129 02 81
1
SEG128 03 80
0
Page4
SEG127 04 7F
0
SEG126 05 7E
0
SEG125 06 7D
1
SEG124 07 7C
0
Page3
7C 07
1
7D 06
1
SEG7
0
7E 05
0
Page2
SEG6
0
7F 04
1
SEG5
0
80 03
0
Page1
SEG4
1
81 02
0
SEG3
0
82 01
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page0
SEG2
0
83 00
0
SEG1
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
SEG0
0
Line
Address Common output status :
Normal mode
µPD16682A
6.5 Display Data Latch Circuit
The display data latch circuit is used for temporary storage of display data that has been output to the LCD driver
circuit from the display data RAM.
The commands that are used to set normal/inverted display modes, display ON/OFF status, and display all ON/OFF
status are commands that control data in this latch so that there is no modification of the data in the display data
RAM.
7. OSCILLATION CIRCUIT
This is a CR-type oscillation circuit that generates the display clock. The oscillation circuit is valid only when CLS =
H. When CLS = L, oscillation is stopped and the display clock is input via the CL pin.
8. DISPLAY TIMING GENERATOR
The display timing generator generates timing signals from the display clock to the line address circuit and the
display data latch circuit. Display data is latched into the display data latch circuit in synch with the display clock and
is output via segment driver output pins. Reading of the display data is completely independent of the CPU’s
accessing of the display data RAM. Consequently, there are no adverse effects (such as flicker) on the LCD panel
even when the display data RAM is accessed asynchronously in relation to the LCD contents.
The internal common timing and LCD’s AC conversion signal (FR) are both generated from the display clock. As is
shown in Figure 8–1, a drive waveform based on the two-frame AC drive method is generated for the LCD driver
circuit.
If a multiple set of µPD16682A chips is used, the display timing signals (FR, CL, and /DOF) for the slave side must
be supplied from the master side.
Operation Mode
Master (M,/S = H)
Slave (M,/S = L)
FR
CL
/DOF
On-chip oscillation circuit is valid (CLS = H)
Output
Output
Output
On-chip oscillation circuit is invalid (CLS = L)
Output
Input
Output
On-chip oscillation circuit is invalid (CLS = H)
Input
Input
Input
On-chip oscillation circuit is invalid (CLS = L)
Input
Input
Input
Data Sheet S14402EJ1V0DS
19
µPD16682A
Figure 8–1. Drive Waveform when Using Two-Frame AC Drive Method
1Frame
1
2
3
4
5
6
7
8
63 64 65 1
CL
FR
RAM
DATA
VLC1
VLC2
VLC3
SEG1
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COM0
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COM1
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COMS
VLC4
VLC5
VSS
20
Data Sheet S14402EJ1V0DS
2
3
4
5
6
7
8
63 64 65
µPD16682A
9. COMMON OUTPUT STATUS SELECT CIRCUIT
With the µ PD16682A, the common output status select command can be used to set the scan direction for COM
outputs (see Table 9–1). As a result, there are fewer IC layout constraints when setting up the LCD module.
Table 9–1. Setting of Scan Direction for COM Outputs
Status
COM Scan Direction
Normal (forward)
COM0
→
COM63
Inverted (reverse)
COM63
→
COM0
10. POWER SUPPLY CIRCUIT
10.1 Power Supply Circuit
The power supply circuit, which supplies the voltage needed to drive the LCD, includes a booster circuit, voltage
regulator circuit, and voltage follower circuit.
The power control set command is used to control the ON/OFF status of the power supply circuit’s booster circuit,
voltage regulator circuit (V regulator circuit), and voltage follower circuit (V/F circuit). This makes it possible to jointly
use an external power supply along with certain functions of the on-chip power supply. Table 10–1 shows the
function that controls the 3-bit data in the power control set command and Table 10–2 shows a reference chart of
combinations.
Table 10–1. Control Values Set to Bits in Power Control Set Command
Item
Status
H
L
D2
Booster circuit control bit
ON
OFF
D1
Voltage regulator circuit control bit
ON
OFF
D0
Voltage follower circuit control bit
ON
OFF
Table 10–2. Reference Chart of Combinations
Use Status
D2
D1
D0
Booster
V Regulator
Circuit
Circuit
V/F Circuit
External Power
Booster-
Supply Input
related Pin
<1> Use on-chip power supply
H
H
H
¡
¡
¡
VDD2
Used
<2> Use V regulator circuit
L
H
H
×
¡
¡
VLCD
Open
<3> Use V/F circuit only
L
L
H
×
×
¡
VLC1
Open
<4> Use External power
L
L
L
×
×
×
VLC1 to VLC5
Open
and V/F circuit only
supply only
+
–
+
–
+
–
Remarks 1. The booster-related pins are indicated as pins C1 , C1 , C2 , C2 , C3 , and C3 .
2. Although combinations other than those shown above are possible, they have no practical uses and
therefore cannot be recommended.
Data Sheet S14402EJ1V0DS
21
µPD16682A
10.2 Booster circuit
3x and 4x booster circuits have been incorporated in chip to generate the current driving the LCD.
+
–
+
–
When using the internal power supply, connect the booster-related capacitor between C1 and C1 , C2 and C2 , and
+
–
C3 and C3 . Also, connect the level stabilization-related capacitor between VLCD and VSS and set D2 high to boost the
potential between VDD2 and VSS from 3 to 4 times.
Since the booster circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating.
The relation between the boosted voltage and the potential is described below.
+
–
+
–
+
–
The C1 , C1 , C2 , C2 , C3 , C3 , and VDD2 pins all relate to the booster circuit, so the wire impedance should be
minimized.
Figure 10–1. 3x and 4x Booster Circuits
VLCD = 4VDD2 = 12 V
(During 4x boost mode)
VLCD = 3VDD2 = 9 V
(During 3x boost mode)
VDD2 = 3 V
VSS = 0 V
Caution When set to 3x boost mode, connect booster-related capacitors
–
+
+
–
between C2 and C3 and between C1 and C1 .
10.3 Voltage Regulator Circuit
The boost voltage that was generated at VLCD is output via the voltage regulator circuit as the LCD drive voltage
VLC1. Since the µ PD16682A has a 64-level electronic volume function and an on-chip resistor for VLC1 voltage
regulation, various components can be used to configure a highly accurate voltage regulator circuit.
10.3.1 Use of on-chip resistor for VLC1 voltage regulation
The on-chip resistor for VLC1 voltage regulation and the electronic volume function can be used to regulate the
darkness of the LCD contents, not only by adding an external resistor but also by controlling the LCD drive voltage
VLC1 by using commands only. The VLC1 voltage can be determined using equation 10–1 as within the range of VLC1 <
VLCD.
22
Data Sheet S14402EJ1V0DS
µPD16682A
★
Equation 10–1
VLC1 = (1 +
Rb
)VEV
Ra
The equation for determining VEV varies according to the temperature gradient.
VEV =
162 (1– α )VREG (–0.05% / °C)
202
162
VEV =
162 (1– α )VREG (–0.09% / °C)
179
162
VEV = (1– α )VREG (–0.14% / °C)
162
VEV =
162 (1– α )VREG (0% / °C)
232
162
+
VLC1
–
VEV (Constant voltage source + electronic volume)
Rb
Ra
VREG is the IC’s internal constant voltage source, whose voltage values (at TA = 25°C) are listed in Table 10–3
below.
★
Table 10–3. VREG
TCS2
TCS1
Temperature Gradient (%/°C)
VREG (V)
L
L
–0.09
1.87
L
H
0
2.41
H
L
–0.05
2.10
H
H
–0.14
1.69
Given α as the electronic volume command value, when data is set to the 6-bit electronic volume register, one of 64
statuses is set. Values for α corresponding to various electronic volume register settings are listed in Table 10–4
below.
Table 10–4. α Values Determined by Electronic Volume Register Settings
D5
D4
D3
D2
D1
D0
α
0
0
0
0
0
0
63
0
0
0
0
0
1
62
0
0
0
0
1
1
61
0
0
0
0
1
1
60
:
:
:
:
:
:
:
1
1
1
1
0
1
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Data Sheet S14402EJ1V0DS
23
µPD16682A
Rb/Ra is an on-chip resistance factor used for the VLC1 voltage regulator. This factor can be controlled among eight
levels using the VLC1 voltage regulator resistance factor set command. Table 10–5 lists reference values for
(1+Rb/Ra) which are set when 3-bit data is set to the VLC1 voltage regulator resistance factor register.
Table 10–5. Reference Values for (1 + Rb/Ra)
Register
Reference Value
D3
D2
D1
0
0
0
3.5
0
0
1
4.0
0
1
0
4.5
0
1
1
5.0
1
0
0
5.5
1
0
1
6.0
1
1
0
6.5
1
1
1
7.0
10.3.2 When using external resistor (not using on-chip resistor for VLC1 voltage regulator)
Instead of using the on-chip resistor for the VLC1 voltage regulator (IRS pin = L), resistors (Ra’ and Rb’) can be
added between VSS and VR and between VR and VLC1 to set the LCD power supply voltage VLC1. In such cases, the
electronic volume function can be used to control the LCD power supply voltage VLC1 using commands to regulate
the darkness of the LCD contents. The VLC1 voltage can be determined using equation 10–2 as within the range of
VLC1 < VLCD.
★
Equation 10–2
VLC1 = (1 +
Rb'
)VEV
Ra'
The equation for determining VEV varies according to the temperature gradient.
VEV =
162 (1– α )VREG (–0.05% / °C)
202
162
VEV =
162 (1– α )VREG (–0.09% / °C)
179
162
α )VREG (–0.14% / °C)
VEV = (1–
162
VEV =
162 (1– α )VREG (0% / °C)
232
162
+
VLC1
–
VEV (Constant voltage source + electronic volume)
VR
Ra'
24
Data Sheet S14402EJ1V0DS
Rb'
VLC1
µPD16682A
10.4 Op Amp Control for Level Power Supply
The µPD16682A’s on-chip power supply circuit is designed for low power consumption (HPM = H). Consequently,
display quality may be diminished when a large LCD device or panel is used. In such cases, the display quality can
be improved by setting HPM = L (high-power mode). We recommend that you check the actual display quality before
deciding whether or not to use high-power mode.
If setting high-power mode still does not sufficiently improve the display quality, the LCD driver’s power supply must
be provided from an external source.
10.5 Command Sequence for Stepping Down On-chip Power Supply
As shown in the following command sequence, we recommend that you set low power mode and turn off the power
before stepping down the on-chip power supply.
Step
Description
(Command, Status)
Command Address
D7
D6
D5
D4
D3
D2
D1
D0
Step1
Display OFF
1
0
1
0
1
1
1
0
Power save command
Step2
Display all ON
1
0
1
0
0
1
0
1
(compound)
End
On-chip power supply
OFF
Data Sheet S14402EJ1V0DS
25
µPD16682A
10.6 Use Example of Power Supply Circuit
A) 4x boost (normal mode/using on-chip power supply)
To logic system power supply
B) 3x boost
To booster circuit power supply
VDD
IRS
HPM
VDD2
VLCD
VRS
+
C4
VLCD
Open
+
VR
C1+
C4
Open
+
VLC1
C1
+
+
C1
+
VLC2
C1
−
C1
+
C2
C1
+
VLC3
Open
+
C2
+
VLC4
−
C2 + Note
C2 −
−
C2
C3 +
+
+
VLC5
C2
+
C3 +
C3
+
−
C3
Open
C3
− Note
VSS
VSS
+
–
Note Leave the C2 and C3 pins open.
Remark C1 = C2 = C3 = C4 = 1.0 µF
26
Data Sheet S14402EJ1V0DS
µPD16682A
11. RESET CIRCUIT
In the µ PD16682A, when the /RESET input is at low level, a reset is executed. The reset (default) settings are
described below.
1. Display OFF
2. Normal display direction
3. ADC select: normal direction (ADC command D0 =L)
4. Power control register: (D2,D1,D0) = (0,0,0)
5. Data cleared from register in serial interface
6. LCD power supply bias: 1/9 bias
7. Read modify write OFF
8. Power save canceled
9. SEG/COM output: VSS
10. Static indicator OFF
Static indicator register: (D2,D1) = (0,0)
11. Display start line: set to line 1
12. Column address: set to address 0
13. Page address: set to page 0
14. Common output status: Normal
15. Canceled mode set for on-chip resistance factor for VLC1 voltage regulator
VLC1 voltage regulator resistance factor register (D2,D1,D0) = (0,0,0)
16. Canceled mode set for electronic volume register
Electronic volume register: (D5,D4,D3,D2,D1,D0) = (1,0,0,0,0,0)
17. Test mode canceled
18. Display all OFF (display all ON/OFF command, D0 = L)
Only items 1, 7, and 9 to 18 above are executed when a reset command is used.
Data Sheet S14402EJ1V0DS
27
µPD16682A
12. COMMANDS
The µ PD16682A uses a combination of A0, /RD(E), and /WR(R,/W) to identify data bus signals. Command
interpretation and execution is performed using internal timing that does not depend on any external clock.
The 80 series CPU interface activates commands using low pulse input to the /RD pin during read and activates
commands using low pulse input to the /WR pin during write. The 68 series CPU interface sets read mode using
high-level input to the R,/W pin and sets write mode using low-level input to the R,/W pin. The command is activated
using high pulse input to the E pin.
Thus, the 68 series CPU interface differs from the 80 series CPU interface in that /RD(E) is at high level during
status read and display data read operations, as is shown in the command descriptions and command table.
Command descriptions using an 80 series CPU interface are shown below.
If the serial interface has been selected, data is input sequentially starting from D7.
12.1 Display ON/OFF
This command specifies the display’s ON/OFF status.
A0
E,/RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
0
1
0
1
0
1
1
1
1
Display ON
0
Display OFF
Executing the display all ON command while the display is OFF sets power save (low power) mode. For details, see
12.20 Power Save (Compound Command).
When the display is OFF, output via all driver outputs (segment and common) is at VSS level.
12.2 Display Start Line Set
This command specifies the address of the display start line in the display data RAM, as was shown in Figure 6–2.
The display area extends from the specified line address in the direction of higher line addresses, and includes the
number of lines that corresponds to the display duty setting. The display can be smoothly scrolled vertically by using
this command to dynamically modify the specified line addresses.
For details, see 6.4 Line Address Circuit.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Line Address
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
↓
28
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Data Sheet S14402EJ1V0DS
µPD16682A
12.3 Page Address Set
This command specifies the page address corresponding to the row address when accessing the display data RAM
from the CPU side, as was shown in Figure 6–2. The specified bit in display data RAM can be accessed by selecting
the corresponding page address and column address. If the page address is changed, the display mode does not
change.
For details, see 6.2 Page Address Circuit.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Page
Address
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
↓
↓
0
1
1
1
7
1
0
0
0
8
12.4 Column Address Set
This command specifies the column address in display data RAM, as was shown in Figure 6–2. The column
address is set in a (basically continuous) series of two specifications, one for the high-order four bits and another for
the low-order four bits. The column address is automatically incremented (+1) each time the display data RAM is
accessed, so the CPU is able to continuously read or write display data. Incrementation of the column address stops
at 83H. At that point the page address can no longer be continuously modified. For details, see 6.3 Column
Address Circuit.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
1
A7
A6
A5
A4
0
A3
A2
A1
A0
A7
A6
A5
A4
A3
A2
A1
A0
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
↓
↓
1
0
0
0
0
0
1
0
130
1
0
0
0
0
0
1
1
131
Data Sheet S14402EJ1V0DS
29
µPD16682A
12.5 Status Read
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
ADC
ON/OFF
RESET
0
0
0
0
ADC
This indicates the relation between the column address and the segment driver.
0: Inverted (column address 131-n←→SEGn)
1: Normal (column address n←→SEGn)
ON/OFF
ON/OFF: Indicates the display’s ON/OFF status.
0: Display ON
1: Display OFF
(This is the opposite of the display ON/OFF command's polarity.)
RESET
This indicates whether or not the system is undergoing a reset via the /RESET
signal or the reset command.
0: Operating mode
1: Reset in progress
12.6 Display Data Write
This command writes 8 bits of data to the specified address in display data RAM. After this data has been written,
the column address is automatically incremented (+1), which enables the CPU to continuously write display data.
A0
E, /RD
R,/W, /WR
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write Data
12.7 Display Data Read
This command reads 8 bits of data from the specified address in display data RAM. After this data has been read,
the column address is automatically incremented (+1), which enables the CPU to continuously read several words of
data.
A single dummy read operation is required immediately after the column address has been set. For details, see
5.1.5 Display data RAM and internal register access.
Note that the display data cannot be read when using a serial interface.
30
A0
E, /RD
R,/W, /WR
1
0
1
D7
D6
D5
D4
D3
Read Data
Data Sheet S14402EJ1V0DS
D2
D1
D0
µPD16682A
12.8 ADC Select (Segment Driver Direction Select)
This command inverts the relation between the display data RAM’s column address and segment driver output, as
was shown in Figure 6–2. Consequently, the segment driver output pin number can be inverted by this command.
For details, see 6.3 Column Address Circuit. Incrementation (+1) of the column address when display data is
either written or read is performed according to the column address shown in Figure 6–2.
This command should be input during initialization.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
0
1
0
1
0
1
1
0
0
0
D0
Setting
0
Normal (forward direction)
1
Inverted (reverse direction)
12.9 Display Normal/Inverted
This command can be used to invert the display ON/OFF control without replacing any of the display data RAM
contents. The display data RAM contents are retained when this command is executed.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
1
0
Setting
RAM data: H
LCD ON potential (normal)
1
RAM data: L
LCD ON potential (inverted)
12.10 Display All ON/OFF
This command can be used to set the display all ON status forcibly regardless of the display data RAM contents.
The display data RAM contents are retained when this command is executed.
This command takes priority over the display normal/inverted command.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
0
1
0
1
0
0
1
0
0
Normal display mode
1
Display all ON
12.11 LCD Bias Set
This command selects the bias setting of the voltage required to drive the LCD. This command is valid when the
power supply circuit’s V/F circuit is operating.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
0
1
0
1/9 bias
1
1/7 bias
Data Sheet S14402EJ1V0DS
Setting
31
µPD16682A
12.12 Read Modify Write
This command is used in a pair with the end command. When this command has been input, the column address is
not changed by the display data read command and can be incremented (+1) only by the display data write
command. This status is retained until an end command is input. Once an end command has been input, the
column address returns to the address that was used when the read modify write command was input. This function
can be used to lighten the burden on the CPU when repeatedly modifying data in special display areas such as the
blinking cursor.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
Caution
The commands other than the display data read/write commands can be used even
during read modify write mode. However, the column address set command cannot be used.
Figure 12–1. Sequence for Cursor Display
Page address set
Column address set
Read modify write
Dummy read
Data read
Data write
No
Changes completed?
Yes
End
32
Data Sheet S14402EJ1V0DS
Data processing
µPD16682A
12.13 End
This command is used to cancel read modify write mode and return to the address that was used during column
address mode reset.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
Figure 12–2. End
Return
N
Column Address
N+1
N+2
N+3
N+m
N
End
Read Modify Write Mode Set
12.14 Reset
This command initializes the contents of the various command registers. The display data RAM is not affected. For
details, see 11. RESET CIRCUIT.
The reset operation is performed after the reset command has been input.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
0
The reset that occurs when the power supply is applied is performed by issuing a reset signal to the /RESET pin. It
cannot be used as a substitute for the reset command.
12.15 Common Output Status Select
This command can be used to select the scan direction for the COM output pins. For details, see 9. COMMON
OUTPUT STATUS SELECT CIRCUIT.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
0
0
X
X
X
1
Remark
Setting
Normal (forward)
Inverted (reverse)
X: Don't care
Status
Selected status
Normal (forward)
COM0
→
COM63
Inverted (reverse)
COM63
→
COM0
Data Sheet S14402EJ1V0DS
33
µPD16682A
12.16 Power Control Set
This command is used to set the function of the power supply circuit. For further description, see 10. POWER
SUPPLY CIRCUIT.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Selected Status
0
1
0
0
0
1
0
1
0
X
X
Booster circuit: OFF
1
X
X
Booster circuit: ON
X
0
X
V regurator circuit: OFF
X
1
X
V regurator circuit: ON
X
X
0
V/F circuit: OFF
X
X
1
V/F circuit: ON
Remark
X: Don’t care
12.17 Set On-chip Resistance Factor for VLC1 Voltage Regulator
This command is used to set the on-chip resistance factor for the VLC1 voltage regulator. For details, see 10.3
Voltage Regulator Circuit.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
(1+Rb/Ra)
0
1
0
0
0
1
0
0
0
0
0
3.5
0
0
1
4.0
0
1
0
4.5
0
1
1
5.0
1
0
0
5.5
1
0
1
6.0
1
1
0
6.5
1
1
1
7.0
12.18 Electronic Volume (Two-Byte Command)
This command can be used to control the LCD drive voltage VLC1 (which is output from the on-chip LCD power
supply’s voltage regulator circuit) to regulate the darkness of the LCD contents.
This command is a two-byte command that is used in a pair with the electronic volume mode set command and the
electronic volume register set command, so be sure to use both commands consecutively.
12.18.1 Electronic volume mode set command (first byte)
Once this command is input, the electronic volume register set command becomes valid. And once the electronic
volume mode has been set, any command other than the electronic volume register set command cannot be used.
This restriction is cleared once data has been set to the register by the electronic volume register set command.
34
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
0
0
0
1
Data Sheet S14402EJ1V0DS
µPD16682A
12.18.2 Electronic volume register set command (second byte)
When six bits of data are set to the electronic volume register by this command, the LCD drive voltage VLC1 is set
to one of 64 possible voltage values.
Once this command has been input and the electronic volume register has been set, electronic volume mode is
canceled.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
VLC1
0
1
0
X
X
0
0
0
0
0
0
Smaller value
X
X
0
0
0
0
0
1
X
X
0
0
0
0
1
0
X
X
1
1
1
1
1
0
X
X
1
1
1
1
1
1
↓
Remark
Larger value
X: Don’t Care
Figure 12–3. Sequence of Electronic Volume Register Set Operations
Electronic volume mode set
Electronic volume register set
Cancel electronic volume mode
No
Changes completed?
Yes
12.19 Static Indicator (Two-Byte Command)
This command is used to control the indicator display for the static drive system. Only this command can control the
static indicator display, and it operates independently of other display control commands.
One of the electrodes for the static indicator’s LCD driver is connected to the FR pin and the other is connected to
the FRS pin. We recommend that these status indicator electrodes be implemented in a pattern that is separate from
the electrodes used for the dynamic drive. The LCD and the electrodes themselves may deteriorate if the patterns
are laid out too close to each other.
The static indicator ON command is a two-byte command that is used in a pair with the static indicator register set
command, so be sure to use both commands consecutively. (The static indicator OFF command is a one-byte
command.)
Data Sheet S14402EJ1V0DS
35
µPD16682A
12.19.1 Static indicator ON/OFF
When the static indicator ON command is input, the static indicator register set command becomes valid. Once
the static indicator ON command has been input, any command other than the static indicator register set
command cannot be used. This restriction is cleared once data has been set to the register by the static indicator
register set command.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Static Indicator
0
1
0
1
0
1
0
1
1
0
0
OFF
1
ON
12.19.2 Static indicator register set
This command sets data to the two-bit static indicator register and then sets the static indicator to blink mode.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
Static Indicator
0
1
0
X
X
X
X
X
X
0
0
OFF
0
1
ON (blinks at onesecond interval)
1
0
ON (blinks at halfsecond interval)
1
1
ON (always ON)
Figure 12–4. Sequence of Static Indicator Register Set Operations
Static indicator ON
Static indicator register set
Cancel static indicator mode
No
Changes completed?
Yes
12.20 Power Save (Compound Command)
The current consumption can be greatly reduced by entering the power save status by inputting the display all ON
command while the display is in OFF mode.
The power save (low power) mode includes two modes; sleep mode and standby mode. Turning the static indicator
OFF sets sleep mode and turning it ON sets standby mode.
During either sleep mode or standby mode, the display data is retained as it was before the power save function
was activated. Also, access to the display data RAM from the CPU is possible during either mode.
Use the display all OFF command to cancel power save mode.
36
Data Sheet S14402EJ1V0DS
µPD16682A
Figure 12–5. Power Save
Static indicator ON
Static indicator OFF
Power save (compound command)
Static indicator ON
Sleep mode
Standby mode
Reset command
Power save OFF
(Display all OFF command)
Power save OFF
(Display all OFF command)
Cancel standby mode
Cancel sleep mode
12.20.1 Sleep mode
During this mode, all LCD operations are stopped and there is no access from the CPU, so current consumption
can be reduced almost as low as the static current level. The internal status during sleep mode is as follows.
(1) The oscillation circuit and LCD power supply circuit are stopped.
(2) All LCD drive circuits are stopped and both segment and common driver outputs output at the VSS level.
12.20.2 Standby mode
During this mode, all duty LCD display system operations are stopped and only the static drive system for the
indicators operate, which reduces the current consumption to the minimum amount needed for static drive. The
internal status during standby mode is as follows.
(1) The LCD’s power supply circuit is stopped. The oscillation circuit operates.
(2) The duty drive system’s LCD drive circuit is stopped and both segment and common driver outputs output at
the VSS level. The static drive system operates.
When a reset command is executed while in standby mode, it sets sleep mode.
Remarks1. If you are using an external power supply, we recommend that you stop the external power supply
circuit’s functions when activating the power save function. For example, if you are using an external
divided resistor circuit to provide LCD drive voltage at different levels, we recommend that you add a
circuit to cut the current flowing on the divided resistor circuit while the power save function is being
activated.
2. The µ PD16682A includes the /DOF pin which is used to control blinking LCD displays is set to low
level when activating the power save function. The output from /DOF can be used to stop the external
power supply circuit's function.
3. When the display has been set to OFF mode, executing the display all ON command sets power save
mode no matter which command is entered afterward.
Data Sheet S14402EJ1V0DS
37
µPD16682A
12.21 NOP
This command is used to set NOP (Non-Operation) mode.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
1
12.22 Test
This command is used for IC testing. Do not use this command. If you use it by mistake, either set the /RESET
input low or use the reset command or NOP command to cancel the test command setting.
A0
E, /RD
R,/W, /WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
1
X
X
X
X
Remark
38
X: Don’t care
Data Sheet S14402EJ1V0DS
µPD16682A
Table 12–1. List of µ PD16682A Commands (1/2)
Command
Display ON/OFF
Display start line set
Command code
Function
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
0
Sets LCD’s ON/OFF status
1
0: OFF, 1: ON
0
1
0
0
1
Display start address
Sets display RAM’s
display start line address
Page address set
0
1
0
1
0
1
1
Page address
Sets display RAM’s page
address
Column address set
0
1
0
0
0
0
1
High-order column address
(high-order bits)
Sets high-order four bits
of display RAM’s column
address
Column address set
0
1
0
0
0
0
0
Low-order column address
(low-order bits)
Sets low-order four bits
display RAM’s column
address
Status read
0
0
1
0
Display data write
1
1
0
Write data
Writes to display RAM
Display data read
1
0
1
Read data
Reads from display RAM
ADC select
0
1
0
1
Status
0
1
0
0
0
0
0
0
0
0
Read status information
0
Sets correspondence of
1
SEG output to display
RAM address
0: Normal, 1: Inverted
Display
0
1
0
1
0
1
0
0
1
1
normal/inverted
Display all ON/OFF
0
1
0
1
0
1
0
0
1
0
0
Sets normal/inverted
1
direction of display
0
Sets display all ON
1
0: Normal display, 1: All
ON
LCD bias set
0
1
0
1
0
1
0
0
0
1
0
Sets the bias setting of
1
the LCD drive voltage
0: 1/9 bias, 1: 1/7 bias
Read modify write
0
1
0
1
1
1
0
0
0
0
0
Specifies incrementation
of the column address
During write: +1,
During read: 0
End
0
1
0
1
1
1
0
1
1
1
0
Cancels read modify write
Reset
0
1
0
1
1
1
0
0
0
1
0
Sets an internal reset
Selects scan
0
1
0
1
1
0
0
0
X
X
X
Selects scan direction for
1
X
X
X
COM outputs
direction for COM
outputs
0: Normal (forward),
1: Inverted (reverse)
Remark X: Don’t care
Data Sheet S14402EJ1V0DS
39
µPD16682A
Table 12–1. List of µ PD16682A Commands (2/2)
Command
Power control set
Command code
Function
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
0
1
0
0
0
1
0
1
Operation mode
D1
D0
Selects operation mode
of internal power supply
Sets VLC1 output
0
1
0
0
0
1
0
0
Resistance factor
voltage to electronic
setting
resistance factor for
volume register
Electronic volume
Selects on-chip
(Ra/Rb)
0
1
0
1
0
0
0
0
0
0
1
mode set
Sets VLC1 output voltage
to electronic volume
Electronic volume
0
1
0
X
X
0
1
0
1
0
Electronic volume value
register
register set
Static indicator
1
0
1
1
0
0
ON/OFF
0: OFF, 1: ON
1
Static indicator
0
1
0
X
X
X
X
X
X
Mode
Sets ON mode
register set
Power save
Compound command for
setting display OFF and
all display ON
NOP
0
1
0
1
1
1
0
0
0
1
1
Command for NonOperation mode
Test
0
1
0
1
1
1
1
X
X
X
X
Command used for IC
testing
Caution Do not use this
command.
Remark
40
X: Don't care
Data Sheet S14402EJ1V0DS
µPD16682A
13. ACCESS PROCEDURE
13.1 Instruction setting example
13.1.1 Initialization setting example (from power application to display ON)
Although a VSS level is output from the SEG and COM LCD drive output pins when power is applied to the IC, if
there is electric charge remaining in the smoothing capacitor connected between the driver reference power supply
pins (VLC1 to VLC5) and VSS, or if the DC/DC converter's booster voltage does not reach the prescribed booster
potential or the levels of the reference power supplies (VLCn) do not reach the prescribed voltages when power is
applied, abnormalities such as a temporary screen blackout may occur when the display turns on.
The following power application flow is recommend to avoid the occurrence of abnormal operation when the
power is turned on.
Power supply between VDD/VDD2 and VSS ON
when /RESET pin in L state
Power supply stabilization
Reset state release (/RESET pin = H)
Initial settings stateNote1
User settings via command input (1)
LCD bias set Note2
ADC select Note3
Common output status selection Note4
User settings via command input (2)
Set on-chip resistance factor for VLC1 voltage regulator Note5
Electronic volume Note6
User settings via command input (3)
Power control set Note7
End of initial settings
LCD display screen settings
Display start line set Note8
Writing screen data, etc.
Be sure to allow at least 700 ms between
power control set and display ON (when the
VLC1 to VLC5 smoothing capacitor is 0.22 µF or less).Note10
Display ONNote9
Data Sheet S14402EJ1V0DS
41
µPD16682A
Notes 1. See 11. RESET CIRCUIT.
2. See 12.11 LCD Bias Set.
3. See 12.8 ADC Select (Segment Driver Direction Select).
4. See 12.15 Common Output Status Select.
5. See 12.17 Set On-chip Resistance Factor for VLC1 Voltage Regulator.
6. See 12.18 Electronic Volume (Two-Byte Command).
7. See 12.16 Power Control Set.
8. See 12.2 Display Start Line Set.
9. See 12.1 Display ON/OFF.
10. This period changes depending on the panel characteristics and the capacitance of the booster/smoothing
capacitor. It is recommended to determine this value after sufficient evaluation using the actual device.
13.1.2 Example of power OFF
When turning the power of the IC off in the normal operation state (liquid crystal display ON, on-chip power supply
circuits operating), because there is electric charge remaining in the power supply level smoothing capacitor
connected between the driver reference power supply pins (VLC1 to VLC5) and VSS, power continues to be supplied
to the LCD drive circuit and voltage may be applied to the LCD panel from the SEG and COM pins. At this time,
the LCD panel may momentarily display data.
Moreover, because the visual quality of the LCD panel may be affected, be sure to turn off the power to the IC in
the following sequence.
Normal operation state
Command input
Power save Note1
Reset (/RESET pin = L )Note2
Power supply between VDD/VDD2 and VSS OFF
Notes1. See 12.20 Power Save (Compound Command).
2. Application of a reset is optional.
42
Data Sheet S14402EJ1V0DS
µPD16682A
14. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Parameter
★
Symbol
Rating
Unit
Supply voltage
VDD
–0.3 to +6.0
V
Supply voltage 2 (4x boost)
VDD2
−0.3 to +3.75
V
Supply voltage 2 (3x boost)
VDD2
−0.3 to +5.0
V
Driver supply voltage
VLCD
−0.3 to +15.0, VDD ≤ VLCD
V
Driver reference supply input voltage
VLC1 to VLC5
−0.3 to VLCD+0.3
V
Logic system input voltage
VIN1
−0.3 to VDD+0.3
V
Logic system output voltage
VOUT1
−0.3 to VDD+0.3
V
Logic system input/output voltage
VI/O1
−0.3 to VDD+0.3
V
Driver system input voltage
VIN2
−0.3 to VLCD+0.3
V
Driver system output voltage
VOUT2
−0.3 to VLCD+0.3
V
Operating ambient temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−55 to +150
°C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Supply voltage
VDD
1.8
4.5
V
Supply voltage 2 (4x boost)
VDD2
2.4
3.0
V
Supply voltage 2 (3x boost)
VDD2
2.4
4.0
V
Driver supply voltage
VLCD
6
12
V
Logic system input voltage
VIN
0
VDD
V
Driver system input voltage
VLC1 to VLC5
0
VLCD
V
10
Remarks 1. When using an external power supply, be sure to maintain these relations:
VSS < VLC5 < VLC4 < VLC3 < VLC2 < VLC1 ≤ VLCD
2. Maintain VDD ≤ VLCD when turning the power on or off.
Data Sheet S14402EJ1V0DS
43
µPD16682A
Electrical Characteristics (unless otherwise specified, TA = −40 to +85°°C, VDD = 2.7 to 3.3 V, during 4x boost
mode: VDD2 = 2.7 to 3.0 V,or VDD2 = 2.7 to 4.0 V )
Parameter
Symbol
High-level input voltage
VIH
Low-level input voltage
VIL
High-level input current
IIH1
Low-level input current
Condition
MIN.
TYP.Note
MAX.
0.8 VDD
Unit
V
0.2 VDD
V
Except for D7(SI), D6(SCL), and D5 to D0
1
µA
IIL1
Except for D7(SI), D6(SCL), and D5 to D0
−1
µA
High-level output voltage
VOH
IOUT = −1.5 mA, except OSCOUT
Low-level output voltage
VOL
IOUT = 4 mA, except OSCOUT
0.5
V
High-level leakage current
ILOH
D7(SI), D6(SCL), and D5 to D0
10
µA
Low-level leakage current
ILOL
−10
µA
Common output ON resistance
RCOM
VLCn → COMn, VLCD ≥ 3VDD2, ILOL = 50 µA
2
kΩ
Segment output ON resistance
RSEG
VLCn → SEGn, VLCD ≥ 3VDD2, ILOL = 50 µA
4
kΩ
Driver voltage (boost voltage)
VLCD
During 3x boost
2.7 VDD
3.0 VDD
V
During 4x boost
3.6 VDD
4.0 VDD
V
60
110
µA
90
135
µA
105
190
µA
155
230
µA
7
15
µA
0.2
5
µA
22
25
kHz
VDD − 0.5
V
VIN/OUT = VDD
D7(SI), D6(SCL), and D5 to D0
VIN/OUT = VSS
Current consumption
IDD11
fOSC = 22 kHz, all display OFF data
output, VDD = VDD2 = 3.0 V during
(normal mode)
3x boost mode, TA = 25°C
fOSC = 22 kHz, all display OFF data
output, VDD = VDD2 = 3.0 V during
4x boost mode, TA = 25°C
Current consumption
IDD12
fOSC = 22 kHz, all display OFF data
output, VDD = VDD2 = 3.0 V during
(high-power mode)
3x boost mode, TA = 25°C
fOSC = 22 kHz, all display OFF data
output, VDD = VDD2 = 3.0 V during
4x boost mode, TA = 25°C
Current consumption
IDD21
Current consumption
fOSC = 22 kHz, VDD = VDD2 = 3.0 V,
TA = 25°C
(standby mode)
IDD22
VDD = VDD2 = 3.0 V, TA = 25°C
fOSC
TA = 25°C, VDD = VDD2 = 3.0 V ± 10%
(sleep mode)
Oscillation frequency
Note The TYP. value is a reference value when TA = 25°C.
44
Data Sheet S14402EJ1V0DS
17
µPD16682A
Required timing conditions (unless otherwise specified, TA = −40 to +85°°C)
80 Series CPU
A0
tAS8
tf
tr
tAH8
/CS1
(CS2=H)
tCYC8
tCCLW, tCCLR
/WR, /RD
tCCHR, tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Data Sheet S14402EJ1V0DS
45
µPD16682A
(VDD = 2.7 to 4.5 V )
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH8
A0
0
ns
Address setup time
tAS8
A0
0
ns
System cycle time
tCYC8
300
ns
Control L pulse /width (/WR)
tCCLW
/WR
60
ns
Control L pulse width (/RD)
tCCLR
/RD
120
ns
Control H pulse width (/WR)
tCCHW
/WR
60
ns
Control H pulse width (/RD)
tCCHR
/RD
60
ns
Data setup time
tDS8
D0 to D7
40
ns
Data hold time
tDH8
D0 to D7
15
ns
/RD access time
tACC8
D0 to D7, CL = 100 pF
Output disable time
tOH8
D0 to D7, CL = 100 pF
10
140
ns
100
ns
MAX.
Unit
Note The TYP. value is a reference value when TA = 25°C.
(VDD = 2.4 to 2.7 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note
Address hold time
tAH8
A0
0
ns
Address setup time
tAS8
A0
0
ns
System cycle time
tCYC8
1000
ns
Control L pulse width (/WR)
tCCLW
/WR
120
ns
Control L pulse width (/RD)
tCCLR
/RD
240
ns
Control H pulse width (/WR)
tCCHW
/WR
120
ns
Control H pulse width (/RD)
tCCHR
/RD
120
ns
Data setup time
tDS8
D0 to D7
80
ns
Data hold time
tDH8
D0 to D7
30
ns
/RD access time
tACC8
D0 to D7, CL = 100 pF
Output disable time
tOH8
D0 to D7, CL = 100 pF
10
280
ns
200
ns
Note The TYP. value is a reference value when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC8–tCCLW –tCCHW ) or (tr + tf) < (tCYC8–tCCLW –tCCHR).
2. All timing is rated based on 20% or 80% of VDD.
3. tCCLW and tCCLR are rated as the overlap time when /CS1 is at low level (CS2 = H) and /WR and /RD are
also at low level.
4. D0 to D7 change to output regardless of the state of the E signal when R,/W becomes H in the state of
/CS1 = L, CS2 = H (See 5.1.2 (2) 68 Series Parallel Interface.).
46
Data Sheet S14402EJ1V0DS
µPD16682A
68 Series CPU
A0
R,/W
tAS6
tf
tr
tAH6
/CS1
(CS2=H)
tCYC6
tEWHR, tEWHW
E
tEWLR, tEWLW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Data Sheet S14402EJ1V0DS
47
µPD16682A
(VDD = 2.7 to 4.5 V )
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH6
A0
0
ns
Address setup time
tAS6
A0
0
ns
System cycle time
tCYC6
300
ns
Data setup time
tDS6
D0 to D7
40
ns
Data hold time
tDH6
D0 to D7
15
ns
Access time
tACC6
D0 to D7, CL = 100 pF
Output disable time
tOH6
D0 to D7, CL = 100 pF
10
ns
Read
tEWHR
E
120
ns
Write
tEWHW
E
60
ns
Read
tEWLR
E
60
ns
Write
tEWLW
E
60
ns
Enable H pulse width
Enable L pulse width
140
ns
Note The TYP. value is a reference value when TA = 25°C.
(VDD = 2.4 to 2.7 V )
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH6
A0, R,/W
0
ns
Address setup time
tAS6
A0, R,/W
0
ns
System cycle time
tCYC6
1000
ns
Data setup time
tDS6
D0 to D7
80
ns
Data hold time
tDH6
D0 to D7
30
ns
Access time
tACC6
D0 to D7, CL = 100 pF
Output disable time
tOH6
D0 to D7, CL = 100 pF
10
ns
Read
tEWHR
E
240
ns
Write
tEWHW
E
120
ns
Read
tEWLR
E
120
ns
Write
tEWLW
E
120
ns
Enable H pulse width
Enable L pulse width
280
ns
Note The TYP. value is a reference value when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) ≤ (tCYC6–tEWLW –tEWHW ) or (tr + tf) ≤ (tCYC6–tEWLR–tEWHR).
2. All timing is rated based on 20% or 80% of VDD.
3. tEWHW and tEWLW are rated as the overlap time when /CS1 is at low level (CS2 = H) and E is at high
level.
48
Data Sheet S14402EJ1V0DS
µPD16682A
Serial Interface
tCSS
tCSH
/CS1
(CS2=H)
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tf
tSHW
tr
tSDS
tSDH
SI
Data Sheet S14402EJ1V0DS
49
µPD16682A
(VDD = 2.7 to 4.5 V )
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Shift clock cycle
tSCYC
SCL
250
ns
SCL H pulse width
tSHW
SCL
100
ns
SCL L pulse width
tSLW
SCL
100
ns
Address setup time
tSAS
A0
150
ns
Address hold time
tSAH
A0
150
ns
Data setup time
tSDS
SI
100
ns
Data hold time
tSDH
SI
100
ns
CS-SCL time
tCSS
/CS1,CS2
150
ns
tCSH
/CS1,CS2
150
ns
Note The TYP. value is a reference value when TA = 25°C.
(VDD = 2.4 to 2.7 V )
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Shift clock cycle
tSCYC
SCL
400
ns
SCL H pulse width
tSHW
SCL
150
ns
SCL L pulse width
tSLW
SCL
150
ns
Address setup time
tSAS
A0
250
ns
Address hold time
tSAH
A0
250
ns
Data setup time
tSDS
SI
150
ns
Data hold time
tSDH
SI
150
ns
CS-SCL time
tCSS
/CS1,CS2
250
ns
tCSH
/CS1,CS2
250
ns
Note The TYP. value is a reference value when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD.
Common
Parameter
Oscillation frequency
Symbol
fCL
Conditions
CL, When using external input,
MIN.
TYP.Note
MAX.
Unit
17
22
25
kHz
TA = 25°C, VDD = VDD2 = 3.0 V ± 10%
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less.
2. The frame time can be determined using the following equation.
1 frame = 1/fOSC or 1/fCL x 4 x duty value
Therefore, when fOSC and fCL = 22 kHz and the duty value is 1/65:
1 frame = 45.5 µs x 4 x 65 = 11.8 ms (approximately 84.6 kHz)
50
Data Sheet S14402EJ1V0DS
µPD16682A
Output timing for display output control
CL
(out)
tDFR
FR
(VDD = 2.7 to 4.5 V )
Parameter
FR delay time
Symbol
tDFR
Conditions
MIN.
FR, CL = 50 pF
TYP.Note
MAX.
Unit
20
80
ns
TYP.Note
MAX.
Unit
50
200
ns
Note The TYP. value is a reference value when TA = 25°C.
(VDD = 2.4 to 2.7 V )
Parameter
FR delay time
Symbol
tDFR
Conditions
FR, CL = 50 pF
MIN.
Note The TYP. value is a reference value when TA = 25°C.
Remark
All timing is rated based on 20% or 80% of VDD.
Data Sheet S14402EJ1V0DS
51
µPD16682A
Reset input timing
tRW
/RESET
tR
Internal
status
During reset
Reset completed
(VDD = 2.7 to 4.5 V )
Parameter
Symbol
Reset time
tR
Reset L pulse width
tRW
Conditions
/RESET
MIN.
TYP.Note
MAX.
Unit
1.0
µs
µs
1.0
Note The TYP. value is a reference value when TA = 25°C.
(VDD = 2.4 to 2.7 V )
Parameter
Symbol
Reset time
tR
Reset L pulse width
tRW
Conditions
/RESET
Note The TYP. value is a reference value when TA = 25°C.
Remark
52
All timing is rated based on 20% or 80% of VDD.
Data Sheet S14402EJ1V0DS
MIN.
1.5
TYP.Note
MAX.
Unit
1.5
µs
µs
µPD16682A
[MEMO]
Data Sheet S14402EJ1V0DS
53
µPD16682A
[MEMO]
54
Data Sheet S14402EJ1V0DS
µPD16682A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14402EJ1V0DS
55