NEC UPD161602B

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD161602A/B
360/396-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD161602A/B is a source driver for TFT-LCDs supporting 64 gray-scale display and can operate with a
supply voltage of 2.5 V for the logic block and 5.0 V for the driver block. Data input as 6-bit x 3-dot digital data is
output as 64 γ -corrected values using an internal D/A converter and 5 external power modules, thus achieving a
260,000-color (full-color) display. In addition, the difference with A articles and B articles is only a difference in
γ compensation resistance.
FEATURES
• CMOS level input
• 360/396 outputs
• Input of 6 bits (gray-scale data) by 3 dots
• Capable of outputting 64 values by means of 5 external power modules and a D/A converter
• Output dynamic range: VSS2 to VDD2
• High-speed data transfer: fCLK = 15 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.5 V)
• Level inversion γ -correction power supply is possible
• Logic power supply voltage (VDD1): 2.2 to 3.6 V
• Driver power supply voltage (VDD2): 4.5 to 5.5 V
★ ORDERING INFORMATION
Part Number
Package
µ PD161602AP
Chip
µ PD161602BP
Chip
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15381EJ1V0DS00 (1st edition)
Date Published May 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
©
2001
µPD161602A/B
★ 1. BLOCK DIAGRAM
STHR
R,/L
STHL
VDD1
VSS1
132-bit bidirectional shift register
C1
CLK
C2
C131
C132
INV
INBUF
D00 to D05
D10 to D15
D20 to D25
Data register
Osel
STB
Mode
control
CM
POL
Latch
AP
VCsel
VCOM
BUF
VCOM
V0 to V4
GAM
Level shifter
γ
control
D/A converter
BIAS
control
Output buffer
VDD2
VSS2
VDD1
TESTIN
TESTO1
TESTO2
BA
S1
S2
S3
Remark /xxx indicates active low signal.
★
2
Data Sheet S15381EJ1V0DS
S396
µPD161602A/B
2. PIN CONFIGURATION (Pad Layout)
Chip size: 16980 x 1620 µm
2
Bump size (Input/VCOM/test/dummy): 86 x 80 µm
Bump size (Output): 33 x 120 µm
2
2
Alignment Mark (µm)
X: –8284.4 Y: 600
X: 8284.4 Y: 600
1
397
510
398
509
Y(-
X(+
500
407
60 µm
408
72 µm
499
72 µm
60 µm
72 µm
72 µm
Driver output pad
40 µm plover
120 µm
33 µm
Input/VCOM/test/dummy
pad
86 µm
35.5 µm
Bump size
3960 µm2
80 µm
Bump size
6880 µm
2
Data Sheet S15381EJ1V0DS
3
µPD161602A/B
Table 2–1. Pad Layout (1/3)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
4
Pad Name
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
X [µ m]
7900.0
7860.0
7820.0
7780.0
7740.0
7700.0
7660.0
7620.0
7580.0
7540.0
7500.0
7460.0
7420.0
7380.0
7340.0
7300.0
7260.0
7220.0
7180.0
7140.0
7100.0
7060.0
7020.0
6980.0
6940.0
6900.0
6860.0
6820.0
6780.0
6740.0
6700.0
6660.0
6620.0
6580.0
6540.0
6500.0
6460.0
6420.0
6380.0
6340.0
6300.0
6260.0
6220.0
6180.0
6140.0
6100.0
6060.0
6020.0
5980.0
5940.0
5900.0
5860.0
5820.0
5780.0
5740.0
5700.0
5660.0
5620.0
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
No.
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Pad Name
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
X [µ m]
5580.0
5540.0
5500.0
5460.0
5420.0
5380.0
5340.0
5300.0
5260.0
5220.0
5180.0
5140.0
5100.0
5060.0
5020.0
4980.0
4940.0
4900.0
4860.0
4820.0
4780.0
4740.0
4700.0
4660.0
4620.0
4580.0
4540.0
4500.0
4460.0
4420.0
4380.0
4340.0
4300.0
4260.0
4220.0
4180.0
4140.0
4100.0
4060.0
4020.0
3980.0
3940.0
3900.0
3860.0
3820.0
3780.0
3740.0
3700.0
3660.0
3620.0
3580.0
3540.0
3500.0
3460.0
3420.0
3380.0
3340.0
3300.0
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
Data Sheet S15381EJ1V0DS
No.
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
Pad Name
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173
S174
X [µ m]
3260.0
3220.0
3180.0
3140.0
3100.0
3060.0
3020.0
2980.0
2940.0
2900.0
2860.0
2820.0
2780.0
2740.0
2700.0
2660.0
2620.0
2580.0
2540.0
2500.0
2460.0
2420.0
2380.0
2340.0
2300.0
2260.0
2220.0
2180.0
2140.0
2100.0
2060.0
2020.0
1980.0
1940.0
1900.0
1860.0
1820.0
1780.0
1740.0
1700.0
1660.0
1620.0
1580.0
1540.0
1500.0
1460.0
1420.0
1380.0
1340.0
1300.0
1260.0
1220.0
1180.0
1140.0
1100.0
1060.0
1020.0
980.0
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
µPD161602A/B
Table 2–1. Pad Layout (2/3)
No.
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
Pad Name
S175
S176
S177
S178
S179
S180
S181
S182
S183
S184
S185
S186
S187
S188
S189
S190
S191
S192
S193
S194
S195
S196
S197
S198
S199
S200
S201
S202
S203
S204
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
S219
S220
S221
S222
S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
X [µ m]
940.0
900.0
860.0
820.0
780.0
740.0
700.0
660.0
620.0
580.0
540.0
500.0
460.0
420.0
380.0
340.0
300.0
260.0
220.0
180.0
140.0
100.0
60.0
20.0
-20.0
-60.0
-100.0
-140.0
-180.0
-220.0
-260.0
-300.0
-340.0
-380.0
-420.0
-460.0
-500.0
-540.0
-580.0
-620.0
-660.0
-700.0
-740.0
-780.0
-820.0
-860.0
-900.0
-940.0
-980.0
-1020.0
-1060.0
-1100.0
-1140.0
-1180.0
-1220.0
-1260.0
-1300.0
-1340.0
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
No.
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
Pad Name
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248
S249
S250
S251
S252
S253
S254
S255
S256
S257
S258
S259
S260
S261
S262
S263
S264
S265
S266
S267
S268
S269
S270
S271
S272
S273
S274
S275
S276
S277
S278
S279
S280
S281
S282
S283
S284
S285
S286
S287
S288
S289
S290
X [µ m]
-1380.0
-1420.0
-1460.0
-1500.0
-1540.0
-1580.0
-1620.0
-1660.0
-1700.0
-1740.0
-1780.0
-1820.0
-1860.0
-1900.0
-1940.0
-1980.0
-2020.0
-2060.0
-2100.0
-2140.0
-2180.0
-2220.0
-2260.0
-2300.0
-2340.0
-2380.0
-2420.0
-2460.0
-2500.0
-2540.0
-2580.0
-2620.0
-2660.0
-2700.0
-2740.0
-2780.0
-2820.0
-2860.0
-2900.0
-2940.0
-2980.0
-3020.0
-3060.0
-3100.0
-3140.0
-3180.0
-3220.0
-3260.0
-3300.0
-3340.0
-3380.0
-3420.0
-3460.0
-3500.0
-3540.0
-3580.0
-3620.0
-3660.0
Data Sheet S15381EJ1V0DS
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
No.
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
Pad Name
S291
S292
S293
S294
S295
S296
S297
S298
S299
S300
S301
S302
S303
S304
S305
S306
S307
S308
S309
S310
S311
S312
S313
S314
S315
S316
S317
S318
S319
S320
S321
S322
S323
S324
S325
S326
S327
S328
S329
S330
S331
S332
S333
S334
S335
S336
S337
S338
S339
S340
S341
S342
S343
S344
S345
S346
S347
S348
X [µ m]
-3700.0
-3740.0
-3780.0
-3820.0
-3860.0
-3900.0
-3940.0
-3980.0
-4020.0
-4060.0
-4100.0
-4140.0
-4180.0
-4220.0
-4260.0
-4300.0
-4340.0
-4380.0
-4420.0
-4460.0
-4500.0
-4540.0
-4580.0
-4620.0
-4660.0
-4700.0
-4740.0
-4780.0
-4820.0
-4860.0
-4900.0
-4940.0
-4980.0
-5020.0
-5060.0
-5100.0
-5140.0
-5180.0
-5220.0
-5260.0
-5300.0
-5340.0
-5380.0
-5420.0
-5460.0
-5500.0
-5540.0
-5580.0
-5620.0
-5660.0
-5700.0
-5740.0
-5780.0
-5820.0
-5860.0
-5900.0
-5940.0
-5980.0
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
5
µPD161602A/B
Table 2–1. Pad Layout (3/3)
No.
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
6
Pad Name
S349
S350
S351
S352
S353
S354
S355
S356
S357
S358
S359
S360
S361
S362
S363
S364
S365
S366
S367
S368
S369
S370
S371
S372
S373
S374
S375
S376
S377
S378
S379
S380
S381
S382
S383
S384
S385
S386
S387
S388
S389
S390
S391
S392
S393
S394
S395
S396
Dummy1
Dummy2
Dummy3
Dummy4
Dummy5
Dummy6
Dummy7
Dummy8
Dummy9
Dummy10
X [µ m]
-6020.0
-6060.0
-6100.0
-6140.0
-6180.0
-6220.0
-6260.0
-6300.0
-6340.0
-6380.0
-6420.0
-6460.0
-6500.0
-6540.0
-6580.0
-6620.0
-6660.0
-6700.0
-6740.0
-6780.0
-6820.0
-6860.0
-6900.0
-6940.0
-6980.0
-7020.0
-7060.0
-7100.0
-7140.0
-7180.0
-7220.0
-7260.0
-7300.0
-7340.0
-7380.0
-7420.0
-7460.0
-7500.0
-7540.0
-7580.0
-7620.0
-7660.0
-7700.0
-7740.0
-7780.0
-7820.0
-7860.0
-7900.0
-8031.4
-8367.0
-8367.0
-8367.0
-8367.0
-8367.0
-8367.0
-8367.0
-8367.0
-8367.0
Y [µ m]
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
667.7
512.2
687.0
347.0
247.0
147.0
47.0
-53.1
-153.1
-253.1
-353.1
-453.2
No.
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
Pad Name
Dummy11
Dummy12
VCOM
STHL
Dummy13
VDD2
VDD2
VDD2
Dummy14
VDD1
VDD1
VDD1
Dummy15
VSS1
VSS1
VSS1
Dummy16
VSS2
VSS2
VSS2
Dummy17
VCSEL
R,/L
OSEL
BA
GAM
CM
POL
AP
STB
D25
D24
D23
D22
D21
D20
CLK
Dummy18
V4
V4
V4
Dummy19
V3
V3
V3
Dummy20
V2
V2
V2
Dummy21
V1
V1
V1
Dummy22
V0
V0
V0
Dummy23
X [µ m]
-8367.0
-8254.8
-8079.8
-7829.8
-7654.8
-7393.4
-7293.4
-7193.4
-6932.0
-6831.9
-6732.0
-6632.0
-6456.9
-6278.6
-6178.7
-6078.7
-5903.7
-5728.7
-5628.7
-5528.7
-5350.4
-5175.4
-4925.3
-4675.3
-4425.3
-4175.3
-3925.3
-3675.2
-3425.2
-3175.2
-2925.2
-2675.2
-2425.1
-2175.1
-1925.1
-1675.1
-1425.1
-1250.0
-1075.0
-975.0
-875.1
-700.0
-525.0
-425.0
-325.1
-150.0
25.1
125.0
225.0
400.0
575.1
675.0
775.0
950.0
1125.1
1225.1
1325.0
1500.1
Y [µ m]
-553.2
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-686.9
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
Data Sheet S15381EJ1V0DS
No.
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
Pad Name
INV
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
TESTO1
TESTO2
TESTIN
Dummy24
VDD1
VDD1
VDD1
Dummy25
VSS1
VSS1
VSS1
Dummy26
VSS2
VSS2
VSS2
Dummy27
VDD2
VDD2
VDD2
Dummy28
STHR
Dummy29
Dummy30
Dummy31
Dummy32
Dummy33
Dummy34
Dummy35
Dummy36
Dummy37
Dummy38
Dummy39
Dummy40
X [µ m]
1675.1
1925.1
2175.1
2425.1
2675.2
2925.2
3175.2
3425.2
3675.2
3925.3
4175.3
4425.3
4675.3
4925.3
5175.4
5425.4
5600.4
5775.5
5875.5
5975.4
6075.5
6253.8
6353.8
6453.8
6628.8
6803.8
6903.8
7003.7
7182.0
7443.5
7543.4
7643.4
7904.8
8079.8
8254.8
8367.0
8367.0
8367.0
8367.0
8367.0
8367.0
8367.0
8367.0
8367.0
8367.0
8031.4
Y [µ m]
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-687.0
-553.2
-453.2
-353.1
-253.1
-153.1
-53.1
47.0
147.0
247.0
347.0
687.0
µPD161602A/B
★
3. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
Pad No.
I/O
Description
S1 to S396
Driver output
1 to 396 Output The D/A converted 64-gray-scale analog voltage is output.
Osel = L: S1 to S396
Osel = H: S19 to S378
D00 to D05
Display data input
477 to 472
D10 to D15
Input
The display data is input with a width of 18 bits, viz., the gray scale data (6 bits) by 3
dots (1 pixels).
DX0: LSB, DX5: MSB
Input
These refer to the shift direction control input.
The shift directions of the shift registers are as follows.
<When in Osel = L>
R,/L = L (left shift): STHL (input), S396 → S1 → STHR (output)
R,/L = H (right shift) : STHR (input), S1 → S396 → STHL (output)
<When in Osel = H>
R,/L = L (left shift): STHL (input), S378 → S19 → STHR (output)
R,/L = H (right shift) : STHR (input), S19 → S378 → STHL (output)
471 to 466
D20 to D25
442 to 437
R,/L
Shift direction
control input
429
STHR
Right shift start
498
pulse input/output
I/O
STHL
Left shift start
410
pulse input/output
I/O
CLK
Shift clock input
443
Input
This pin is the shift clock input of the shift register.
Display data is captured into the data register at the rising edge.
Osel = L: The start pulse output enters high level at the rising edge of the 132 th clock
following the start pulse input, and becomes the start pulse of the next level
driver. The 133th clock of the first driver becomes the start pulse input of the
next driver
Osel = H: The start pulse output enters high level at the rising edge of the 120th clock
following the start pulse input, and becomes the start pulse of the next driver.
The 121th clock of the first driver becomes the start pulse input of the next
driver.
STB
Latch input
436
Input
A timing signal that latches the contents of the data register. When an H level is read
at the rising edge of CLK, the contents of the data register are latched and transferred
to the D/A converter, and analog voltage corresponding to the display data is output.
Also, because the internal operation via CLK continues even after the STB latch, do
not stop CLK. The contents of the shift register are cleared at the rising edge of STB.
Following a 1-pulse input at startup, this IC will operate normally. Note that the output
switch is turned off at the rising edge of STB.
For the STB input timing, refer to Switching Characteristics Waveform.
POL
Polarity inversion
signal
434
Input
This pin inverts the output polarity. The polarity inversion signal data is captured at the
rising edge of STB. The γ -resistor is switched in accordance with the positive/negative
polarity.
POL = L: Negative polarity
POL = H: Positive polarity
INV
Data inversion
465
Input
This pin inverts the input data. Input data in synchronization with the shift clock.
INV = L: Normal input
INV = H: Data inversion input
VCOM
COM amplitude
output
409
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, STHL output
R,/L = L (left shift): STHL input, STHR output
Output This pin inverts the signal input from the POL pin and outputs it following conversion to
the VDD2 potential at the rising edge of STB. When the VCOM output is not used, VCsel
must be fixed to L.
Data Sheet S15381EJ1V0DS
7
µPD161602A/B
(2/2)
Pin Symbol
Pin Name
Pad No.
I/O
Description
VCsel
COM amplitude
428
output fixing signal
Input
The VCOM output is fixed to L. When the VCOM output is not used, VCsel needs
to be fixed to L.
VCsel = L: VCOM output fixed to L
VCsel = H: VCOM signal output in correspondence with POL signal
CM
8-color display
mode switching
433
Input
The operating mode is switched to 8-color mode. In this mode, turn off the γ resistor, amplifier, and BIAS circuit. However, when the γ -correction power supply
is input externally, the γ -circuit current will flow continuously.
CM = L: Normal display mode
CM = H: 8-color display mode
AP
Output SW
ON/OFF
435
Input
This pin turns ON/OFF the BIAS circuit and turns on the output SW and amplifier.
When AP is H, the amplifier is set and the LCD is driving.
The amplifier output and output SW are turned on at the rising edge of AP,
starting the LCD drive. Note that the output SW is turned off at the rising edge of
STB and the output becomes Hi-Z.
For the AP input timing, refer to Switching Characteristics Waveform.
GAM
External γ usage
selection
432
Input
When the γ -correction power supply is input externally, switch GAM to H. If two or
more chips are used, be sure to input the γ -correction power supply externally.
Figure 4–1 shows an input example of the γ -correction power supply.
GAM = L: External γ -correction power supply not input (open)
GAM = H: External γ -correction power supply input
Osel
Driver output
count switching
430
Input
The output count can be selected. When Osel = H, the unused pins S1 to S18 and
S379 to S396 always become Hi-Z.
Osel = L: 396 outputs
Osel = H: 360 outputs
V0 to V4
γ -corrected power
supplies
461 to 463,
−
457 to 459, 453
to 455, 449 to
451, 445 to 447
BA
BIAS current
adjustment
function
431
TESTIN
TEST input pin
480
TESTO1,
TESTO2
TEST output pin
478,
479
VDD1
Logic power
supply
416 to 418, 482
Driver power
supply
412 to 414, 494
Logic ground
420 to 422, 486
VDD2
VSS1
These pins input the γ -corrected power supplies from outside, the relationship
below must be observed. Also, be sure to stabilize the gray-scale-level power
supply during gray-scale voltage output.
VSS2 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VDD2
Input
This pin adjusts the BIAS current. Select either the high power mode or low power
mode.
BA = L: Low power mode
BA = H: high power mode
Input
Set to H or leave open
Output Leave open.
−
2.2 to 3.6 V
−
4.5 to 5.5 V
−
Ground
−
Ground
−
This pin is dummy.
to 484
to 496
to 488
VSS2
Driver ground
424 to 426, 490
to 492
Dummy1 to Dummy
dummy40
397 to 408, 411,
415, 419, 423, 427,
444, 448, 452, 456,
460, 464, 481, 485,
489, 493, 487, 499
to 510
Caution
To avoid latchup failure, the sequence when turning on the power must be VDD1 → logic input →
VDD2 →gray-scale power supply (V0 to V4), and the reverse sequence when turning off the power.
Follow this sequence during shift periods as well.
8
Data Sheet S15381EJ1V0DS
µPD161602A/B
4. EXAMPLES OF EACH SINGAL INPUT OR OUTPUT
Examples of the input/output timing of each signal during white and black display are shown below.
Figure 4–1. Timing Chart
STB
AP
POL
DATA
DATA = 111111
DATA = 000000
VCOM
260,000-color display mode (CM = L)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Undefined
OUT
Black level
Black level
White level
White level
Black level
Black level
White level
White level
8-color display mode
OUT
LSB
MSB
MSB used in 8-color
display mode
Data Sheet S15381EJ1V0DS
9
µPD161602A/B
4.1 γ-Correction Power Supply Connection Example
The µ PD161602A/B enables customization of the γ -correction power supply on both the positive and negative
polarity sides (refer to 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE).
Consequently, a γ -correction power supply does not have to be input externally when a single source-driver chip is
being used in the panel.
Multiple chips can also be used without having to input a γ -correction power supply externally because the error
between the chips can be absorbed by shorting the γ -correction power supply pins, as shown in Figure 4–2.
Figure 4–2. γ -Correction Power-Supply Connection Example
·Single chip
<Example 1 (GAM = L)>
Open
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
mPD161602
<Example 2 (GAM = H)>
External power supply input
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
mPD161602
·Multiple chips
<Example 1 (GAM = L)>
Vn - Vn short
External power supply input
VDD2 VSS2
V 0 V1 V 2 V 3 V 4
VSS2 VDD2
VDD2 VSS2
mPD161602
V 0 V 1 V 2 V3 V 4
VSS2 VDD2
mPD161602
<Example 2 (GAM = H)>
External power supply input
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
mPD161602
10
Data Sheet S15381EJ1V0DS
VDD2 VSS2
V 0 V 1 V 2 V 3 V4
mPD161602
VSS2 VDD2
µPD161602A/B
4.2 AP Signal Timing
The driver power consumption is dependent on the high period of the AP signal because the operational amplifier in
the IC is operation and current is constantly flowing in this period. A chart indication the recommended timing of
inputting the AP signal vis-a-vis the STB signal is shown below.
STB
AP
Hi-Z
MIN. 10 µs
Amp driving
10 to 15 µs
SW driving
Note that the ideal AP signal high period differs depending on the load of the liquid crystal. The AP period must
therefore be able to be adjusted using a controller.
The AP signal can also be used as shown below. However, in these cases, be sure to perform sufficient evaluation
before use.
<When SW drive in not used>
Only the amp is driven (SW drive is not used) if one horizontal period is short (40 µs or less) or the liquid crystal
load is large (50 pF or more).
STB
AP
<When the AP signal high period is 10 µs or less>
The amp drive period is shortened and the SW drive period lengthened when one horizontal period is long (100 µs
or more) and the liquid crystal load is small (20 pF).
STB
AP
Data Sheet S15381EJ1V0DS
11
µPD161602A/B
4.3 CLK Signal Input
Input at least 4 clocks of the CLK signal after the rising of the STB signal.
STB
2
1
3
4 /1
2
3
4
5
6
D10 to D12
D13 to D15
7
8
CLK
STH
Invalid D0 to D3 D4 to D6 D7 to D9
D16 to D18 D19 to D21
Internal latch
signal1 Note
Internal latch
signal2 Note
Internal latch
signal3 Note
Note Internal latch signal : It is the signal that do latch the display data put in data register in output latch circuit.
5. MODE EXPLANATION
Normal Mode/ 8-clor Display Mode
CM
H
POL
H
L
L
H
L
12
Data
MSB = H
Driver Output Status
8-color mode
Driver Output (in normally white)
White level display
MSB = L
Black level display
MSB = H
White level display
MSB = L
Black level display
All bit = H
260,000-color mode
White level display
All bit = L
Black level display
All bit = H
White level display
All bit = L
Black level display
Data Sheet S15381EJ1V0DS
µPD161602A/B
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The relation between input data and output voltage are shown in Table 6−2, 6−3.
Any 3 major points V1 to V3 from the LCD panel γ-characteristics curve can be used as the external power supplies.
The relationship V0 to V4 external power supplies and γ-correction resistance is shown in Table 6−1, Figure 6−1.
Table 6–1. Relationship between External Power Supply Pins and γ-correction Resistance
Pin Name
Voltage (V)
Resistance (Ω)
V0
5.0
0
V1
3.5
7,500
V2
2.5
12,500
V3
1.5
17,500
V4
0
25,000
Figure 6–1. Relationship between External Power Supply Pins and γ-correction Resistance
VDD2
V0
7500 Ω
V1
5000 Ω
V2
5000 Ω
V3
7500 Ω
V4
VSS2
This external power supply pins (V0 to V4) can customize the γ-correction voltage by selecting the desired voltage
from one of 250 divisions of the string resistor between VSS2 and VDD2, which generated γ-correction voltage. Note
that the voltage can be selected individually for both positive and negative polarity.
Data Sheet S15381EJ1V0DS
13
µPD161602A/B
Table 6−
−2. Relation of Input Data and Output Voltage in µPD161602A
Input
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Gray
Scale
Positive
Negative
Positive
Negative
Polarity
Polarity
Polarity
Polarity
Side (V)
Side (V)
Side (Ω)
Side (Ω)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
5.000
4.920
4.760
4.540
4.280
3.960
3.840
3.740
3.640
3.540
3.480
3.400
3.320
3.240
3.160
3.100
3.060
3.000
2.960
2.900
2.860
2.820
2.780
2.740
2.700
2.680
2.640
2.620
2.600
2.560
2.540
2.500
0.000
0.080
0.260
0.480
0.760
1.080
1.200
1.300
1.400
1.520
1.580
1.660
1.740
1.840
1.920
2.000
2.060
2.100
2.160
2.220
2.280
2.320
2.360
2.400
2.440
2.480
2.520
2.560
2.580
2.620
2.660
2.700
0
400
1200
2300
3600
5200
5800
6300
6800
7300
7600
8000
8400
8800
9200
9500
9700
10000
10200
10500
10700
10900
11100
11300
11500
11600
11800
11900
12000
12200
12300
12500
25000
24600
23700
22600
21200
19600
19000
18500
18000
17400
17100
16700
16300
15800
15400
15000
14700
14500
14200
13900
13600
13400
13200
13000
12800
12600
12400
12200
12100
11900
11700
11500
Input
Data
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Gray
Scale
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Positive
Negative
Positive
Polarity
Polarity
Polarity
Polarity
Side (V)
Side (V)
Side (Ω)
Side (Ω)
2.480
2.460
2.420
2.400
2.360
2.340
2.300
2.280
2.240
2.220
2.180
2.160
2.140
2.120
2.080
2.060
2.040
2.020
1.980
1.960
1.920
1.900
1.860
1.840
1.780
1.740
1.680
1.620
1.520
1.360
1.180
0.400
2.720
2.760
2.800
2.820
2.860
2.900
2.940
2.960
3.000
3.040
3.080
3.100
3.140
3.180
3.200
3.240
3.260
3.300
3.340
3.360
3.400
3.440
3.480
3.520
3.580
3.620
3.680
3.760
3.860
4.040
4.220
5.000
12600
12700
12900
13000
13200
13300
13500
13600
13800
13900
14100
14200
14300
14400
14600
14700
14800
14900
15100
15200
15400
15500
15700
15800
16100
16300
16600
16900
17400
18200
19100
23000
γ- curve
5.000
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
0
10
20
30
gray-scale
14
Data Sheet S15381EJ1V0DS
40
50
60
Negative
11400
11200
11000
10900
10700
10500
10300
10200
10000
9800
9600
9500
9300
9100
9000
8800
8700
8500
8300
8200
8000
7800
7600
7400
7100
6900
6600
6200
5700
4800
3900
0
µPD161602A/B
Table 6−
−3. Relation of Input Data and Output Voltage in µPD161602B
Input
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Gray
Scale
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Positive
Negative
Positive
Negative
Polarity
Polarity
Polarity
Polarity
Side (V)
Side (V)
Side (Ω)
Side (Ω)
5.000
4.980
4.960
4.920
4.880
4.800
4.720
4.600
4.460
4.320
4.160
4.000
3.860
3.780
3.700
3.620
3.540
3.460
3.380
3.320
3.280
3.220
3.160
3.120
3.060
3.040
3.000
2.960
2.940
2.900
2.860
2.820
0.000
0.020
0.060
0.100
0.140
0.220
0.300
0.440
0.580
0.740
0.920
1.080
1.240
1.320
1.420
1.500
1.600
1.680
1.760
1.820
1.880
1.940
2.000
2.040
2.100
2.140
2.180
2.220
2.240
2.280
2.320
2.360
0
100
200
400
600
1000
1400
2000
2700
3400
4200
5000
5700
6100
6500
6900
7300
7700
8100
8400
8600
8900
9200
9400
9700
9800
10000
10200
10300
10500
10700
10900
Input
Data
25000
24900
24700
24500
24300
23900
23500
22800
22100
21300
20400
19600
18800
18400
17900
17500
17000
16600
16200
15900
15600
15300
15000
14800
14500
14300
14100
13900
13800
13600
13400
13200
Gray
Scale
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Positive
Negative
Positive
Polarity
Polarity
Polarity
Polarity
Side (V)
Side (V)
Side (Ω)
Side (Ω)
2.780
2.760
2.720
2.680
2.660
2.620
2.600
2.560
2.520
2.480
2.460
2.400
2.360
2.340
2.300
2.260
2.220
2.180
2.140
2.100
2.040
2.000
1.960
1.900
1.840
1.780
1.700
1.580
1.460
1.260
1.080
0.400
2.400
2.440
2.480
2.520
2.540
2.580
2.620
2.660
2.700
2.740
2.780
2.820
2.860
2.900
2.940
2.980
3.020
3.060
3.100
3.160
3.220
3.260
3.320
3.380
3.420
3.520
3.600
3.720
3.840
4.060
4.280
5.000
11100
11200
11400
11600
11700
11900
12000
12200
12400
12600
12700
13000
13200
13300
13500
13700
13900
14100
14300
14500
14800
15000
15200
15500
15800
16100
16500
17100
17700
18700
19600
23000
Negative
13000
12800
12600
12400
12300
12100
11900
11700
11500
11300
11100
10900
10700
10500
10300
10100
9900
9700
9500
9200
8900
8700
8400
8100
7900
7400
7000
6400
5800
4700
3600
0
γ- curve
5.000
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
0
10
20
30
40
50
60
gray-scale
Data Sheet S15381EJ1V0DS
15
µPD161602A/B
6.1 Connection between γ-correction Resistance, Power Supply, and GND Pin
Connection of γ- compensation resistance power supply (V0-V4) and a power supply pin (VDD2 and VSS2) is indicated
below to be γ- compensation resistance of µPD161602 A/B.
By setup of a GAM pin, as for γ-compensation resistance, connection changes the highest minimum potential
between VDD2-VSS2 or among V0-V4.
Figure 6−
−2. GAM Pin Function
VDD2
γ -selectionSW
Positive Negative
polarity polarity
GAM
SW1
V0
GAM = L
SW1
SW2
V1
V2
GAM = H
V3
SW1
SW2
V4
SW2
GAM
VSS2
16
Data Sheet S15381EJ1V0DS
µPD161602A/B
7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits x RGBs (3 dots)
Input width: 18 bits (1-pixel data)
R,/L = H (Right shift), Osel = L (396 outputs)
Output
S1
S2
S3
S4
...
S395
S396
Data
D00 to D05
D10 to D15
D20 to D25
D00 to D05
...
D10 to D15
D20 to D25
R,/L = L (Left shift), Osel = L (396 outputs)
Output
S1
S2
S3
S4
...
S395
S396
Data
D00 to D05
D10 to D15
D20 to D25
D00 to D05
...
D10 to D15
D20 to D25
Data Sheet S15381EJ1V0DS
17
µPD161602A/B
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Rating
Unit
Logic Part Supply Voltage
VDD1
–0.3 to +4.5
V
Driver Part Supply Voltage
VDD2
–0.3 to +6.0
V
Input Voltage
VI
–0.3 to VDD1,2 + 0.3
V
Output Voltage
VO
–0.3 to VDD1,2 + 0.3
V
Operating Ambient Temperature
TA
–20 to +75
°C
Storage Temperature
Tstg
–55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –20 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.6
V
5.5
V
Logic Part Supply Voltage
VDD1
2.2
Driver Part Supply Voltage
VDD2
4.5
High-Level Input Voltage
VIH
0.7 VDD1
VDD1
V
Low-Level Input Voltage
VIL
0
0.3 VDD1
V
γ -Corrected Voltage
V0 to V4
VSS2
VDD2
V
Clock Frequency
fCLK
15
MHz
18
Data Sheet S15381EJ1V0DS
5.0
µPD161602A/B
Electrical Characteristics (TA = –20 to +75°C, VDD1 = 2.2 to 3.6 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Input Leak Current
Symbol
IIL
Condition
MIN.
TYP.
D00-D05, D10-D15, D20-D25, R,/L, STB, CLK,
MAX.
Unit
±1.0
µA
200
µA
STHR(L), INV, CM, AP, Osel, BA, POL,
GAM, VCsel
Input Current
IIL2
TESTIN
10
High-Level Output Voltage
VOH
STHR (STHL), IOH = –1.0 mA
Low-Level Output Voltage
VOL
STHR (STHL), IOL = +1.0 mA
VCOM Output Voltage
VOH2
VDD2 = 5.0 V, IO = –1.0 mA
VOL2
VDD2 = 5.0 V, IO = +1.0 mA
VDD1 – 0.5
VDD2 – 0.5
V0 = 5.0 V, V4 = 0 V
Static Current Consumption
(when in γ -correction power mode)
IVOH1
100
VDD2 = 5.0 V, VOUT = VX – 1.0 V
V
0.5
γ -Correction Power-supply Iγ
Driver Output Current
40
Note1
V
V
0.5
V
200
400
µA
–0.5
–0.15
mA
Input data: 1FH
(AMP drive)
IVOL1
VDD2 = 5.0 V, VOUT = VX + 1.0 V
Note1
0.15
0.50
mA
Input data: 20H
Driver Output Current
IVOH2
VDD2 = 5.0 V, VOUT = VX – 1.0 V
Note1
–50
–15
µA
Input data: 1FH
(Switch drive)
IVOL2
VDD2 = 5.0 V, VOUT = VX + 1.0 V
Note1
15
µA
40
Input data: 20H
Driver Output Current
VOH3
VDD2 = 5.0 V, IO = –50 uA
(8-color display mode)
VOL3
VDD2 = 5.0 V, IO = +50 uA
Output Voltage Deviation
∆VO
VDD1 = 2.5 V, VDD2 = 5.0 V,
VOUT = 2.5 V
Output Voltage Range
VO
Logic Part Dynamic Current IDD1
VDD2 – 0.5
0.5
V
±20
mV
VDD2 – 0.05
V
0.4
0.8
mA
0.9
1.5
mA
±10
Note1
Input data: 00H to 3FH
With no load
V
VSS2 + 0.05
Note2
Consumption
Driver Part Dynamic
IDD2
VDD = 5.0 V, with no load
Note2
Current Consumption
Notes 1. VX refers to the output voltage of analog output pins S1 to S396.
VOUT refers to the voltage applied to analog output pins S1 to S396.
2. fCLK = 15 MHz, STB cycle = 60 µs, AP pulse width = 15 µs, BA = L (low power mode)
Data Sheet S15381EJ1V0DS
19
µPD161602A/B
Switching Characteristics (TA = –20 to +75°C, VDD1 = 2.2 to 3.6 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Start Pulse Delay Time
Symbol
tPLH1
Condition
MIN.
TYP.
CL = 15 pF
tPHL1
MAX.
Unit
25
ns
25
ns
Driver Output Delay Time
tPLH2H
CL = 30 pF
12
µs
(High power mode)
tPHL2H
AP↓ →VOUT – 100 mV or VOUT + 100 mV
12
µs
Driver Output Delay Time
tPLH2L
CL = 30 pF
15
µs
tPHL2L
AP↓ →VOUT – 100 mV or VOUT + 100 mV
15
µs
CI1
V0 to V4, TA = 25°C
5
15
pF
CI2
Excluded V0 to V4, TA = 25°C
10
15
pF
TYP.
MAX.
Unit
(Low power mode)
Input Capacitance
★ Timing Requirements (TA = –20 to +75°°C, VDD1 = 2.2 to 3.6 V, VSS1 = 0 V, tr = tf = 10 ns)
Parameter
Symbol
Condition
MIN.
Clock Pulse Width
PW CLK
65
ns
Clock Pulse High Period
PW CLK(H)
20
ns
Clock Pulse Low Period
PW CLK(L)
20
ns
Data Setup Time
tSETUP1
20
ns
Data Hold Time
tHOLD1
20
ns
Start Pulse Setup Time
tSETUP2
20
ns
Start Pulse Hold Time
tHOLD2
20
ns
Start Pulse Low Period
tSPL
3
CLK
Last Data Timing
tLDT
2
CLK
CLK-STB Time
tCLK-STB
20
ns
STB Pulse Width
PW STB
40
ns
Start Pulse Rising Time
tSTB-STH
3
CLK
INV Set-up Time
tSETUP3
20
ns
INV Hold Time
tHOLD3
20
ns
STB Set-up Time
tSETUP4
20
ns
STB Hold Time
tHOLD4
20
ns
POL-STB Time
tPOL-STB
0
ns
STB-POL Time
tSTB-POL
40
ns
CM-STB Time
tCM-STB
0
ns
STB-CM Time
tSTB-CM
40
ns
STB-AP Time
tSTB-AP
20
µs
AP Pulse Width (High power mode)
PW APH
12
µs
AP Pulse Width (Low power mode)
PW APL
15
µs
20
CLK↑ →STB↑
STB↑ →STH↑
STB↑ →AP↓
STB cycle 40µs, CL = 30 pF
Data Sheet S15381EJ1V0DS
2
3
tr
132
133
10%
tSETUP2 tHOLD2
tSPL
STHR
(1st Dr.)
tSETUP1
DATA
D1 to D3
INVALID
tHOLD1
D4 to D6
INVALID
Last Data
tPLH1
tPHL1
STHL
(1st Dr.)
tLDT
tSETUP4
Data Sheet S15381EJ1V0DS
tCLK-STB
tHOLD4
PWSTB
STB
tSTB-STH
tSETUP3 tHOLD3
INV
tPOL-STB tSTB-POL
POL
tCM-STB tSTB-CM
CM
tSTB-AP
PWAB
AP
tPLH2
VOUT
tf
90%
Hi-Z
Switching Characteristic Waveform (R,/L= H, OSEL=L)
1
CLK
PWCLK(H)
PWCLK(L)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK
Hi-Z
21
µPD161602A/B
tPHL2
µPD161602A/B
[MEMO]
22
Data Sheet S15381EJ1V0DS
µPD161602A/B
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15381EJ1V0DS
23