DATA SHEET MOS INTEGRATED CIRCUIT µPD161660 POWER SUPPLY FOR TFT-LCD DRIVER DESCRIPTION The µPD161660 is a power supply IC for TFT-LCD driver. This ICs can generate the levels which TFT-LCD driver need, from 2.7 V. FEATURES • To generate 3 levels from single voltage input • To integrate regulator circuit for source and gate driver ORDERING INFORMATION ★ Part number Package µPD161660P Chip Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14799EJ1V0DS00 (1st edition) Date Published May 2002 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 2000, 2002 µPD161660 1. BLOCK DIAGRAM/SYSTEM DIAGRAM VDC VCC1 VDD1 C1+ C1 C1 – C2+ C1 DC/DC C2 – C3 + C1 C2 VCC X7 VDD2 C2 C3 – C4 + C1 C4 – C5 + C1 C2 C1 C5 – C6 + C1 0 V (GND) VO C6 – VEE VREF VREG VDD1 VREFSEL 2.5 V VREF + MVT – VT 15 V 12.5 V C3 RbT RcT VDD2 RaT VDD2 – MVS + VS RbS C3 RcS FS0 FS1 LFS0 LFS1 LPM ACS0 ACS1 LACS0 LACS1 RaS TESTOUT TESTIN1 to TESTIN6 RSEL EXRVT EXRVS VCE VCD2 VCD11 VCD12 2 DCON RGONP VSS DVSS Data Sheet S14799EJ1V0DS 5V 4V µPD161660 2. PIN CONFIGURATION (Pad Layout) Chip size: X = 4.20 mm, Y = 4.35 mm Pad size : 100 x 100 µm 2 (1) Alignment mark 30 µm 30 µm 30 µm 30 µm 30 µm 30 µm VDD2 16 VDD1 C1+ C1- DUMMY DUMMY DUMMY 26 C2- C3+ C425 C2+ 24 C3- 23 C4+ C5+ 22 C5- C621 27 28 29 30 31 32 33 34 35 DUMMY 36 TESTIN1 15 37 TESTIN2 MVT 14 38 TESTIN3 VT 13 39 DUMMY VREF 12 40 VSS MVS 11 41 DUMMY VS 10 42 VCC1 DUMMY 9 43 DUMMY DUMMY 8 44 DUMMY VDC 7 45 TESTIN4 DUMMY 6 46 TESTIN5 DUMMY 5 47 TESTOUT VCE 4 48 TESTIN6 VCD2 3 49 DVSS VCD12 2 50 LACS0 DUMMY 1 51 DUMMY Chip Surface (Bump Side) Y 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 DUMMY VCD11 LPM RGONP DCON EXRVT EXRVS LFS1 LFS0 FS1 FS0 RSEL ACS1 ACS0 VREFSEL LACS1 DUMMY X Alignment Mark Y = 4.35 mm 17 20 D161660 DUMMY 19 C6+ 18 VO DUMMY (2) Arrangement Alignment Mark (No Bump) X = 4.20 mm (No Bump) Data Sheet S14799E1V0DS 3 µPD161660 Table 2-1. Pad Layout 4 Pad No. Pad name 1 DUMMY −1950 −1800 Pad No. Pad name 41 DUMMY 1950 450 2 VCD12 −1950 −1575 3 VCD2 −1950 −1350 42 VCC1 1950 225 43 DUMMY 1950 4 VCE −1950 −1125 0 44 DUMMY 1950 −225 5 DUMMY −1950 6 DUMMY −1950 −900 45 TESTIN4 1950 −450 −675 46 TESTIN5 1950 7 VDC −675 −1950 −450 47 TESTOUT 1950 −900 8 9 DUMMY −1950 −225 48 TESTIN6 1950 −1125 DUMMY −1950 0 49 DVSS 1950 −1350 10 VS −1950 225 50 LACS0 1950 −1575 11 MVS −1950 450 51 DUMMY 1950 −1800 12 VREF −1950 675 52 DUMMY 1800 −2025 13 VT −1950 900 53 LACS1 1575 −2025 14 MVT −1950 1125 54 VREFSEL 1350 −2025 15 VDD1 −1950 1350 55 ACS0 1125 −2025 16 VDD2 −1950 1575 56 ACS1 900 −2025 17 DUMMY −1950 1800 57 RSEL 675 −2025 18 DUMMY −1800 2025 58 FS0 450 −2025 19 VO −1575 2025 59 FS1 225 −2025 20 C6 + −1350 2025 60 LFS0 0 −2025 21 C6 −1125 2025 61 LFS1 −225 −2025 −900 2025 62 EXRVS −450 −2025 −675 2025 63 EXRVT −675 −2025 −450 2025 64 DCON −900 −2025 −225 2025 65 RGONP −1125 −2025 0 2025 66 LPM −1350 −2025 − + 22 C5 23 C5 − + 24 C4 25 C4 26 C3 − + − 27 C3 28 C2 29 C2 + − + X[mm] Y[mm] Y[mm] 225 2025 67 VCD11 −1575 −2025 450 2025 68 DUMMY −1800 −2025 675 2025 Alignment mark −1950 −2025 Alignment mark 1950 −2025 30 C1 900 2025 31 C1 1125 2025 32 DUMMY 1350 2025 33 DUMMY 1575 2025 34 DUMMY 1800 2025 35 DUMMY 1950 1800 36 TESTIN1 1950 1575 37 TESTIN2 1950 1350 38 TESTIN3 1950 1125 39 DUMMY 1950 900 40 VSS 1950 675 − X[mm] Data Sheet S14799EJ1V0DS µPD161660 3. PIN FUNCTIONS (1/2) Symbol Pin Name Pad No. I/O Description VDC Power supply 7 – Power supply for DC/DC converter. VCC1 Power supply 42 – Power supply for logic circuit. VSS Ground 40 – Ground. DVSS Ground 49 – Ground (for control pin pull-down) VDD1 DC/DC converter output 15 – Boost voltage of DC/DC converter (x4, x5, x6 or x7). The capacitors required for each boost level are shown below. • x4 boost: C1, C2, C6 (C3, C4, and C5 are not required) • x5 boost: C1, C2, C3, C6 (C4, and C5 are not required) • x6 boost: C1, C2, C3, C4, C6 (C5 is not required) • x7 boost: C1, C2, C3, C4, C5, C6 VDD2 DC/DC converter output 16 – Boost voltage of DC/DC converter (x2 or x3). The boost steps for VDD2 is selected by VCD2 pin. The capacitors required for each boost level are shown below. • x2 boost: C1 • x3 boost: C1, C2, VO Rectangle signal output for 19 – negative boost Rectangle signal output for negative boost. The VO voltage range is selected by VCE pin. The capacitors required for each boost level are shown below. <VCE = L> • x3 boost: C1, C2 • x4 boost: C1, C2, C3 • x5 boost: C1, C2, C3, C4 • x6 boost: C1, C2, C3, C4, C5 <VCE = H> • x4 boost: C1, C2, C6 • x5 boost: C1, C2, C3, C6 • x6 boost: C1, C2, C3, C4, C6 • x7 boost: C1, C2, C3, C4, C5, C6 VT Regulator output 13 – 15 V/12.5 V regulator output for gate driver. VS Regulator output 10 – 5 V/4 V regulator output for source driver. VREF Reference voltage 12 I/O The gate driver includes reference voltage for VB regulator. When VREFSEL = H, external reference voltage can be input/output input. Reference voltage input/output pin of VT, VS regulator. DCON DC/DC converter control 64 I DC/DC converter ON/OFF control. Connect to DCON pin of source driver. RGONP Regulator control 65 I Regulator ON/OFF control. Connect to RGONP pin of source driver. EXRVT VT regulating resistor EXRVS VS regulating resistor 63 I To select internal/external resistor for VT regulator. 62 I To select internal/external resistor for VS regulator. selection selection Data Sheet S14799E1V0DS 5 µPD161660 (2/2) Symbol VCD11 Pin Name VDD1 booster selection Pad No. I/O 67 I Description To select x4/x5/x6/x7 boost for VDD1. Connect to VCD11 pin of source driver. VCD12 VDD1 booster selection 2 I To select x4/x5/x6/x7 boost for VDD1. Connect to VCD2 VDD2 booster selection 3 I To select x2/x3 boost for VDD2. Connect to VCD2 pin VCD12 pin of source driver. of source driver. VCE VO level selection 4 I To select x3/x4/x5/x6/x7 boost for VO top voltage level. Connect to VCE pin of source driver. LPM Low power mode signal 66 I Control signal for low power mode. When this pin is high level, it comes to be low power mode. LPM = H: LACS0, LACS1, LFS0, LFS1 are enabled. LPM = L : ACS0, ACS1, FS0, FS1 are enabled. Connect to LPMP pin of source driver. ACS0, Amp. current selection ACS1 55, I To select Amp. current when in scanning. I To select Amp. current in low power mode. 56 LACS0, Amp. current selection LACS1 50, 53 MVT VT regulator input 14 – EXRVT = H: Connect to external resistor. MVS VS regulator input 11 – EXRVS = H: Connect to external resistor. EXRVT = L: Leave it open. EXRVS = L: Leave it open. TESTIN1- Test TESTIN6 I Test pins. Normally leave it open. 47 O Test pin. Normally leave them open. 58, 59 I 36-38, 45, 46, 48 TESTOUT Test output FS0, FS1 OSC frequency selection To select OSC frequency for DC/DC converter when in scanning. LFS0, LFS1 OSC frequency selection 60, 61 I To select OSC frequency for DC/DC capacitor when 57 I To select internal resistor for regulator. 54 I To select external or internal reference voltage of 30, 31 – in scanning. RSEL Internal resistor selection for regulator VREFSEL Regulator reference voltage input VT, VS regulator. selection + − + − + − + − + − + − C1 , C1 C2 , C2 C3 , C3 C4 , C4 C5 , C5 C6 , C6 6 Capacitor connect pin for boost To connect external capacitor for DC/DC converter. 28, 29 The capacitance and tolerance of each capacitor are 26, 27 shown below. 24, 25 Capacitance 22, 23 Withstanding voltage: 10 V 20, 21 Data Sheet S14799EJ1V0DS : 1 µF µPD161660 4. MODE DESCRIPTION (1) DC/DC converter control DCON H DC/DC converter ON L DC/DC converter OFF (2) Regulator control RGONP H Regulator ON L Regulator OFF (VT, VS = High impedance) (3) VT regulating resistor EXRVT H External resistor L Internal resistor (4) VS regulating resistor EXRVS H External resistor L Internal resistor (5) VDD2 booster selection VCD2 H x3 booster L x2 booster (6) VT, VS regulator selection RSEL VT VS H 15.0 V 5.0 V L 12.5 V 4.0 V (7) Regulator reference voltage input selection VREFSEL H VREF : External reference voltage input L VREF : Internal reference voltage output Data Sheet S14799E1V0DS 7 µPD161660 (8) VDD1 and VO high-level booster selection VCD12 VCD11 VCE VDD1 booster VO high level H H H x7 VDC x7 VDC H H L x7 VDC x6 VDC H L H x6 VDC x6 VDC H L L x6 VDC x5 VDC L H H x5 VDC x5 VDC L H L x5 VDC x4 VDC L L H x4 VDC x4 VDC L L L x4 VDC x3 VDC (9) Amp. current selection VT ACS0 Note ACS1 (LACS0) Note Note VS Source current Sink current Amp. current Source current Sink current Amp. current (LACS1) L L 1 mA > 0.5 µA 1 µA 3 mA > 0.5 µA 1 µA L H 1 mA > 1 µA 2 µA 3 mA > 1 µA 2 µA H L 1 mA > 2.5 µA 5 µA 3 mA > 2.5 µA 5 µA H H 1 mA > 5 µA 10 µA 3 mA > 5 µA 10 µA ACS0, ACS1 : Current selection in scanning time LACS0, LACS1: Current selection in low power mode (10) OSC frequency selection Note FS1, LFS1 Note FS0, LFS0 Note OSC L L fOSC/8 L H fOSC/2 H L fOSC/32 H H fOSC/256 FS0, FS1 : Current selection when in scanning LFS0, LFS1: Current selection in low power mode (11) Low power mode selection LPM H Low power mode LACS0, LACS1, LFS0, LFS1 are enable. L Normal mode ACS0, ACS1, FS0, FS1 are enable. 8 Data Sheet S14799EJ1V0DS µPD161660 Figure 4-1. Example of Internal/External resistor for the regulator VREG VREF VREG VREFSEL VREG VREFSEL 2.5 V VREF + VT – MVT + 2.5V VREF 15 V MVT C3 VT – 15 V C3 RbT VT RaT VDD2 VDD2 – – MVS + MVS VS 5V C3 + RbS VS 5V C3 VS RaS External Resistor Mode EXRVT = H EXRVS = H Internal Resistor Mode EXRVT = L EXRVS = L VT = (1 + RbT ) VREF RaT VS = (1 + RbS ) VREF RaS Data Sheet S14799E1V0DS 9 µPD161660 5. POWER ON/OFF SEQUENCE 5.1 Power ON sequence VDC 2.5 V VCC1 tVR1 1.7 V 0 ns VCC2 tVR2 0 ns /RESET RESET command 100 ns < DISP ON command 0 ns DCON tDDRP RGONP tRPRG RGONG tRGOE1 OE1 OE2 A B tVR1, tVR2 = 100 ns MIN. Remarks 1. /xxx indicates active low signal. 2. OE1, OE2, /RESET, RGONG, RGONP, VCC2 are signals from source driver. ① All three power supplies, VDC, VCC1, and VCC2, can be on at the same time. ② The pins are fixed to the following levels by the source driver during the period of /RESET = L (A period). Note that the gate output is fixed to the VB level, and the DC/DC converter and the regulators are off. DCON, RGONG, RGONP, OE1: L (low level) OE2: H (high level) ③ The /RESET pin can be made high at the end of both tVR1, which starts from the rising edge of VCC1, and tVR2, which starts from the rising edge of VCC2. ④ The wait time between when the /RESET signal rises and when the RESET command is acknowledged must be at least 100 ns. ⑤ The logical status of the DCON, RGONG, RGONP, OE1, and OE2 pins in the period between when the /RESET signal rises and when the RESET command (↑part) is acknowledged (B period) is undefined. Be aware, therefore, 10 Data Sheet S14799EJ1V0DS µPD161660 that the gate output may be undefined and the DC/DC converter and the regulators may be on. If the B period is sufficiently short however, it is unlikely that the display will be affected. Note that the gate output MAX value in the B period must be determined separately as a specification of the LCD module. } The pins are re-fixed to the following levels by the source driver when the RESET command is input. Note that the gate output is fixed to the VB level, and the DC/DC converter and the regulators are off. DCON, RGONG, RGONP, OE1: L (low level) OE2: H (high level) ⑦ Set a timing that ensures the DCON, RGONP, and RGONG pins are shifted to high level in that order after the RESET command is input. At this time, the DC/DC converter and the regulators are on. Before that, the booster level must have been set up (by BGRS, VCE, VCD2, PVCOM of R32 register and R34 register of the µPD161620) . Note that the target timing of tDDRP and tRPRG (while the DC/DC converter output and regulator output is stable) is tDDRP = approx. 50 ms and tRPRG = approx. 20 ms, but users are requested to set the final timing after sufficiently evaluating the µPD161660 in the LCD module. ⑧ Input the DISPON command (↑part) after ensuring that all the power supplies are high level. The source driver will start display with OE1 = H. The target is tRGOE1 = approx. 1 ms, but users are requested to set the final timing after sufficiently evaluating the µPD161660 in the LCD module. Data Sheet S14799E1V0DS 11 µPD161660 5.2 Power OFF sequence VDC 0 ns VCC1 0 ns VCC2 0 ns /RESET STBY command < 1-frame 0 ns tRPDD DCON RGONP RGONG tRGRP tOE2RG OE1 OE2 Remark OE1, OE2, /RESET, RGONG, RGONP, VCC2 are the signals from driver. ① Input the STBY command (↑part). The source driver sets the status of the OE1 and OE2 pins to low level within one frame. The gate output is fixed to VT. ② Set a timing that ensures the RGONG, RGONP, and DCON pins are shifted to low level in that order after the panel load has been sufficiently discharged (tOE2RG timing; Secure an amount of time equivalent to one frame after executing the standby command). At this time, the DC/DC converter and the regulators are off. Note that a timing of 0 ns for tRGRP and tRPDD causes no problems on the device side, but users are requested to set the final timing after sufficiently evaluating the µPD161660 in the LCD module. ③ Although it is unnecessary to input the RESET command to the source driver, for designs in which the system is reset when the power supply is turned off, make settings that ensure /RESET = L at DCON = L and subsequent timings. ④ All three power supplies, VDC, VCC1, and VCC2, can be off at the same time. 12 Data Sheet S14799EJ1V0DS µPD161660 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V) Parameter Symbol Supply voltage VCC1 Supply voltage VDC Input voltage VI Input current II Output voltage VDD1 Output current IO Rating Unit –0.5 to +6.0 V –0.5 to + 6.0 V −0.5 to VCC1 + 0.5 V ±10 mA –0.5 to +40 V ±10 mA Output current IO2 ±10 mA Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = –40 to +85°°C, VSS = 0 V) Parameter Symbol MIN. TYP. MAX. Unit 2.7 Supply voltage VCC1 2.5 3.6 V Supply voltage VDC 2.5 3.6 V Input voltage VI 0 VCC1 V Electrical Characteristics (Unless otherwise specified, TA = –40 to +85°°C, VCC1 = 2.5 to 3.6 V, VSS = 0 V) Parameter ★ Symbol Condition MIN. TYP. MAX. 0.8 VCC1 Unit High level input voltage VIH Low level input voltage VIL V Boost voltage VDD1 IDD1 = 300 µA, 7 x Boost Boost voltage VDD1 Boost voltage VDD1 Boost voltage VDD1 IDD1 = 300 µA, 4 x Boost Boost voltage VDD2 VCD2 = L, IDD2 = 1 mA Boost voltage VDD2 VCD2 = H, IDD2 = 1 mA 2.7 VDC 3 VDC V Output voltage VT RSEL = H 13.5 15 16.5 V Output voltage VT RSEL = L 11.25 12.5 13.75 V Output voltage VS RSEL = H 4.5 5 5.5 V Output voltage VS RSEL = L 3.6 4 4.4 V VCC1 static current Ivcc1d VCC1 = 2.7 V, 5 µA 5 µA 2.75 V 0.2 VCC1 V 6 VDC 7 VDC V IDD1 = 300 µA, 6 x Boost 5 VDC 6 VDC V IDD1 = 300 µA, 5 x Boost 4 VDC 5 VDC V 3 VDC 4 VDC V 1.8 VDC 2 VDC V DCON, RGONG, RGONP = L ★ VDC static current Ivdcd VDC = 2.5 V, DCON, RGONG, RGONP = L VREF voltage 2.25 Data Sheet S14799E1V0DS 2.5 13 µPD161660 [MEMO] 14 Data Sheet S14799EJ1V0DS µPD161660 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14799E1V0DS 15