NEC UPD161641

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD161641
240-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The µPD161641 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can
output a high gate scanning voltage in response to a CMOS-level input.
FEATURES
• High breakdown voltage output (VT-VB = 37 V MAX.)
• 3.0 V CMOS level input
• Number of output: 240
★ ORDERING INFORMATION
Part number
Package
µPD161641N-xxx
TCP (TAB package)
µPD161641P
Chip
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S15678EJ1V0DS00 (1st edition)
Date Published July 2002 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
2001
µPD161641
1. BLOCK DIAGRAM
R,/L
CLK
STVSEL
STVR
SR1
SR87
SR2
SR88
SR89 SR90
SR239 SR240
STVL
MPX
OE1SEL
OE1
OE2SEL
OE2
VEE
VSS
VCC1
VT
Level Shifter
PVSS
PVCC1
VB
O1
Remark
2
O2
O87
O88
O89
/xxx indicates active low signal.
Data Sheet S15678EJ1V0DS
O90
O239
O240
µPD161641
2. PIN CONFIGURATION (Pad Layout)
Chip size: 9.4 x 3.5 mm
2
Bump size: INPUT (include input side dummy and short-side dummy): 49 x 85 µm
OUTPUT (include output side dummy): 35 x 94 µm
2
2
No.123
No.380
Face Up
No.122
No.381
Y
X
(0,0)
No.119
No.384
No.118
No.1
Alignment Mark
30 µm 30 µm 30 µm
30 µm
30 µm
30 µm
Data Sheet S15678EJ1V0DS
3
µPD161641
Table 2
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
4
Gate Inputs 75 µm pich
Pad Name
X [mm]
Alignment Mark
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
PVCC1
OE1SEL
OE1SEL
OE1SEL
OE1SEL
OE1SEL
PVSS
OE2SEL
OE2SEL
OE2SEL
OE2SEL
OE2SEL
DUMMY
PVCC1
STVSEL
STVSEL
STVSEL
STVSEL
STVSEL
PVSS
R,/L
R,/L
R,/L
R,/L
R,/L
PVCC1
DUMMY
VT
VT
VT
VT
VT
DUMMY
DUMMY
VCC1
VCC1
VCC1
VCC1
VCC1
DUMMY
DUMMY
DUMMY
VSS
VSS
VSS
VSS
VSS
1. Pad Layout (1/4)
Y [mm]
4.5650
-1.6145
4.3875
4.3125
4.2375
4.1625
4.0875
4.0125
3.9375
3.8625
3.7875
3.7125
3.6375
3.5625
3.4875
3.4125
3.3375
3.2625
3.1875
3.1125
3.0375
2.9625
2.8875
2.8125
2.7375
2.6625
2.5875
2.5125
2.4375
2.3625
2.2875
2.2125
2.1375
2.0625
1.9875
1.9125
1.8375
1.7625
1.6875
1.6125
1.5375
1.4625
1.3875
1.3125
1.2375
1.1625
1.0875
1.0125
0.9375
0.8625
0.7875
0.7125
0.6375
0.5625
0.4875
0.4125
0.3375
0.2625
0.1875
0.1125
0.0375
-0.0375
-0.1125
-0.1875
-0.2625
-0.3375
-0.4125
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
Pad No.
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
−
Data Sheet S15678EJ1V0DS
Gate Inputs 75 µm pich
Pad Name
X [mm]
DUMMY
-0.4875
DUMMY
-0.5625
DUMMY
-0.6375
DUMMY
-0.7125
VEE
-0.7875
VEE
-0.8625
VEE
-0.9375
VEE
-1.0125
VEE
-1.0875
DUMMY
-1.1625
DUMMY
-1.2375
VB
-1.3125
VB
-1.3875
VB
-1.4625
VB
-1.5375
VB
-1.6125
DUMMY
-1.6875
DUMMY
-1.7625
DUMMY
-1.8375
STVR
-1.9125
STVR
-1.9875
STVR
-2.0625
STVR
-2.1375
STVR
-2.2125
DUMMY
-2.2875
STVL
-2.3625
STVL
-2.4375
STVL
-2.5125
STVL
-2.5875
STVL
-2.6625
DUMMY
-2.7375
CLK
-2.8125
CLK
-2.8875
CLK
-2.9625
CLK
-3.0375
CLK
-3.1125
DUMMY
-3.1875
OE1
-3.2625
OE1
-3.3375
OE1
-3.4125
OE1
-3.4875
OE1
-3.5625
DUMMY
-3.6375
OE2
-3.7125
OE2
-3.7875
OE2
-3.8625
OE2
-3.9375
OE2
-4.0125
DUMMY
-4.0875
DUMMY
-4.1625
DUMMY
-4.2375
DUMMY
-4.3125
DUMMY
-4.3875
Y [mm]
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-1.6145
-4.5650
-1.6145
Alignment Mark
µPD161641
Table 2−
−1. Pad Layout (2/4)
Pad No.
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Gate Outputs 35 µm pich
Pad Name
X [mm]
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
-4.4975
-4.4625
-4.4275
-4.3925
-4.3575
-4.3225
-4.2875
-4.2525
-4.2175
-4.1825
-4.1475
-4.1125
-4.0775
-4.0425
-4.0075
-3.9725
-3.9375
-3.9025
-3.8675
-3.8325
-3.7975
-3.7625
-3.7275
-3.6925
-3.6575
-3.6225
-3.5875
-3.5525
-3.5175
-3.4825
-3.4475
-3.4125
-3.3775
-3.3425
-3.3075
-3.2725
-3.2375
-3.2025
-3.1675
-3.1325
-3.0975
-3.0625
-3.0275
-2.9925
-2.9575
-2.9225
-2.8875
-2.8525
-2.8175
-2.7825
-2.7475
-2.7125
-2.6775
-2.6425
-2.6075
-2.5725
-2.5375
-2.5025
-2.4675
-2.4325
-2.3975
-2.3625
-2.3275
-2.2925
-2.2575
-2.2225
Y [mm]
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
Pad No.
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
Data Sheet S15678EJ1V0DS
Gate Outputs 35 µm pich
Pad Name
X [mm]
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
DUMMY
DUMMY
DUMMY
-2.1875
-2.1525
-2.1175
-2.0825
-2.0475
-2.0125
-1.9775
-1.9425
-1.9075
-1.8725
-1.8375
-1.8025
-1.7675
-1.7325
-1.6975
-1.6625
-1.6275
-1.5925
-1.5575
-1.5225
-1.4875
-1.4525
-1.4175
-1.3825
-1.3475
-1.3125
-1.2775
-1.2425
-1.2075
-1.1725
-1.1375
-1.1025
-1.0675
-1.0325
-0.9975
-0.9625
-0.9275
-0.8925
-0.8575
-0.8225
-0.7875
-0.7525
-0.7175
-0.6825
-0.6475
-0.6125
-0.5775
-0.5425
-0.5075
-0.4725
-0.4375
-0.4025
-0.3675
-0.3325
-0.2975
-0.2625
-0.2275
-0.1925
-0.1575
-0.1225
-0.0875
-0.0525
-0.0175
0.0175
0.0525
0.0875
Y [mm]
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
5
µPD161641
Table 2−
−1. Pad Layout (3/4)
Pad No.
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
6
Gate Outputs 35 µm pich
Pad Name
X [mm]
DUMMY
DUMMY
DUMMY
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
0.1225
0.1575
0.1925
0.2275
0.2625
0.2975
0.3325
0.3675
0.4025
0.4375
0.4725
0.5075
0.5425
0.5775
0.6125
0.6475
0.6825
0.7175
0.7525
0.7875
0.8225
0.8575
0.8925
0.9275
0.9625
0.9975
1.0325
1.0675
1.1025
1.1375
1.1725
1.2075
1.2425
1.2775
1.3125
1.3475
1.3825
1.4175
1.4525
1.4875
1.5225
1.5575
1.5925
1.6275
1.6625
1.6975
1.7325
1.7675
1.8025
1.8375
1.8725
1.9075
1.9425
1.9775
2.0125
2.0475
2.0825
2.1175
2.1525
2.1875
2.2225
2.2575
2.2925
2.3275
2.3625
Y [mm]
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
Pad No.
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
Data Sheet S15678EJ1V0DS
Gate Outputs 35 µm pich
Pad Name
X [mm]
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DUMMY
DUMMY
DUMMY
2.3975
2.4325
2.4675
2.5025
2.5375
2.5725
2.6075
2.6425
2.6775
2.7125
2.7475
2.7825
2.8175
2.8525
2.8875
2.9225
2.9575
2.9925
3.0275
3.0625
3.0975
3.1325
3.1675
3.2025
3.2375
3.2725
3.3075
3.3425
3.3775
3.4125
3.4475
3.4825
3.5175
3.5525
3.5875
3.6225
3.6575
3.6925
3.7275
3.7625
3.7975
3.8325
3.8675
3.9025
3.9375
3.9725
4.0075
4.0425
4.0775
4.1125
4.1475
4.1825
4.2175
4.2525
4.2875
4.3225
4.3575
4.3925
4.4275
4.4625
4.4975
Y [mm]
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
1.6100
1.4800
µPD161641
Table 2−
−1. Pad Layout (4/4)
Pad No.
381
382
383
384
Gate Right 75 µm pich
Pad Name
X [mm]
DUMMY
DUMMY
DUMMY
DUMMY
4.5825
4.5825
4.5825
4.5825
Y [mm]
1.1250
0.3750
-0.3750
-1.1250
Pad No.
119
120
121
122
Data Sheet S15678EJ1V0DS
Gate Left 75 µm pich
Pad Name
X [mm]
DUMMY
DUMMY
DUMMY
DUMMY
-4.5825
-4.5825
-4.5825
-4.5825
Y [mm]
-1.1250
-0.3750
0.3750
1.1250
7
µPD161641
3. PIN FUNCTIONS
(1/2)
Symbol
O1 to O240
Pin Name
Driver output
Pad No.
I/O
132 to 251,
Output
258 to 377
Function
Scan signal output pins that drive the gate electrode of a TFTLCD. The status of each output pin changes in synchronization
with the rising edge of shift clock. The output voltage of the driver
is VT-VB.
STVR,
Start pulse input/output
STVL
85 to 89,
I/O
91 to 95
Input/output pin of the internal shift register.
Read of start pulse signal is set at rising edge of shift clock, and
outputs a scanning signal from a driver output pin. In addition,
the effective level of a STVR/STVL pin is determined by setup
of STVSEL pin. Moreover, an input/output level is VCC1-VSS
(logic level).
STVSEL = L: Start pulse is set to low level by the 240th falling
edge of shift clock, and is set to a high level by the 241st falling
edge.
STVSEL
Start pulse input
33 to 37
Input
effective level selection
The effective level of the start pulse signal inputted into
STVR/STVL is selected.
STVSEL = L: Low level
STVSEL = H: High level
CLK
Shift clock input
97 to 101
Input
Shift clock input for the internal shift register. The contents of
internal shift register is shifted at the rising edge of CLK.
Connect to GCLK pin of source driver.
R,/L
Shift direction
39 to 43
Input
Shift direction switching input pin of the internal shift register.
R,/L = H (right shift): STVR → O1 → O2 ··· O239 → O240 → STVL
switching input
R,/L = L (left shift): STVL → O240 → O239 ··· O2 → O1 → STVR
OE1
Enable input
103 to 107
Input
Input of the level selected by OE1SEL fixes a driver output to a
low level (input of a low level fixes driver output to low level at
the time of OE1SEL = L). However, shift register is not cleared.
Moreover, output enable operation is asynchronous on a clock.
Connect with GOE1 pin of sauce driver.
OE1SEL
OE1 effective level
20 to 24
Input
selection
This pin selects effective level of OE1 pin.
OE1SEL = L: Low level
OE1SEL = H: High level
OE2
Enable input
109 to 113
Input
Input of the level selected by OE2SEL fixes a driver output to a
high level (input of a low level fixes driver output to high level at
the time of OE2SEL = L). However, shift register is not cleared.
Moreover, output enable operation is asynchronous on a clock.
Connect with GOE2 pin of sauce driver.
OE2SEL
OE2 effective level
selection
26 to 30
Input
This pin selects effective level of OE2 pin.
OE2SEL = L: Low level
OE2SEL = H: High level
8
Data Sheet S15678EJ1V0DS
µPD161641
(2/2)
Symbol
VT
Name
Positive power
Pad No.
I/O
−
70 to 74
−
Negative power supply for level shifter.
77 to 81
−
Negative power supply for output buffer.
53 to 57
−
Positive power supply for logic circuit.
supply for driver
VEE
Negative power
Function
48 to 50
Positive power supply for level shifter and output buffer.
Positive power supply for Liquid crystal.
supply for logic
VB
Negative power
supply for driver
VCC1
Positive power
Negative power supply for Liquid crystal.
supply for logic
VSS
Ground
61 to 65
−
Connect to the system ground.
PVCC1
Pull-up power
19, 32, 44
−
Pull-up power supply for mode setting pins (R,/L, STVSEL,
25, 38
−
supply
PVSS
OE1SEL, OE2SEL).
Pull-down power
supply
Pull-down power supply for mode setting pins (R,/L, STVSEL,
OE1SEL, OE2SEL).
4. MODE DESCRIPTION
Output Mode Selection
R,/L
STVR
STVL
Scan Direction
H
Input
Output
1→240
L
Output
Input
240→1
Remark H: VCC1, L: VSS
Data Sheet S15678EJ1V0DS
9
µPD161641
5. TIMING CHART
The timing chart in each conditions is shown as follows.
R,/L = H, STVSEL = L, OE1SEL = L, OE2SEL = L
1
2
3
4
240
241
242
243
244
245
4
240
241
242
243
244
245
CLK
OE1
OE2
STVR
O1
O2
O3
O 240
STVL
(O 1 )
(O 2 )
(O 3 )
R,/L = L, STVSEL = H, OE1SEL = H, OE2SEL = H
1
2
3
CLK
OE1
OE2
STVL
O 240
O 239
O 238
O1
STVR
(O 240 )
(O 239 )
(O 238 )
10
Data Sheet S15678EJ1V0DS
µPD161641
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Parameter
Symbol
Rating
Unit
Supply Voltage
VT
–0.5 to +23
V
Supply Voltage
VCC1
–0.5 to +7.0
V
Supply Voltage
VT-VEE
–0.5 to +40
V
Supply Voltage
VEE
VT−38 to +0.5
V
Supply Voltage
VB
VEE+0.5 to +0.5
V
Note
VI
−0.5 to VCC1+0.5
V
Operating Ambient Temperature
TA
−40 to +85
°C
Storage Temperature
Tstg
−55 to +150
°C
Input Voltage
Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = –40 to +85°°C, VSS = 0 V)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
8.5
15
20.5
V
VEE
–16.5
–15
–13.5
V
VB
VEE+1
VEE+12
V
Supply Voltage
VT
Supply Voltage
Supply Voltage
Supply Voltage
VT-VEE
22
Supply Voltage
VCC1
2.5
Input Voltage
Note
VI
0
2.7
37
V
3.6
V
VCC1
V
Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL
Data Sheet S15678EJ1V0DS
11
µPD161641
Electrical Characteristics (TA = −40 to +85°°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = −15 V, VB = −11 V, VSS = 0 V)
Parameter
High Level Input Voltage
Symbol
Condition
MAX.
Unit
0.8 VCC1
MIN.
TYP.
VCC1
V
0
0.2 VCC1
V
VCC1 – 0.4
VCC1
V
VIH1
R,/L, CLK, STVR, STVL, OE1, OE2,
Low Level Input Voltage
VIL1
STVSEL , OE1SEL , OE2SEL
High Level Output Voltage
VOH
STVR, STVL, IOH = –40 µA
Low Level Output Voltage
VOL
STVR, STVL, IOH = +40 µA
0
0.4
V
Output ON Resistance
RON1
O1 to O240
1.0
kΩ
Input Current
II1
Logic input pin
±1.0
µA
Dynamic Current 1
ICC1
VCC1, Note
200
µA
Dynamic Current 2
IT
VT, Note
100
µA
Dynamic Current 3
IEE
VEE, Note
100
µA
ISS
VCC1, VT in stand-by mode
10
µA
Static Current
Note
Note fCLK = 45.5 kHz, output no load
Switching Characteristics (TA = −40 to +85°°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = −15 V, VB = −11 V, VSS = 0 V)
Parameter
Cascade Output Delay Time
Driver Output Delay Time 1
Driver Output Delay Time2
Driver Output Delay Time 3
Symbol
tPHL1
Condition
MIN.
TYP.
CL = 20 pF,
MAX.
Unit
800
ns
tPLH1
CLK → STVL (STVR)
800
ns
tPHL2
CL = 300 pF,
500
ns
tPLH2
CLK → On
500
ns
tPHL3
CL = 300 pF,
500
ns
tPLH3
OE1 → On
500
ns
tPHL4
CL = 300 pF,
500
ns
tPLH4
OE2 → On
500
ns
Output Rise Time
tTLH
CL = 300 pF
800
ns
Output Fall Time
tTHL
800
ns
Input Capacitance
CI
TA = 25°C
15
pF
Clock Frequency
fCLK
When connected in cascade
500
kHz
Timing Requirement (TA = −40 to +85°°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = −15 V, VB = −11 V, VSS = 0 V)
Parameter
Clock Pulse High Period
Symbol
Condition
PW CLK(H)
Clock Pulse Low Period
PW CLK(L)
Enable Pulse High Period
PW OE
OE1, OE2
Data Setup Time
tSETUP
Data Hold Time
tHOLD
Remark
12
MIN.
TYP.
MAX.
Unit
500
ns
500
ns
1
µs
STVR (STVL) ↓ →CLK↑
200
ns
CLK↑→STVR (STVL) ↑
200
ns
The rise and fall times of logic input must be tr = tf = 20 ns (10 to 90%)
Data Sheet S15678EJ1V0DS
µPD161641
Switching Characteristics Waveform (R,/L = H, STVSEL = L, OE1SEL = L, OE2SEL = L)
( ): R,/L = L
1/fCLK
PWCLK(H)
PWCLK(L)
VDD
CLK
50%
50%
50%
50%
VSS
tSETUP
tHOLD
VDD
STVR
(STVL)
50%
50%
VSS
tPHL1
tPLH1
VDD
STVL
(STVR)
50%
50%
VSS
tPLH2
tTLH
tPHL2
90%
tTHL
VGG
90%
On
10%
10%
VEE
PWOE
VDD
OE1
50%
50%
VSS
tPHL3
tPLH3
VGG
90%
On
10%
VEE
PWOE
VDD
OE2
50%
50%
VSS
tPLH4
tPHL4
VGG
90%
On
10%
VEE
Data Sheet S15678EJ1V0DS
13
µPD161641
[MEMO]
14
Data Sheet S15678EJ1V0DS
µPD161641
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15678EJ1V0DS
15