NJRC NJU26203AV

NJU26203A
Dolby Pro Logic II Decoder
General Description
■Package
The NJU26203A is a digital signal processor that provides the function of Dolby Pro Logic II,
Bass Management, Multi channel input, and 5-band PEQ function.
The applications of NJU26203A are suitable for multi channel products such as Car Audio,
DVD Receiver and speakers system.
Features
NJU26203AV
-Software
Dolby Pro Logic II (Max 5.1ch Output)
Bass Management
Multi channel input
5-band PEQ
Center Mixer, Rear Center Mixer
Master Volume
-Hardware
24bit Fixed-point Digital Signal Processing
Maximum Clock Frequency
: 12.288MHz(Standard), built-in PLL Circuit
Digital Audio Interface
: 4 Input ports / 4 Output ports
Digital Audio Format
: I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs
Master / Slave Mode
Microcomputer Interface
I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
Operating Voltage
: VDD = VDDPLL = 1.8V
: VDDIO = 3.3V
Input Terminal
: +5.0V Input tolerant
Package
: SSOP44 (Pb-Free)
* The detail hardware specification of the NJU26203A is described in the “ NJU26200 Series Hardware Data Sheet”.
Ver.2008-12-10
-1-
NJU26203A
Hardware Block Diagram
AD1/SDIN
AD2/SSb
DSP ARITHMETIC UNIT
SCL/SCK
SDA/SDOUT
SERIAL
HOST
INTERFACE
BCKO
BCKO
PROGRAM
CONTROL
LRO
2424-BIT x 2424-BIT
MULTIPLIER
ALU
RESETb
MCK
CLK
SERIAL AUDIO
INTERFACE
TIMING
GENERATOR
/ PLL
L/Rout
SDO1
SDO1
C/SWout
C/SWout
SDO2
SDO2
LS/RSout
SDO3
SDO3
LB/RB
/RBout
SDO0
SDO0
Input
Input
SDI0~3
SDI0~3
ADDRESS GENERATION UNIT
BCKI
CLKOUT
LRI
PROC
DATA
RAM
FIRMWARE
ROM
General I/O
INTERFACE
MUTEb
MUTEb
SEL
WDC
Fig. 1 NJU26203A Hardware Block Diagram
-2-
Ver.2008-12-10
NJU26203A
Function Block Diagram
L
4 Stereo
L/R->LS/RS
5 Band PEQ
SDO1
SDI0
R
Pro Logic II
L/R
SW
LFE Generator
C
SW
LS/RS Delay
SDI3
5 Band PEQ
LS
RS
LB
5 Band PEQ
Master Volume & Channel Trim
Input Trimmer
SDI2
Center Delay
SDI1
Bass Management
6 Stereo
L/R->C/SW
L/R->LS/RS
SDO2
5 Band PEQ
5 Band PEQ
SDO3
5 Band PEQ
Delay
5 Band PEQ
SDO0
5 Band PEQ
SDO1
RB
Noise Generator
Smooth Control
*Center Mix is effective only at the time of 4ch Stereo Mode or Multi Input Mode choice.
*LFE Generator ON/OFF is effective only at the time of 4ch Stereo Mode choice.
Fig. 2 NJU26203A Function Block Diagram (Firmware)
L
4 Stereo
L/R->LS/RS
SDI0
R
SW
LFE Generator
SW
LS/RS Delay
L/R
C
LS
RS
LB
5 Band PEQ
Master Volume & Channel Trim
Pro Logic II
Center Delay
Input Trimmer
Bass Management
SDI1
5 Band PEQ
SDO2
5 Band PEQ
5 Band PEQ
SDO3
5 Band PEQ
Delay
5 Band PEQ
SDO0
RB
Noise Generator
Smooth Control
Fig. 3 NJU26203A Function Block Diagram (Stereo Input)
Ver.2008-12-10
-3-
NJU26203A
L
5 Band PEQ
SDO1
SDI0
R
LFE Output Trim
LS/RS
C
SW
LS/RS Delay
SDI3
C/SW
5 Band PEQ
LS
RS
LB
5 Band PEQ
Master Volume & Channel Trim
Input Trimmer
SDI2
C
Bass Management
SDI1
Center Delay
L/R
SDO2
5 Band PEQ
5 Band PEQ
SDO3
5 Band PEQ
Delay
5 Band PEQ
SDO0
RB
Noise Generator
Smooth Control
Fig. 4 NJU26203A Function Block Diagram (Multi channel input)
L
5 Band PEQ
SDO1
SDI0
R
5 Band PEQ
C
SW
LS/RS Delay
LS
RS
LB
5 Band PEQ
Master Volume & Channel Trim
Input Trimmer
Bass Management
SDI1
6 Stereo
L/R->C/SW
L/R->LS/RS
SDO2
5 Band PEQ
5 Band PEQ
SDO3
5 Band PEQ
Delay
5 Band PEQ
SDO0
RB
Noise Generator
Smooth Control
Fig. 5 NJU26203A Function Block Diagram (Stereo Input, NON-FADER (6ch Stereo))
-4-
Ver.2008-12-10
NJU26203A
Pin Configuration
SDI3
1
44
VDD
SDI2
2
43
VSS
SDI1
3
42
VSSIO
SDI0
4
41
VDDIO
LRI
5
40
SDO0
VDDIO
6
39
SDO1
BCKI
7
38
SDO2
VSS
8
37
SDO3
VDD
9
36
LRO
TEST
10
35
BCKO
34
MCK
33
VDDIO
NJU26203A
MUTEb
11
WDC
12
PROC
13
32
SDA/SDOUT
VSSIO
14
31
SCL/SCK
VDDIO
15
30
AD2/SSb
SEL
16
29
AD1/SDIN
VDDPLL
17
28
TEST
VSSPLL
18
27
TEST
VSS
19
26
TEST
VDD
20
25
RESETb
CLKOUT
21
24
VDDIO
CLK
22
23
VSSIO
SSOP44
Fig. 6 NJU26203A Pin Configuration
Ver.2008-12-10
-5-
NJU26203A
Pin Description
Table 1 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
SDI3
SDI2
SDI1
SDI0
LRI
VDDIO
BCKI
VSS
VDD
I/O
I
I
I
I
I
I
-
10
TEST *
I
11
12
MUTEb *
WDC *
I
OD
13
PROC *
I
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSSIO
VDDIO
SEL
VDDPLL
VSSPLL
VSS
VDD
CLKOUT
CLK
VSSIO
VDDIO
RESETb
TEST
TEST
TEST
AD1/SDIN
AD2/SSb
SCL/SCK
SDA/SDOUT
VDDIO
MCK
BCKO
LRO
SDO3
SDO2
SDO1
SDO0
VDDIO
VSSIO
VSS
VDD
I
O
I
I
I
I
I
I
I
I
I/O
O
O
O
O
O
O
O
-
Function
Audio Data Input ch.3 (LS/RS)
Audio Data Input ch.2 (C/SW)
Audio Data Input ch.1 (L/R)
Audio Data Input ch.0 (L/R)
LR Clock Input
I/O Power Supply +3.3V
Bit Clock Input
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
for test
connect with VSSIO through 3.3-ohm resistance.
Master Volume Status after reset ‘1’: 0dB, ‘0’: Mute
Watchdog Clock output pin (Open drain output)
Signal Processing after reset ‘1’: Normal Processing, ‘0’: Waiting for a
Command without Processing
I/O Power Supply GND
I/O Power Supply +3.3V
2
Host Interface Selection ‘1’: Serial Interface, ‘0’: I C bus
PLL Power Supply +1.8V
PLL Power Supply GND
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
OSC Clock Output
OSC Clock Input (12.288MHz)
I/O Power Supply GND
I/O Power Supply +3.3V
Reset (RESETb=’0’: DSP Reset)
for test (connect to VDDIO)
for test (connect to VSSIO)
for test (connect to VSSIO)
2
2
I C Address (I C mode) / Serial In (4-wire serial mode)
2
2
I C Address (I C mode) / Serial enable (4-wire serial mode)
2
2
I C SCL (I C mode) / Serial clock (4-wire serial mode)
2
2
I C SDA (I C mode) / Serial Out (4-wire serial mode)
I/O Power Supply +3.3V
A/D, D/A clock output (buffer output of a CLK pin)
Bit Clock Output
LR Clock Output
Audio Data Output ch.3 (LS/RS)
Audio Data Output ch.2 (C/SW)
Audio Data Output ch.1 (L/R)
Audio Data Output ch.0 (LB/RB)
I/O Power Supply +3.3V
I/O Power Supply GND
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3kΩ resistance
-6-
Ver.2008-12-10
NJU26203A
Audio Interface
The NJU26203A audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first
Right-justified. The NJU26203A audio interface provides four data inputs, SDI0, SDI1, SDI2 and SDI3, and four data
outputs, SDO0, SDO1, SDO2 and SDO3 as shown in table 2 and 3. The input serial data is selected by the firmware
command.
Table 2
Serial Audio Input Pin
Pin No.
Symbol
4
3
2
1
SDI0
SDI1
SDI2
SDI3
Description
Stereo input
Multi channel input
Audio Data Input (L/R)
Audio Data Input (L/R)
(SDI0/SDI1 pin select)
(SDI0/SDI1 pin select)
None
Audio Data Input 2 (C/SW)
None
Audio Data Input 3 (LS/RS)
Table 3 Serial Audio Output Pin
Pin No.
Symbol
Description
40
SDO0
Audio Data Output 0 (LB/RB)
39
SDO1
Audio Data Output 1 (L/R)
38
SDO2
Audio Data Output 2 (C/SW)
37
SDO3
Audio Data Output 3 (LS/RS)
Host Interface
The NJU26203A can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or
4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a
SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data
transfers, regardless of the chosen communication protocol.
The detail I2C bus and 4-Wire Serial bus information are described in the ‘NJU26200 Series Hardware Data
Sheet’.
Table 4 Serial Host Interface Pin Descriptions
Pin No.
Symbol
Setting
Low
16
SEL
High
Table 5
Pin No.
Serial Host Interface Pin Description
Symbol
2
I C bus Interface
4-Wire Serial Interface
I C Address Select Bit1
2
I C Address Select Bit2
Serial Clock
Serial Data Input/Output
(Open Drain output)
Serial data input
Slave select
Serial Clock
Serial data output
(CMOS Output)
2
29
30
31
(I C /Serial)
AD1/SDIN
AD2/SSb
SCL/SCK
32
SDA/SDOUT
Host Interface
I2C Bus Interface
4-Wire Serial Interface
2
2
Note: When I C Bus is selected, the SDA/SDOUT pin is a bi-directional Open Drain output. This pin, which is assigned
2
for I C Bus, requires a pull-up resistance.
When 4-Wire Serial bus is selected, the SDA/SDOUT pin is CMOS output.
The SDA/SDOUT pin isn’t 5.0V Input tolerant.
Ver.2008-12-10
-7-
NJU26203A
I2C Bus
When the NJU26203A is configured for I2C bus communication in SEL=”Low”, the serial host interface transfers
data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance.
Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)
2
Table 6 I C Bus Interface Slave address
bit7
0
0
0
0
bit6
0
0
0
0
bit5
1
1
1
1
Start
bit
bit4
1
1
1
1
AD2
bit2
0
0
1
1
bit3
1
1
1
1
AD1
bit1
0
1
0
1
R/W
bit
Slave Address ( 7bit )
R/W
bit0
R/W
ACK
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
* SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”.
Note:
Both “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” data transfer rate are supported.
4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the
Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the
same time that a read byte is shifted out of the SDOUT pin.
Data transfers are MSB first and are enabled by setting SSb = “Low”. Data is clocked into SDIN on rising
transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is
latched on the falling transitions of SSb. SDOUT is always CMOS output. SDOUT does not require a pull-up
resistance.
SSb
SCK
bit7
SDIN
bit6
bit5
bit1
MSB
SDOUT
unstable
bit7
bit0
LSB
bit6
bit5
bit1
bit0
unstable
Fig. 7 4-Wire Serial Interface Timing
Note :
When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
transition of SSb=”High”.
When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”.
-8-
Ver.2008-12-10
NJU26203A
Pin setting
The NJU26203A operates default command setting after resetting the NJU26203A. In addition, the NJU26203A
restricts operation at power on by setting PROC pin and MUTEb pin. These pins are input pin. However, these pins
operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3kΩ resistance.
Table 7
Pin No.
13
11
Pin setting
Symbol
Setting
“High”
PROC
“Low”
MUTEb
“High”
“Low”
Function
The NJU26203A operates default setting after reset.
The NJU26203A does not operate after reset. Sending start
command is required for starting operation.
Master volume is set 0dB after reset.
Master volume is set mute after reset.
WatchDog Clock
The NJU26203A outputs clock pulse through WDC (Pin No.12) during normal operation. The WDC clock is useful
to check the status of the NJU26203A operation. For example, a microcomputer monitors the WDC clock and checks
the status of the NJU26203A. When the WDC clock pulse is lost or not normal clock cycle, the NJU26203A does not
operate correctly. Then reset the NJU26203A and set up the NJU26203A again. The WDC clock is able to be variable
for 0msec to 100msec by command. Default setting of WDC clock is 100msec.
The WDC pin is open drain output. The WDC pin setting (Table 8)
Table 8 WDC pin setting
Pin No.
Symbol
12
WDC
WDC pin is used.
WDC pin is not used.
Setting
Connect with VDDIO through 3.3kΩ resistance.
Connect with VSSIO through 3.3kΩ resistance.
Do not open WDC pin.
Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing.
In slave mode, when there is no input of BCKI/LRI, WDC can’t output.
It is required to set up a sampling rate correctly.
Ver.2008-12-10
-9-
NJU26203A
Firmware Command Table
Host processor can control the NJU26203A via I2C bus or 4-Wire serial bus interface. The following table
summarizes the available user commands.
Table 9 Command Table
No.
Command Description
1
Set Task Command
2
System State Command
3
Sample rate Select Command
4
Smooth Control Config Command
5
Master Volume Control Command
6
Channel Trim Control Command
7
Input Trim Control Command
8
LFE Trim Control Command
9
Center Mix Trim Control Command
10
Pro Logic II Mode Command
11
Center Delay Control Command
12
Surround Delay Control Command
13
Bass Management Config Command
14
PNG Mode Command
15
EQ Channel Select Command
16
EQ Mode Select Command
17
EQ f0 Control Command
18
EQ Q Control Command
19
EQ Gain Control Command
20
Watch Dog Timer Command
21
LB ch Output Select Command
22
LFE f0 Control Command
23
LB Delay Control Command
24
Firmware Version Number Request Command
25
DSP Reset Command
26
Start Command
27
Nop Command
Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a
licenser (Dolby) is required.
Response of status
NJU26203A returns the response of 4 types to the host controller.
Table 10 Response of status
Response
Status : Command Accepted
Status : Command Error
Status : Command Process
Status : Not Ready
- 10 -
Command
0x80
0x81
0x82
0x83
Remark
Reception OK
Reception ERROR
Command processing
Initialization
Ver.2008-12-10
NJU26203A
License Information
The Word “DOLBY”, “Pro Logic II” and the double D mark are trademarks of Dolby Laboratories.
The NJU26203A can only be delivered to licensees of Dolby Laboratories.
Please refer to the licensing application manual issued by Dolby Laboratories.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2008-12-10
- 11 -