NPC SM5844

SM5844AF
Asynchronous Sample Rate Converter
OVERVIEW
APPLICATIONS
The SM5844AF is a digital audio signal,
asynchronous sample rate converter LSI. It reads 16
or 20-bit word length input data, and writes 16, 18,
or 20-bit word length output data. It also features a
built-in digital deemphasis filter and digital
attenuator.
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■
■
■
■
■
SLAVE
OW18N
VDD
PACKAGE DIMENSIONS
Unit: mm
44-pin QFP
12.80 +- 0.30
10.00
0 to 10
■
OW20N
0.60 +- 0.20
0.80
0.35 +- 0.10
1.75MAX
■
■
IFM2
1.45
■
IISN
0 to 0.20
■
IFM1
RSTN
TST2N
TST1N
STATE
MLEN/DEEM
■
LRCI
ICLK
ICKSL
10.00
■
VSS
BCKI
12.80 +- 0.30
■
DI
SM5844AF
■
Left/right-channel processing (stereo)
Input sample rate (fsi) ranges
• 24 to 48 kHz (256fsi mode)
• 27 to 55 kHz (384fsi mode)
Output sample rate (fso) range
• 20 to 100 kHz
Sample rate conversion ratio (fso/fsi)
• 0.5 to 2.0 times
Asynchronous input and output timing (clock
inputs)
System clock inputs (input and output clocks
independent)
• 256fsi or 384fsi input system clock
• 256fso or 384fso output system clock
Deemphasis filter
• IIR-type filter
• 44.1, 48 or 32 kHz
Digital attenuator
• 11-bit data for 1025 levels
• Smooth, incremental attenuation change
• +12 dB gain shift function
Direct mute function
Through mode operation
• Input to output direct
Output data clocks (LRCO, BCKO)
• External input (slave mode)
• Output system clock generated internally
(master mode)
CMOS-level input/outputs
5 V (standard) single supply
44-pin QFP
Molybdenum-gate CMOS process
0.17 +- 0.05
■
■
THRUN
Functions
BCKO
DOUT
FEATURES
LRCO
OCLK
OCKSL
PINOUT
DMUTE
The SM5844AF operates from a 5 V supply, and is
available in 44-pin QFPs.
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Digital audio equipment, sample rate conversion
(audiovisual amplifiers, CD-R, DAT, MD and 8
mm VTRs)
Commercial recording/editing equipment, sample
rate conversion
Input data jitter elimination
MCOM
MDT/FSI1
MDT/FSI2
NIPPON PRECISION CIRCUITS LTD.
NIPPON PRECISION CIRCUITS—1
SM5844AF
Filter Characteristics and Converter
Efficiency
■
■
■
■
■
20-bit internal data word length
Deemphasis filter characteristics (IIR filter)
• ±0.03 dB gain deviation from ideal filter
characteristics
Converter noise levels
• ≤ −110 dB internally-generated noise
• −98 dB (16-bit output), −110 dB (18-bit output)
and −122 dB (20-bit output) word rounding
noise
Anti-aliasing LPF characteristics (4 FIR filters)
with automatic output/input sample rate
conversion ratio selection
• Up converter LPF (1.0 to 2.0 times)
• Down converter LPF 1 (48.0 to 44.1 kHz or
0.92 times)
• Down converter LPF 2 (44.1 to 32.0 kHz or
0.73 times)
• Down converter LPF 3 (48.0 to 32.0 kHz or
0.67 times)
Output S/N ratio (theoretical values)
S/N ratio
Output signal word
length
16 bits
16-bit input word
length
20-bit input word
length
94.8 dB
97 dB
18 bits
97.5 dB
106 dB
20 bits
97.7 dB
109 dB
Interfaces
■
Input data format
• 2s-complement, L/R alternating, serial
• Normal format (non IIS)
Mode
W ord length
1
16 bits
Front/rear
p a cking
Data
sequence
Rear
2
3
M S B fi rst
20 bits
4
■
Front
Rear
LSB first
Output data format
• 2s-complement, MSB first, L/R alternating,
serial
• Continuous bit clock
Mode
W ord length
1
16 bits
2
18 bits
3
20 bits
4
20 bits
5
16 bits
6
18 bits
7
20 bits
IIS selection
Nor mal (non
IIS)
Front/rear
p a cking
Rear
Front
IIS
NIPPON PRECISION CIRCUITS—2
SM5844AF
BLOCK DIAGRAM
IFM1
IFM2
MCOM
MDT/FSI1
MCK/FSI2
BCKI
DI
Input data
interface
Deemphasis and
attenuator setup
MLEN/DEEM
Arithmetic
operations
ICLK
ICKSL
LRCI
RSTN
Input-stage
divider
Deemphasis
operation
Input timing
controller
Attenuator
Filter characteristic
select
Interpolation
filter operation
TST1N
TST2N
Output operation
timing controller
OW18N
OW20N
Output
operation
Dither
Output format
controller
Output data
interface
IISN
SLAVE
OCLK
OCKSL
Output-stage
clock select
LRCI BCKI
DI
Output-stage
divider
Through mode
switching
Mute
generator
Direct mute
THRUN
DMUTE
STATE
LRCO
BCKO
DOUT
NIPPON PRECISION CIRCUITS—3
SM5844AF
PIN DESCRIPTION
Number1
Name
I/O 2
1, 2
DI
Ip
Data input
3, 4
BCKI
Ip
Input bit clock
5
LRCI3
Ip
Input word clock (fsi)
6
ICLK
I
Input system clock input
7
ICKSL
Ip
Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW .
Description
Input format select
8, 9
IFM1
Ip
IFM1
IFM2
W ord length
LOW
LOW
16 bits
LOW
HIGH
HIGH
LOW
HIGH
HIGH
Data sequence
Data position
Rear packed
10, 11
IFM2
Ip
M S B fi rst
20 bits
Front packed
LSB first
Rear packed
12, 13
VDD
–
5 V supply pin
14, 15
DMUTE
Ip
Direct mute pin
16
MCOM
Ip
Interface switch control pin. M D T, MCK and MLEN control when HIGH. FSI1, FSI2 and DEEM
control when LOW .
Ip
W h e n M C O M i s H I G H : Microcontroller interface
data input (MDT)
17
18
19, 20
MDT/FSI1
MCK/FSI2
MLEN/DEEM
Ip
Ip
W h e n M C O M i s L OW : Deemphasis frequency
set pins
W h e n M C O M i s H I G H : Microcontroller interface
bit clock (MCK)
FSI1
FSI2
fsi
LOW
HIGH
48.0 kHz
×
LOW
44.1 kHz
HIGH
HIGH
32.0 kHz
W h e n M C O M i s H I G H : Microcontroller data word latch clock (MLEN)
W h e n M C O M i s L OW : Deemphasis ON/OFF control (DEEM)
Output format select
When IISN = HIGH (nor mal mode)
21, 22
OW18N
Ip
OW20N
OW18N
LOW
LOW
W ord length
Data position
Front packed
20 bits
LOW
HIGH
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
OW20N
OW18N
W ord length
LOW
LOW
LOW
HIGH
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
Rear packed
When IISN = LOW (IIS mode)
23, 24
OW20N
Ip
Data position
20 bits
25, 26
IISN
Ip
IIS output mode select. Normal mode when HIGH, and IIS mode when LOW .
27
S TAT E
O
Internal operation status output (for operation check)
28
TST1N
Ip
Output dither control. Dither ON when LOW , and OFF when HIGH.
29
TST2N
Ip
Test pin. Test mode when LOW . Normal operating mode when HIGH.
IIS mode
Front packed
NIPPON PRECISION CIRCUITS—4
SM5844AF
Number1
Name
I/O 2
30, 31
RSTN
Ip
Reset pin
32, 33
VSS
–
0 V ground pin
34, 35
S L AV E
Ip
B C K O and LRCO mode set. Outputs (master mode) when LOW , and inputs (slave mode) when
HIGH.
36, 37
THRU N
Ip
DOUT through mode set. Normal mode when HIGH, and through mode when LOW .
38
OCKSL
Ip
Output system clock (OCLK) select. 384fso when HIGH, and 256fso when LOW .
39
OCLK
I
Output system clock input
40
LRCO3
I/O
Output word clock input/output (fso). Input/output mode set by the level on SLAVE.
41, 42
B C KO
I/O
Output bit clock input/output. Input/output mode set by the level on SLAVE.
43, 44
DOUT
O
Data output
Description
1. Pins which have the same name are connected internally. Accordingly, circuit connections can be made to either pin or to both pins.
2. I = input, Ip = Input with pull-up resistor (HIGH-level pins can be left open), O = output, I/O = input/output
3. fsi is the input word clock (LRCI) frequency, and fso is the output word clock (LRCO) frequency.
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0 V
P arameter
Symbol
Rating
Unit
Supply voltage range
VDD
−0.3 to 7.0
V
Input voltage range
V IN
−0.3 to V D D + 0.3
V
Storage temperature range
T stg
−40 to 125
°C
Pow er dissipation
PD
550
mW
Soldering temperature
T sld
255
°C
Soldering time
tsld
10
s
Symbol
Rating
Unit
Supply voltage range
VDD
4.75 to 5.5
V
Operating temperature range
T opr
−20 to 70
°C
Recommended Operating Conditions
VSS = 0 V
P arameter
NIPPON PRECISION CIRCUITS—5
SM5844AF
DC Electrical Characteristics
VDD = 4.75 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C
P arameter
Symbol
Current consumption
ID D
Rating
Condition
Unit
min
typ
max
–
–
80
mA
V D D = 5.0 V 1
voltage 2 ,3
V IH
0.7V D D
–
–
V
L O W -level input voltage 2 ,3
V IL
–
–
0.3V D D
V
voltage 2
V A CI
0.3V D D
–
–
V p-p
HIGH-level output voltage 4
VOH
IO H = −1.0 mA
V D D − 0.5
–
–
V
voltage 4
VOL
HIGH-level input
A C-coupled input
L O W -level output
IO L = 1.0 mA
–
–
0.4
V
IIH
V IN = V D D
–
10
20
µA
L O W -level input current 2 ,3
IIL
V IN = 0 V
–
10
20
µA
Input leakage current 3
IL H
V IN = V D D
–
–
1.0
µA
250
500
1000
kΩ
HIGH-level input current 2
Pull-up
resistance 3
R IH
1. ICKSL = LOW , OCKSL = LOW , fI C L K = 13.0 MHz, f O C L K = 13.0 MHz, no output load
2. Pins ICLK and OCLK.
3. Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OW 1 8 N , OW20N, IISN, TST1N, T S T 2 N , R S T N ,
T H R U N , O C K S L a n d S L AVE.
4. P i n s D O U T, BCKO , LRCO and STATE.
AC Electrical Characteristics
VDD = 4.75 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C
ICLK input
P arameter
Symbol
L O W -level clock
pulsewidth
tC W L
HIGH-level clock
pulsewidth
tC W H
Clock pulse cycle
tC Y
Condition
Rating
ICKSL
System clock
min
typ
max
LOW
256fsi
30
–
–
HIGH
384fsi
10
–
–
LOW
256fsi
30
–
–
HIGH
384fsi
10
–
–
LOW
256fsi
80
–
162
HIGH
384fsi
47
–
106
OCKSL
System clock
min
typ
max
Unit
ns
ns
ns
OCLK input
P arameter
Symbol
L O W -level clock
pulsewidth
tC W L
HIGH-level clock
pulsewidth
tC W H
Clock pulse cycle
tC Y
Condition
Rating
LOW
256fso
15
–
–
HIGH
384fso
10
–
–
LOW
256fso
15
–
–
HIGH
384fso
10
–
–
LOW
256fso
39
–
200
HIGH
384fso
26
–
130
Unit
ns
ns
ns
ICLK and OCLK timing
>0.7VDD
ICLK
OCLK
0.5VDD
<0.3VDD
t CWH
t CWL
t CY
NIPPON PRECISION CIRCUITS—6
SM5844AF
BCKI, DI, LRCI inputs
Rating
P arameter
Symbol
Unit
min
typ
max
B C K I L OW -level pulsewidth
tB C W L 1
50
–
–
ns
BCKI HIGH-level pulsewidth
tB C W H 1
50
–
–
ns
tB C Y 1
100
–
–
ns
DI setup time
tD S
50
–
–
ns
DI hold time
tD H
50
–
–
ns
Last BCKI rising edge to LRCI edge
tB L 1
50
–
–
ns
LRCI edge to first BCKI rising edge
tL B 1
50
–
–
ns
BCKI pulse cycle
BCKI, DI, LRCI timing
t BCY1
t BCWH1
t BCWL1
0.5VDD
BCKI
t DS
t DH
0.5VDD
DI
t BL1
t LB1
0.5VDD
LRCI
BCKO, LRCO (Inputs when SLAVE = HIGH)
Rating
P arameter
Symbol
Unit
min
typ
max
B C K O L OW -level pulsewidth
tB C W L 2
78
–
–
ns
B C K O HIGH-level pulsewidth
tB C W H 2
78
–
–
ns
tB C Y 2
156
–
–
ns
Last BCKO rising edge to LRCO edge
tB L 2
78
–
–
ns
LRCO edge to first BCKO rising edge
tL B 2
78
–
–
ns
B C K O pulse
cycle 1
1. B C KO clock inputs exceeding 64fso cannot be detected, and will cause incorrect operation.
NIPPON PRECISION CIRCUITS—7
SM5844AF
BCKO, LRCO timing
t BCY2
t BCWH2
t BCWL2
0.5VDD
BCKO
t BL2
t LB2
0.5VDD
LRCO
MDT, MCK, MLEN inputs
Rating
P arameter
Symbol
Unit
min
typ
max
M C K a n d M L E N r ise time 1
tr
–
–
100
ns
MCK and MLEN fall time 1
tf
–
–
100
ns
MDT setup time
tM D S
50
–
–
ns
MDT hold time
tM D H
50
–
–
ns
MLEN setup time
tM C S
50
–
–
ns
MLEN hold time
tM C H
50
–
–
ns
M L E N L OW -level pulsewidth
tM E W L
50
–
–
ns
MLEN HIGH-level pulsewidth
tM E W H
50
–
–
ns
1. tr and t f are the input waveform transition times measured between 0.1V D D and 0.9V D D levels.
MDT, MCK, MLEN timing
0.5VDD
MDT
t MDS
t MDH
0.5VDD
MCK
t MCS
t MCH
0.5VDD
MLEN
t MEWL
t MEWH
NIPPON PRECISION CIRCUITS—8
SM5844AF
DEEM, DMUTE inputs
Rating
P arameter
Symbol
Unit
min
typ
max
Rise time
tr
–
–
100
ns
Fall time
tf
–
–
100
ns
DOUT, BCKO, LRCO input/outputs
SLAVE = LOW (outputs), CL = 15 pF
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
LRCO pulse cycle
tL O C Y
–
1/fso
–
ns
L R C O L OW -level pulsewidth
tL O C L
–
1/2fso
–
ns
LRCO HIGH-level pulsewidth
tL O C H
–
1/2fso
–
ns
O C K S L = L OW
–
1/64fso
–
B C K O pulse cycle
tB O C Y
OCKSL = HIGH
–
1/48fso
–
O C K S L = L OW
–
1/128fso
–
OCKSL = HIGH
–
1/96fso
–
O C K S L = L OW
–
1/128fso
–
OCKSL = HIGH
–
1/96fso
–
ts b H 1
From OCLK fall to BCKO
rise
10
–
70
ns
tsbL1
From OCLK fall to BCKO
fall
10
–
70
ns
ts b H 2
From OCLK fall to BCKO
rise
15
–
80
ns
tsbL2
From OCLK fall to BCKO
fall
15
–
80
ns
tb d H 1
Fr o m B C KO fall to DOUT
rise
0
–
20
ns
tb d L 1
Fr o m B C KO fall to DOUT
fall
0
–
20
ns
B C K O L OW -level pulsewidth
B C K O HIGH-level pulsewidth
O C L K t o B C KO delay time
( O C K S L = L OW )
O C L K t o B C KO delay time
(OCKSL = HIGH)
B C K O to DOUT and LRCO delay
time
tB O W L
tB O W H
ns
ns
ns
SLAVE = HIGH (inputs), CL = 15 pF
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
tb d H 2
Fr o m B C KO fall to DOUT
rise
10
–
100
ns
tb d L 2
Fr o m B C KO fall to DOUT
fall
10
–
100
ns
B C K O to DOUT delay time
NIPPON PRECISION CIRCUITS—9
SM5844AF
DOUT, BCKO, LRCO timing
OCLK
BCKO
t sbL1, t sbL2
t sbH1, t sbH2
t BOWH
t BOWL
t BOCY
BCKO
t bdH, t bdL
DOUT
t bdH
t bdL
LRCO
t LOCH
t LOCL
t LROOY
NIPPON PRECISION CIRCUITS—10
SM5844AF
Filter Characteristics
Anti-aliasing filter frequency characteristic
0
48k
20
48k
44.1k
32k
40
Attenuation (dB)
44.1k
32k
Up conversion
60
80
100
120
140
0.250
0.300
0.350
0.400
0.450
Frequency (fs)
0.500
0.550
0.600
0.650
Deemphasis filter frequency characteristic
0
48.0 kHz
44.1 kHz
32 kHz
2
–20
4
–40
6
–60
Phase characteristic, Θ (°)
Attenuation (dB)
0
48.0, 44.1 and 32 kHz
8
10
Phase
Attenuation
12
10
20
50
100
200
500
1k
Frequency (Hz)
2K
5k
10k
20k
NIPPON PRECISION CIRCUITS—11
SM5844AF
FUNCTIONAL DESCRIPTION
Input Data Interface (DI, LRCI, BCKI, IFM1, IFM2)
Mode
IFM1
IFM2
W ord length
1
LOW
LOW
16 bits
2
LOW
HIGH
3
HIGH
LOW
4
HIGH
HIGH
Data position
Data
sequence
Rear packed
M S B fi rst
20 bits
Front packed
Rear packed
C o m m o n f eatures
Non IIS
L/R alternating
Bit serial
LSB first
Attenuator and Deemphasis Selection
The attenuator is set using the microcontroller
interface. When the attenuator is used, deemphasis
settings also need to be set using the microcontroller
interface. The microcontroller interface comprises
MDT, MCK and MLEN, and is used to receive all
input serial data.
Table 1. Attenuator and deemphasis function
selection
Function set method
External pins
( M C O M = L OW )
Microcontroller
interface flags
(MCOM = HIGH)
Deemphasis
ON/OFF
DEEM
FDEEM
Deemphasis
frequency (fsi)
select
FSI1, FSI2
FFSI1, FFSI2
N/A (no attenuation)
11 bits (a1 to a11)
Irreversible
(test mode 1)
FTST1, FTST2
Function
Attenuator data set
Test mode select
When MCOM is HIGH, serial data received on
MDT, MCK and MLEN sets the attenuation data and
control flag data.
When MCOM is LOW, the logic levels on FSI1,
FSI2 and DEEM select the device function.
NIPPON PRECISION CIRCUITS—12
SM5844AF
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, MDT (data), MCK (clock)
and MLEN (latch enable clock) interface pins are
used.
latched into the mode register on the rising edge of
the latch enable clock MLEN.
The mode register addressed is determined by the 1st
bit of the 12 data bits before MLEN goes HIGH. If
this bit is LOW, then the data is read into the
attenuation data register as shown in figure 1. If this
bit is HIGH, then the data is read into the mode flag
register as shown in figure 2. The function of each bit
in the mode flag register is described in table 1.
Input data on MDT is synchronized to the MCK
clock. Data is read into the input stage shift register
on the rising edge of MCK. Accordingly, the input
data should change on the falling edge of MCK.
Input data enters an internal SIPO (serial-to-parallel
converter register), and then the parallel data is
MDT
B1
B2
B3
B4
B8
B9
B10
B11
LOW
a0
a1
a2
a6
a7
a8
a9
MSB
B12
a10
LSB
MCK
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 1. Attenuation data format (B1 = LOW)
B1
MDT
HIGH
B2
* *
B5
Not used
B6
B7
B8
B9
B10
B11
B12
FTST1
FTST2
FRATE
F12DB
FFSI1
FFSI2
FDEEM
MCK
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 2. Mode flag data format (B1 = HIGH)
NIPPON PRECISION CIRCUITS—13
SM5844AF
Table 2. Mode flag description
Mode function select
B1
Bit
Reset
mode
M o d e fl ag
P arameter
B2 to B5
L OW/HIGH
Select
Not used
T S T 2 N = L OW
B6
B7
B8
FTST1
FTST2
F R AT E
Test mode select 1
Test mode select 2
B10
F12DB
FFSI1
FTST1
Mode
LOW
LOW
0
LOW
HIGH
1
HIGH
LOW
2
HIGH
HIGH
3
LOW
Input/output sample rate ratio check after every
output
HIGH
Input/output sample rate ratio check for high
accuracy after every 2048 outputs
LOW
Nor mal operation (no shift)
HIGH
+12 dB gain shift
LOW
LOW
LOW
Input/output rate
HIGH
B9
FTST2
Attenuator
LOW
Deemphasis filter fs
select 1
FFSI2
FFSI1
fsi
LOW
LOW
LOW
HIGH
HIGH
LOW
48.0 kHz
HIGH
HIGH
32.0 kHz
LOW
44.1 kHz
B11
B12
FFSI2
FDEEM
Deemphasis filter fs
select 2
Deemphasis control
ON/OFF
LOW
Deemphasis filter OFF
HIGH
Deemphasis filter ON
LOW
LOW
Deemphasis (DEEM, FSI1, FSI2 pins or FDEEM, FFSI1, FFSI2 flags)
The digital deemphasis filter is an IIR filter with variable coefficients to faithfully reproduce the gain and
phase characteristics of standard analog deemphasis
filters.
The filter coefficients are selected by FSI1 (or FFSI1
flag) and FSI2 (or FFSI2 flag) to correspond to the
sampling frequencies fs = 44.1, 48.0 and 32.0 kHz.
Table 3. Deemphasis ON/OFF
W h e n M C O M = L OW
When MCOM = HIGH
Deemphasis
DEEM = HIGH
FDEEM = HIGH
ON
D E E M = L OW
F D E E M = L OW
OFF
Table 4. Deemphasis fs select (FSI1, FSI2 pins or
FFSI1, FFSI2 flags)
M C O M = L OW ( M C O M = H I G H )
fs
FSI1 (FFSI1)
FSI2 (FFSI2)
LOW
LOW
HIGH
LOW
LOW
HIGH
48.0 kHz
HIGH
HIGH
32.0 kHz
44.1 kHz
NIPPON PRECISION CIRCUITS—14
SM5844AF
Attenuation (MDT, MCK, MLEN)
The digital attenuator coefficients are read in as
serial data on the microcontroller interface. Data on
MDT is read into the internal shift register on the
rising edge of MCK, and then 12 bits are latched
internally on the rising edge of MLEN.
MDT
When the leading bit is 0 (B1 = LOW), the following
11 bits are read into the attenuation register and used
as an unsigned integer in MSB first format. See
figure 3.
B1
B2
B3
B4
B8
B9
B10
B11
LOW
a0
a1
a2
a6
a7
a8
a9
B12
a10
MSB
LSB
MCK
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 3. Attenuation data format (microcontroller interface)
Although the attenuation data comprises 11 bits,
only 1025 levels are valid as given by the following.
10
DATT =
∑
ai × 2
DATT
Gain = 20 × log  ---------------- [dB]
 1024 
when F12DB = LOW
( 10 – i )
i=0
DATT
= 20 × log  ---------------- [dB]
 256 
The gain of the attenuator for values of DATT from
001H to 400H are given by the following equations.
Note that when the F12DB flag is HIGH, the gain is
shifted by +12.0412 dB.
when F12DB = HIGH
After a system reset initialization, DATT is set to
400H and the F12DB flag is LOW, corresponding to
0 dB gain. (The F12DB flag is described in table 2.)
Table 5. Attenuator settings
F 1 2 D B = L OW (default)
F12DB = HIGH
Attenuation data DAT T
Gain (dB)
Linear expression
Gain (dB)
Linear expression
000H
−∞
0.0
−∞
0.0
001H
−60.206
1/1024
−48.165
1/256
↓
↓
↓
↓
↓
100H
−12.041
256/1024
0.0
256/256
↓
↓
↓
↓
↓
3FFH
−0.0085
1023/1024
12.032
1023/256
400H (to 7FFH)
0
1.0
12.041
4.0
NIPPON PRECISION CIRCUITS—15
SM5844AF
Attenuator operation
A change in the attenuation data DATT causes the
gain to change smoothly from its previous value
towards the new setting. The new attenuation data is
stored in the attenuation data register and the current
attenuation level is stored in a temporary register.
Consequently, if a new attenuation level is read in
before the previously set level is reached, the gain
changes smoothly from the current value towards the
latest setting as shown in figure 4.
The attenuation counter output changes, and hence
the gain changes, by 1 step every output sample. The
time taken to reduce the gain from 0 dB (or 12 dB) to
−∞ dB is (1024/fso), which corresponds to
approximately 23.2 ms when fso = 44.1 kHz.
Level 1
Level 5
0 dB
Level 3
Gain
Level 2
−∞
∆t
Level 4
Time
Figure 4. Attenuator operation example
NIPPON PRECISION CIRCUITS—16
SM5844AF
Direct Mute (DMUTE)
Direct mute ON/OFF
Table 6. DMUTE operation
DMUTE
Function
LOW
Nor mal data is output from the next output word (mute
OFF)
HIGH
0 data is output from the next output word (mute ON)
Reset mute
Table 7. RSTN mute operation
RSTN
Function
LOW
0 data is output from the next output word (mute ON)
HIGH
Nor mal data is output from the 3073rd output word
( m ute OFF)
Internal operating status (STATE)
Internally, all functions are performed using 20-bit
serial data, and the conversion rate and filter type are
automatically selected for output. Output data is in
20-bit front-packed format.
Table 8. Bit function
Output bit position
1st to 18th
19th
20th
Content
(Output data cycle/input data cycle) − 9
Ex.
1st
18th
00.1111111111110111 ⇒ 1.0 times
01.1111111111110111 ⇒ 2.0 times (1/2 conversion rate ratio)
00.0111111111110111 ⇒ 0.5 times (2.0 conversion rate ratio)
DA1
DA0
Selected filter type
DA1
DA0
Filter
Mode
0
0
Up converter
1
1
0
44.1 to 48 kHz
2
0
1
32 to 44.1 kHz
3
1
1
32 to 48 kHz
4
Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE
output.
NIPPON PRECISION CIRCUITS—17
SM5844AF
System Clock
Input system clock (ICLK, ICKSL)
Output system clock (OCLK, OCKSL)
The input system clock can be set to run at either
256fsi or 384fsi, where fsi is the input frequency on
LRCI.
The output system clock can be set to run at either
256fso or 384fso, where fso is the input frequency on
LRCO. In through mode, OCLK and OCKSL have
no function and are not used.
Note that ICLK and LRCI should be divided from a
common clock source or PLL to maintain
synchronism.
Table 9. ICLK system clock
ICKSL
ICLK system clock rate
HIGH
384fsi
LOW
256fsi
Note that in slave mode, a suitable clock must be
input on OCLK. The clock on OCLK should ideally
have a protection circuit to prevent incorrect
operation for times when the clock on ICLK is
halted.
Table 10. OCLK system clock
S L AV E
OCKSL
O C L K s y s t e m clock rate
HIGH
384fso
LOW
256fso
×
Not used
LOW
HIGH
Output data interface and output clock selection (LRCO, BCKO, DOUT, SLAVE)
Table 11. Output mode description
Function
THRUN
S L AV E
Mode
Description
L R C O , B C KO state
LOW
Master mode
Output word clock (LRCO) and output bit clock
( B C KO) are divided from OCLK.
Outputs
HIGH
Slave mode
Output word clock (LRCO) and output bit clock
( B C KO) are supplied externally.
Inputs 1
Through mode
Output word clock (LRCO), output bit clock
( B C KO) and output data (DOUT) are the
same as LRCI, BCKI and DI, respectively.
Outputs
HIGH
LOW
×
1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.
System Reset (RSTN)
Through Mode (THRUN)
At power-ON, all device functions must be reset. The
device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic
operation, output timing counter and internal flag
register operation are synchronized on the next LRCI
rising edge. Note that all flags are set to their defaults
(all LOW).
Table 12. THRUN operation
THRUN
Mode
Description
LOW
Through mode
Direct connections are made: LRCI
to LRCO, BCKI to BCKO , and DI to
D O U T.
HIGH
Nor mal mode
Sample rate converter operation
A power-ON reset signal can be applied from an
external microcontroller. For systems where ICLK
and LRCI are stable at power ON, initialization can
be performed by connecting a 0.001 µF capacitor
between RSTN and VSS. Otherwise, a capacitor
value should be chosen such that RSTN does not go
HIGH until after LRCI and ICLK have stabilized.
NIPPON PRECISION CIRCUITS—18
SM5844AF
Internal Arithmetic Timing Auto-reset
Output Timing Calculation
The clock on LRCI should pass through 1 cycle for
every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW)
ICLK clock cycles to maintain correct internal
arithmetic sequence. If the number of ICLK cycles is
different, increases or decreases, or any jitter is
present, device operation could be affected.
The output timing is calculated to maintain the
desired ratio between the output data cycle and the
input data cycle.
There is a fixed-value tolerance within which the
internal sequence and LRCI clock timing are not
adversely affected.
Table 13. Clock tolerance
ICKSL
Allow a b le clock variation
HIGH (384fs mode)
+8/−6 cycles
L O W (256fs mode)
+4/−3 cycles
The output is in MSB-first, 2s-complement, L/R
alternating, bit serial format with a continuous bit
clock.
Table 14. Output format selection
IISN
1
2
3
HIGH
HIGH
Output format
OW20N OW18N
HIGH
W ord
length
HIGH
LOW
18 bits
LOW
HIGH
20 bits
LOW
LOW
20 bits
5
HIGH
HIGH
16 bits
HIGH
LOW
18 bits
LOW
×
20 bits
7
LOW
Front/rear
p a cking
16 bits
4
6
IIS
selection
Non IIS
IIS
The ratio between the output sample rate and input
sample rate is measured automatically and the most
suitable filter type for this ratio is selected
automatically.
Mode
Filter
fs ratio (fso/fsi)
Selects range
1
Up converter
1.0 to 2.0
≥ 0.97
2
48.0 to 44.1 kHz
0.91875
0.865 to 0.97
3
44.1 to 32.0 kHz
0.72562
0.711 to 0.865
4
48.0 to 32.0 kHz
0.66667
≤ 0.711
When the selected fs conversion ratio and the actual
sample rate conversion ratio do not coincide, the
following phenomenon are generated.
Output Format Control (OW18N,
OW20N, IISN)
Mode
Conversion rates from 0.5 to 2.0 times are supported
using the following 4 filter types.
Table 15. fs ratio and filter selection
Whenever the allowable tolerance is exceeded, the
internal sequence is automatically reset so that the
internal sequence matches the LRCI clock. When
this occurs, there is a possibility that click noise will
be generated.
Inputs
Filter Characteristic Selection
Rear
Table 16. fs ratio mismatch
Condition
Affect
Actual sample rate conversion
ratio is low er than the selected
filter conversion ratio
The audio band high-pass
develops aliasing noise.
Actual sample rate conversion
ratio is higher than the selected
filter conversion ratio
The audio band high-pass is cut
off.
Note: An output noise may be generated if the fs conversion ratio
changes at a rate greater than 0.057%/sec.
Front
NIPPON PRECISION CIRCUITS—19
SM5844AF
TIMING DIAGRAMS
Input Timing Examples (DI, BCKI, LRCI)
Audio data input timing (rear-packed 16-bit word, IFM1 = LOW, IFM2 = LOW)
1/fs
Left-channel data
Right-channel data
MSB
DI
1
2
14
15
LSB
MSB
16
1
LSB
2
14
15
16
BCKI
LRCI
Audio data input timing (rear-packed 20-bit word, IFM1 = LOW, IFM2 = HIGH)
1/fs
Left-channel data
Right-channel data
MSB
DI
1
2
18
19
LSB
MSB
20
1
LSB
2
18
19
20
BCKI
LRCI
Audio data input timing (front-packed 20-bit word, IFM1 = HIGH, IFM2 = LOW)
1/fs
Left-channel data
Right-channel data
MSB
DI
1
2
3
19
LSB
MSB
20
1
LSB
2
3
19
20
1
BCKI
LRCI
All data bits after the LSB (20th bit) are ignored. Accordingly, more than 20 BCKI cycles are required.
NIPPON PRECISION CIRCUITS—20
SM5844AF
Audio data input timing (rear-packed 20-bit word, LSB first, IFM1 = HIGH, IFM2 = HIGH)
1/fs
Left-channel data
Right-channel data
LSB
DI
1
2
18
MSB
LSB
20
1
19
MSB
2
18
19
20
BCKI
LRCI
Output Timing Examples (DOUT, BCKO, LRCO)
Audio data output timing (rear-packed 16-bit word)
1/fso
Left-channel data
Right-channel data
MSB
DOUT
1
2
15
LSB
MSB
16
1
LSB
2
15
16
BCKO
LRCO
Audio data output timing (rear-packed 18-bit word)
1/fso
Left-channel data
Right-channel data
MSB
DOUT
1
2
17
LSB
MSB
18
1
LSB
2
17
18
BCKO
LRCO
Audio data output timing (rear-packed 20-bit word)
1/fso
Left-channel data
Right-channel data
MSB
DOUT
1
2
19
LSB
MSB
20
1
LSB
2
19
20
BCKO
LRCO
NIPPON PRECISION CIRCUITS—21
SM5844AF
Audio data output timing (front-packed 20-bit word, OW18N = LOW, OW20N = LOW)
1/fso
Left-channel data
Right-channel data
MSB
DOUT
1
2
19
LSB
MSB
20
1
LSB
2
19
20
BCKO
LRCO
Audio data output timing (IIS mode, front-packed 16/18/20-bit word selected by OW18N and
OW20N)
1/fso
Left-channel data
Right-channel data
MSB
DOUT
1
2
16
17
18
19
LSB
MSB
20
1
LSB
2
16
17
18
19
20
BCKO
LRCO
Data is output in 20-bit units.
State Data Output Timing
State data output timing (IISN = HIGH)
1/fso
State data
MSB
STATE
1
LSB
2
19
20
BCKO
LRCO
State data output timing (IISN = LOW)
1/fso
State data
MSB
STATE
1
LSB
2
19
20
BCKO
LRCO
NIPPON PRECISION CIRCUITS—22
SM5844AF
Delay Time
tINPUT is the time when the serial input data has been
read in completely (on the rising edge of LRCI).
tOUTPUT is the time when the serial output data has
been read out completely (on the rising edge of
LRCO). The delay between input and output is given
by tOUTPUT − tINPUT = (49 ± 2)/fsi.
1/fs
LRCI
Serial data input
49 ±2
t input
LRCO
Serial data output
1/fso
t output
t INPUT
t OUTPUT – t INPUT
t OUTPUT
NIPPON PRECISION CIRCUITS—23
SM5844AF
TYPICAL APPLICATIONS
Input Interface Circuits
Digital audio interface receiver (PD0052)
VCOOUT
384fs
ICLK
ICKSL
DIR
PD0052
LRCK
LRCI
BCK
BCKI
DI
DATA
MLEN/DEEM
EMP
32k
44.1k
SM5844AF
MCOM
MODE
48k
MDT/FSI1
1FM1
MCK/FSI2
1FM2
Digital audio interface transceiver(YM3613)
OCKSL
OCLK
SM5844AF
384fs 16.9344 MHz
øA
LRCO
WCI
BCKO
BCI
DOUT
DIN
IISN
DIT
YM3613
OW18N
OW20N
SEL
THRUN
SLAVE
NIPPON PRECISION CIRCUITS—24
SM5844AF
APPLICATION NOTE
Delay in the slave mode
In the slave mode , the delay (tbdH2, tbdL2)of
DUOT from BCKO is MIN= 10ns, MAX= 100ns
which is ratter wide width.
As specified in AC Electrical Characteristics, and
BCKO is prohibited from inputting longer than
64fso.
When tbdH2, tbdL2 is maximum 100ns, ideal timing
may not be attained for the following devise,
depending on the OCLK cycle (example 1).
Please use considering the timing in the following
examples in the slave mode.
(example 1) OCLK= 39ns(fs= 99.84kHz), OCKSL= L(256fs), BCKO(64fso)= 156ns, OW20N= L, OW 1 8 N = H
LRCO
BCKO
(LSB)
DOUT
L2
100ns
L1
100ns
156ns
(example 2) OCLK= 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N= L, OW 1 8 N = H
LRCO
BCKO
(LSB)
DOUT
L2
100ns
L1
100ns
354ns
NIPPON PRECISION CIRCUITS—25
SM5844AF
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinaft er,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS LTD.
4-3, Fukuzumi 2 chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9308DE
2000.09
NIPPON PRECISION CIRCUITS—26