SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 D 100-ns Instruction Cycle Time D 1568 Words of Configurable On-Chip D D D D D D D D D D D D D D D D D D D D D Data/Program RAM 256 Words of On-Chip Program ROM 128K Words of Data/Program Space Pin-for-Pin Compatible with the SMJ320C25 16 Input and 16 Output Channels 16-Bit Parallel Interface Directly Accessible External Data Memory Space Global Data Memory Interface 16-Bit Instruction and Data Words 32-Bit ALU and Accumulator Single-Cycle Multiply/Accumulate Instructions 0 to 16-Bit Scaling Shifter Bit Manipulation and Logical Instructions Instruction Set Support for Floating-Point Operations, Adaptive Filtering, and Extended-Precision Arithmetic Block Moves for Data/Program Management Repeat Instructions for Efficient Use of Program Space Eight Auxiliary Registers and Dedicated Arithmetic Unit for Indirect Addressing Serial Port for Direct Codec Interface Synchronization Input for Multiprocessor Configurations Wait States for Communications to Slow Off-Chip Memories/Peripherals On-Chip Timer for Control Operations Three External Maskable User Interrupts 68-PIN GB PIN GRID ARRAY CERAMIC PACKAGE† (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L † See Pin Assignments Table (Page 2) and Pin Nomenclature Table (Page 3) for location and description of all pins. D Input Pin Polled by Software Branch D D D D D D D D Instruction Programmable Output Pin for Signalling External Devices 1.6-µm CMOS Technology Single 5-V Supply Packaging: 68-Pin Leaded Ceramic Chip Carrier (FJ Suffix) 68-Pin Leadless Ceramic Chip Carrier (FD Suffix) 68-Pin Grid Array Ceramic Package (GB Suffix) Military Operating Temperature Range . . . – 55° to 125°C description The SMJ320C26 Digital Signal Processor is a member of the TMS320 family of VLSI digital signal processors and peripherals. The TMS320 family supports a wide range of digital signal processing applications, such as telecommunications, modems, image processing, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, and other computation intensive applications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated ! " #$ %!& % "! "! '! ! !( ! %% )*& % "!+ %! !!$* $ %! !+ $$ "!!& POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 68-PIN FJ AND FD LEADED AND LEADLESS CERAMIC CHIP CARRIER PACKAGES† (TOP VIEW) description D8 D9 D10 D11 D12 D13 D14 D15 MP/MC BIO HOLD READY RS CLKR CLKX VCC VCC With a 100-ns instruction cycle time and an innovative memory configuration, the SMJ320C26 performs operations necessary for many real time digital signal processing algorithms. Since most instructions require only one cycle, the SMJ320C26 is capable of executing ten million instructions per second. On-chip programmable data/program RAM of 1568 words of 16 bits, on-chip program ROM of 256-words, direct addressing of up to 64K-words of external program and 64K-words of data memory space, and multiprocessor interface features for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the processor. VSS D7 D6 D5 D4 D3 D2 D1 D0 SYNC INT0 INT1 INT2 VCC DR FSR A0 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 IACK MSC CLKOUT1 CLKOUT2 XF HOLDA DX FSX X2/CLKIN X1 BR STRB R/W PS IS DS VSS VSS A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 The SMJ320C26 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1. 10 11 12 13 14 15 16 † See Pin Assignments Table (Page 2) and Pin Nomenclature Table (Page 3) for location and description of all pins. PGA/LCCC/JLCC PIN ASSIGNMENTS FUNCTION 2 PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN A0 K1/26 A12 K8/40 D2 E1/16 D14 A5/3 INT2 H1/22 A1 K2/28 A13 L9/41 D3 D2/15 D15 B6/2 IS J11/46 A2 L3/29 A14 K9/42 D4 D1/14 DR J1/24 MP/MC A6/1 A3 K3/30 A15 L10/43 D5 C2/13 DS K10/45 MSC C10/59 A4 L4/31 BIO B7/68 D6 C1/12 DX E11/54 PS J10/47 A5 K4/32 BR G11/50 D7 B2/11 FSR J2/25 READY A6 L5/33 CLKOUT1 C11/58 D8 A2/9 FSX F10/53 A7 K5/34 CLKOUT2 D10/57 D9 B3/8 HOLD A7/67 A8 K6/36 CLKR B9/64 D10 A3/7 HOLDA A9 L7/37 CLKX A9/63 D11 B4/6 A10 K7/38 D0 F1/18 D12 A4/5 A11 L8/39 D1 E2/17 D13 B5/4 POST OFFICE BOX 1443 FUNCTION PIN VCC VCC H2/23 VSS VSS B1/10 VSS XF L2/27 B8/66 RS A8/65 X1 G10/51 R/W H11/48 X2/CLKIN F11/52 E10/55 STRB H10/49 IACK B11/60 SYNC F2/19 INT0 G1/20 A10/61 INT1 G2/21 VCC VCC • HOUSTON, TEXAS 77251–1443 B10/62 L6/35 K11/44 D11/56 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PIN NOMENCLATURE NAME I/O/Z† DEFINITION VCC VSS I 5-V supply pins. I Ground pins. X1 O Output from internal oscillator for crystal. X2/CLKIN I Input to internal oscillator from crystal or external clock. CLKOUT1 O Master clock output (crystal or CLKIN frequency/4). O A second clock output signal. CLKOUT2 D15–D0 I/O/Z 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces. A15–A0 O/Z 16-bit address bus A15 (MSB) through A0 (LSB). PS, DS, IS O/Z Program, data and I/O space select signals. R/W O/Z Read/write signal. STRB O/Z Strobe signal. RS I Reset input. INT2, INT1, INT0 I External user interrupt inputs. MP/MC I Microprocessor/microcomputer mode select pin. MSC O Microstate complete signal. IACK O Interrupt acknowledge signal. READY I Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction is complete. BR O Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space. XF O External flag output (latched software – programmable signal). HOLD I Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines in the high-impedance state. HOLDA O Hold acknowledge signal. SYNC I Synchronization input. BIO I Branch control input. Polled by BIOZ instruction. DR I Serial data receive input. CLKR I Clock input for serial port receiver. I Frame synchronization pulse for receive input. FSR DX CLKX O/Z I Serial data transmit output. Clock input for serial port transmitter. FSX I/O/Z Frame synchronization pulse for transmit. May be configured as either an input or an output. † I/O/Z denotes input/output/high-impedance state. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 functional block diagram PS DS IS SYNC X1 X2/CLKIN CLKOUT1 CLKOUT2 PROGRAM BUS 16 16 QIR(16) IR(16) ST0(16) ST1(16) RPTC(8) IFR(6) 16 16 16 R/W STRB READY BR XF HOLD HOLDA MSC BIO RS IACK CONTROLLER PFC(16) 16 MCS(16) 16 STACK (8 - 16) ADDRESS 16 MUX 16 A15–A0 16 PROGRAM ROM (256 x 16) 3 INT(2-0) DR CLKR FSR DX CLKX FSX 16 PC(16) 16 16 16 MP/MC 16 16 MUX 16 16 16 INSTRUCTION 6 8 16 16 MUX 16 D15–D0 16 16 RSR(16) XSR(16) DRR(16) DXR(16) TIM(16) PRD(16) IMR(6) GREG(8) 16 PROGRAM BUS DATA BUS 16 16 16 16 3 16 16 AR0(16) AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) 3 ARP(3) 3 ARS(3) SHIFTER(0–16) 9 16 MULTIPLIER DP(9) 9 7 LSB FROM IR PR(32) 32 32 16 16 3 SHIFTER (6.0.1.4) ARAU(16) MUX 16 MUX MUX MUX 16 MUX 16 DATA RAM (32 x 16) BLOCK B2 MUX TR(16) 16 DATA/PROG RAM (512 x 16) BLOCK B3 32 MUX 16 DATA/PROG RAM (512 x 16) BLOCK B1 ALU(32) 32 DATA/PROG RAM (512 x 16) BLOCK B0 32 C ACCH(16) ACCL(16) 32 MUX MUX MUX SHIFTERS (0–7) 16 16 16 16 16 16 DATA BUS LEGEND: ACCH = ACCL = ALU = ARAU = ARS = ARP = DP = DRR = DXR = 4 Accumulator high Accumulator low Arithmetic logic unit Auxiliary register arithmetic unit Auxiliary register pointer buffer Auxiliary register pointer Data memory page pointer Serial port data receive register Serial port data trademark register IFR IMR IR MCS QIR PR PRD TIM TR = = = = = = = = = Interrupt flag register Interrupt mask register Instruction register Microcall stack Queue instruction register Product register Product register for timer Timer Temporary register POST OFFICE BOX 1443 PC PFC RPTC GREG RSR XSR AR0–AR7 ST0, ST1 C • HOUSTON, TEXAS 77251–1443 = = = = = = = = = Program counter Prefetch counter Repeat instruction counter Global memory allocation register Serial port receive shift register Serial port to transmit shift register Auxiliary registers Status registers Carry bit SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 architecture The SMJ320C26 architecture is based on the SMJ320C25 with a different internal RAM and ROM configuration. The SMJ320C26 integrates 256 words of on-chip ROM and 1568 words of on-chip RAM compared to 4K words of on-chip ROM and 544 words of on-chip RAM for the SMJ320C25. The SMJ320C26 is pin for pin compatible with the SMJ320C25. Increased throughput on the SMJ320C26 for many DSP applications is accomplished by means of single cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data intensive signal processing. The architectural design of the SMJ320C26 emphasizes overall speed, communication, and flexibility in the processor configuration. Control signals and instructions provide floating point support, block memory transfers, communication to slower off-chip devices, and multiprocessing implementations. Three large on-chip RAM blocks, configurable either as separate program and data spaces or as three contiguous data blocks, provide increased flexibility in system design. Programs of up to 256 words can be masked into the internal program ROM. The remainder of the 64K-word program memory space is located externally. Large programs can execute at full speed from this memory space. Programs can also be downloaded from slow external memory to high speed on-chip RAM. A data memory address space of 64K words is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SMJ320C26 incorporates all of these features as well as many others, including a hardware timer, serial port, and block data transfer capabilities. 32-bit ALU accumulator The SMJ320C26 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and logic instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following capabilities: D Branch to an address specified by the accumulator. D Normalize fixed point numbers contained in the accumulator. D Test a specified bit of a word in data memory. One input to the ALU is always provided from the accumulator, and the other input may be provided from the Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator. The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. scaling shifter The SMJ320C26 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16-bits on the input data, as specified in the instruction word. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign extended, depending upon the value of the SXM (sign extension mode) bit of status register STO. 16 × 16 bit parallel multiplier The SMJ320C26 has a 16 × 16 bit-hardware multiplier, which is capable of computing a signed or unsigned 32-bit product in a single machine cycle. The multiplier has the following two associated registers: D A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and D A 32-bit Product Register (PR) that holds the product. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 16 × 16 bit parallel multiplier (continued) Incorporated into the SMJ320C26 instruction set are single-cycle multiply/accumulate instructions that allow both operands to be fetched simultaneously. The data for these operations may reside anywhere in internal or external memory, and can be transferred to the multiplier each cycle via the program and data buses. Four product shift modes are available at the Product Register (PR) output that are useful when performing multiply/accumulate operations, fractional arithmetic, or justifying fractional products. timer The SMJ320C26 provides a memory mapped 16-bit timer for control operations. The on-chip timer (TIM) register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every time the timer decrements to zero, provided the timer interrupt is enabled. The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT1. memory control The SMJ320C26 provides a total of 1568 words of 16 bit on-chip RAM, divided into four separate blocks (B0, B1, B2, and B3). Of the 1568 words, 32 words (block B2) are always data memory, and all other blocks are programmable as either data or program memory. A data memory size of 1568 words allows the SMJ320C26 to handle a data array of 1536 words, while still leaving 32 locations for intermediate storage. When using B0, B1, or B3 as program memory, instructions can be downloaded from external memory into on-chip RAM, and then executed. When using on-chip program RAM, ROM, or high speed external program memory, the SMJ320C26 runs at full speed without wait states. However, the READY line can be used to interface the SMJ320C26 to slower, less expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM speeds processing and cuts overall system costs. The SMJ320C26 provides three separate address spaces for program memory, data memory, and I/O. The on-chip memory is mapped into either the data memory or program memory space, depending upon the choice of memory configuration. The instruction configuration (parameter) is used as follows to configure the blocks B0, B1, and B3 as program or as data memory. CONFIGURATION B0 B1 B3 0 1 2 3 Data Program Program Program Data Data Program Program Data Data Data Program Regardless of the configuration, the user may still execute from external program memory. The SMJ320C26 provides a ROM of 256 words. The ROM is sufficient to allow the programming of a bootstrap program and interrupt handler, or to implement self test routines. The SMJ320C26 has six registers that are mapped into the data memory space at the locations 0–5; a serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, and global memory allocation register. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 memory control (continued) MEMORY MAPS AFTER A RESET OR CONF 0 1 MP/MC = 1 PROGRAM 0 (0000h) INTERRUPTS AND RESERVED (EXTERNAL) 31 (001Fh) 32 (0020h) 5 (0005h) 6 (0006h) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) EXTERNAL I/O DATA 0 (0000h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 0 ON-CHIP MMRs EXTERNAL 15 RESERVED PAGE 0 ON-CHIP BLOCK B2 RESERVED PAGE 1-3 ON-CHIP BLOCK B0 PAGE 4-7 ON-CHIP BLOCK B1 PAGE 8-11 ON-CHIP BLOCK B3 PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) 65535 (FFFFh) 2 MP/MC = 0 PROGRAM 0 (0000h) INTERRUPTS AND RESERVED BOOTLOAD ROM 255 (00FFh) 256 (0100h) 5 (0005h) 6 (0006h) 95 (005Fh) 96 (0060h) RESERVED 127 (007Fh) 128 (0080h) 4095 (0FFFh) 4096 (1000h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) EXTERNAL 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) I/O DATA 0 (0000h) 0 ON-CHIP MMRs EXTERNAL 15 RESERVED PAGE 0 ON-CHIP BLOCK B2 RESERVED PAGE 1-3 ON-CHIP BLOCK B0 PAGE 4-7 ON-CHIP BLOCK B1 PAGE 8-11 ON-CHIP BLOCK B3 PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) Figure 1A. Memory Maps POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 memory control (continued) MEMORY MAPS AFTER CONF 1 1 MP/MC = 1 PROGRAM 0 (0000h) 31 (001Fh) 32 (0020h) INTERRUPTS AND RESERVED (EXTERNAL) 5 (0005h) 6 (0006h) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) EXTERNAL 511 (01FFh) 512 (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) I/O DATA 0 (0000h) 1023 (03FFh) 1024 (0400h) ON-CHIP BLOCK B0 1535 (05FFh) 1536 (0600h) EXTERNAL 65023 (FDFFh) 65024 (FE00h) 2047 (07FFh) 2048 (0800h) EXTERNAL 65535 (FFFFh) 0 ON-CHIP MMRs EXTERNAL 15 RESERVED PAGE 0 ON-CHIP BLOCK B2 RESERVED PAGE 1-3 DOES NOT EXIST PAGE 4-7 ON-CHIP BLOCK B1 PAGE 8-11 ON-CHIP BLOCK B3 PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) 2 MP/MC = 0 255 (00FFh) 256 (0100h) INTERRUPTS AND RESERVED BOOTLOAD ROM RESERVED 4095 (0FFFh) 4096 (1000h) 0 (0000h) 5 (0005h) 6 (0006h) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) EXTERNAL 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) ON-CHIP BLOCK B0 EXTERNAL 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) EXTERNAL EXTERNAL 15 RESERVED PAGE 0 ON-CHIP BLOCK B2 RESERVED PAGE 1-3 DOES NOT EXIST PAGE 4-7 ON-CHIP BLOCK B1 PAGE 8-11 ON-CHIP BLOCK B3 PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) POST OFFICE BOX 1443 0 ON-CHIP MMRs Figure 1B. Memory Maps 8 I/O DATA PROGRAM 0 (0000h) • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 memory control (continued) MEMORY MAPS AFTER CONF 2 1 MP/MC = 1 PROGRAM 0 (0000h) 31 (001Fh) 32 (0020h) 0 (0000h) INTERRUPTS AND RESERVED (EXTERNAL) 5 (0005h) 6 (0006h) 95 (005Fh) 96 (0060h) EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) ON-CHIP BLOCK B0 ON-CHIP BLOCK B1 EXTERNAL 65535 (FFFFh) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 0 ON-CHIP MMRs EXTERNAL 15 RESERVED PAGE 0 ON-CHIP BLOCK B2 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 63999 (F9FFh) 64000 (FA00h) I/O DATA RESERVED PAGE 1-3 DOES NOT EXIST PAGE 4-7 DOES NOT EXIST PAGE 8-11 ON-CHIP BLOCK B3 PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) 2 MP/MC = 0 PROGRAM 0 (0000h) 255 (00FFh) 256 (0100h) INTERRUPTS AND RESERVED BOOTLOAD ROM RESERVED 4095 (0FFFh) 4096 (1000h) DATA 0 (0000h) 5 (0005h) 6 (0006h) I/O 0 ON-CHIP MMRs EXTERNAL 15 RESERVED 95 (005Fh) 96 (0060h) PAGE 0 ON-CHIP BLOCK B2 EXTERNAL 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 1023 (03FFh) 1024 (0400h) ON-CHIP BLOCK B0 ON-CHIP BLOCK B1 EXTERNAL 65535 (FFFFh) 1535 (05FFh) 1536 (0600h) RESERVED PAGE 1-3 DOES NOT EXIST PAGE 4-7 DOES NOT EXIST PAGE 8-11 ON-CHIP BLOCK B3 PAGE 12-15 EXTERNAL PAGE 16-511 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) Figure 1C. Memory Maps POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 memory control (continued) MEMORY MAPS AFTER CONF 3 1 MP/MC = 1 PROGRAM 0 (0000h) 31 (001Fh) 32 (0020h) 0 (0000h) INTERRUPTS AND RESERVED (EXTERNAL) 5 (0005h) 6 (0006h) 95 (005Fh) 96 (0060h) 511 (01FFh) 512 (0200h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 1023 (03FFh) 1024 (0400h) ON-CHIP BLOCK B0 1535 (05FFh) 1536 (0600h) ON-CHIP BLOCK B1 2047 (07FFh) 2048 (0800h) ON-CHIP BLOCK B3 65535 (FFFFh) 0 ON-CHIP MMRs EXTERNAL 15 RESERVED PAGE 0 ON-CHIP BLOCK B2 127 (007Fh) 128 (0080h) EXTERNAL 63999 (F9FFh) 64000 (FA00h) I/O DATA RESERVED PAGE 1-3 DOES NOT EXIST PAGE 4-7 DOES NOT EXIST PAGE 8-11 DOES NOT EXIST PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) 2 MP/MC = 0 PROGRAM 0 (0000h) 255 (00FFh) 256 (0100h) DATA INTERRUPTS AND RESERVED BOOTLOAD ROM RESERVED 4095 (0FFFh) 4096 (1000h) 0 (0000h) 5 (0005h) 6 (0006h) I/O 0 ON-CHIP MMRs EXTERNAL 15 RESERVED 95 (005Fh) 96 (0060h) PAGE 0 ON-CHIP BLOCK B2 EXTERNAL 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh) ON-CHIP BLOCK B0 ON-CHIP BLOCK B1 ON-CHIP BLOCK B3 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) RESERVED PAGE 1-3 DOES NOT EXIST PAGE 4-7 DOES NOT EXIST PAGE 8-11 DOES NOT EXIST PAGE 12-15 EXTERNAL PAGE 16-511 65535 (FFFFh) Figure 1D. Memory Maps 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 interrupts and subroutines The SMJ320C26 has three external maskable user interrupts INT2–INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on two-words boundaries so that branch instructions can be accommodated in those locations if desired. A built in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to instructions that are repeated or become multicycle due to the READY signal. external interface The SMJ320C26 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor’s external address and data busses in the same manner as memory-mapped devices. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are made with slower devices, the SMJ320C26 processor waits until the other device completes its function and signals the processor via the READY line, the SMJ320C26 then continues execution. A serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial systems. The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware. The serial port may also be used for intercommunication between processors in multiprocessing applications. The serial port has two memory mapped registers; the data transmit register (DXR) and the data receive register (DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same manner as any other data memory location. Each register has an external clock, a framing signal, and associated shift registers. One method of multiprocessing may be implemented by programming one device to transmit while the others are in the receive mode. multiprocessing The flexibility of the SMJ320C26 allows configurations to satisfy a wide range of system requirements. The SMJ320C26 can be used as follows: D D D D A standalone processor. A multiprocessor with devices in parallel. A multiprocessor with global memory space. A peripheral processor interfaced via processor controlled signals to another device. For multiprocessing applications, the SMJ320C26 has the capability of allocating global data memory space and communicating with that space via the BR (bus request) and READY control signals. Global memory is data memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory mapped GREG (global memory allocation register) specifies part of the SMJ320C26’s data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses a location within that space, BR is asserted to request control of the data bus. The length of the memory cycle is controlled by the READY line. The SMJ320C26 supports DMA (direct memory access) to its external program/data memory using the HOLD and HOLDA signals. Another processor can take complete control of the SMJ320C26’s external memory by asserting HOLD low. This causes the SMJ320C26 to place its address, data, and control lines in a high impedance state, and assert HOLDA. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 addressing modes The SMJ320C26 instruction set provides three memory addressing modes; direct, indirect, and immediate addressing. Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate addressing, the data is embedded in the instruction word(s). In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words. Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0 through AR7 respectively. There are seven types of indirect addressing: auto increment, auto decrement, post indexing by either adding or subtracting the contents of AR0, single indirect addressing with no increment or decrement and bit reversal addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, followed by an ARP update. repeat feature A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table read/writes, allows a single instruction to be executed up to 256 times. The repeat counter (RPTC) is loaded with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this operand is one less than the number of times that the next instruction is executed. Those instructions that are normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle instructions. instruction set The SMJ320C26 microprocessor implements a comprehensive instruction set that supports both numeric intensive signal processing operations as well as general purpose applications, such as multiprocessing and high speed control. For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary depending upon whether the next data operand fetch is from internal or external program memory. Highest throughput is achieved by maintaining data memory on-chip and using either internal or fast program memory. Table 1 lists the symbols and abbreviations used in Table 2, the instruction set summary. Table 2 consists primarily of single-cycle, single-word instructions. Infrequently used branch, I-O, and CALL instructions are multicycle. The instruction set summary is arranged according to function and alphabetized within each functional grouping. The symbol (‡) indicates instructions that are not included in the SMJ320C25 instruction set. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 instruction set (continued) Table 1. Instruction Symbols SYMBOL MEANING B 4-bit field specifying a bit code CM 2-bit field specifying compare mode D Data memory address field FO Format status bit M Addressing mode bit K Immediate operand field PA Port address (PA0 through PA 15 are predefined assembler symbols equal to 0 through 15 respectively). PM 2-bit field specifying P register output shift code R 3-bit operand field specifying auxiliary register S 4-bit left-shift code CNF Internal RAM configuration bits X 3-bit accumulator left-shift field POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 instruction set (continued) Table 2. Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC INSTRUCTION BIT CODE NO. DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 ABS Absolute value of accumulator 1 1 1 0 0 ADD Add to accumulator with shift 1 0 0 0 0 ADDC Add to accumulator with carry 1 0 1 0 0 0 0 1 ADDH Add to high accumulator 1 0 1 0 0 1 0 0 ADDK Add to accumulator short immediate 1 1 1 0 0 1 1 0 0 ADDS Add to low accumulator with sign extension suppressed 1 0 1 0 0 1 0 0 1 M ADDT† Add to accumulator with shift specified by T register 1 0 1 0 0 1 0 1 0 M ADLK† Add to accumulator long immediate with shift 2 1 1 0 1 0 0 AND AND with accumulator 1 0 1 0 0 1 0 M ANDK† AND immediate with accumulator with shift 2 1 1 0 1 CMPL† Complement accumulator 1 1 1 0 0 1 0 LAC Load accumulator with shift 1 0 0 1 0 LACK Load accumulator immediate short 1 1 1 0 1 0 LACT† Load accumulator with shift specified by T register 1 0 1 1 1 LALK† Load accumulator long immediate with shift 2 1 1 NEG† Negate accumulator 1 1 NORM† Normalize contents of accumulator 1 OR OR with accumulator 1 ORK† OR immediate with accumulator with shift ROL Rotate accumulator left ROR SACH S 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 2 1 1 0 1 1 1 1 0 0 1 1 Rotate accumulator right 1 1 1 0 0 1 1 Store high accumulator with shift 1 0 1 1 0 1 SACL Store low accumulator with shift 1 0 1 1 0 0 SBLK† Subtract from accumulator long immediate with shift 2 1 1 0 1 SFL† Shift accumulator left 1 1 1 0 0 1 1 SFR† Shift accumulator right 1 1 1 0 0 1 1 SUB Subtract from accumulator with shift 1 0 0 0 1 SUBB Subtract from accumulator with borrow 1 0 1 0 0 1 1 1 SUBC Conditional subtract 1 0 1 0 0 0 1 1 SUBH Subtract from high accumulator 1 0 1 0 0 0 1 SUBK Subtract from accumulator short immediate 1 1 1 0 0 1 SUBS Subtract from low accumulator with sign extension suppressed 1 0 1 0 0 0 SUBT† Subtract from accumulator with shift specified by T register 1 0 1 0 0 XOR Exclusive-OR with accumulator 1 0 1 0 0 XORK† Exclusive-OR immediate with accumulator with shift 2 1 1 0 1 ZAC Zero accumulator 1 1 1 0 0 1 0 1 ZALH Zero low accumulator and load high accumulator 1 0 1 0 0 0 0 ZALR Zero low accumulator and load high accumulator with rounding 1 0 1 1 1 1 0 ZALS Zero accumulator and load low accumulator with sign extension suppressed 1 0 1 0 0 0 0 † These instructions are not included in the SMJ32010 instruction set. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 M D 1 M D 0 M D S S S D D D 0 0 0 0 D 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 D M S K D M 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 M X X X 0 0 1 0 0 1 M 1 0 1 0 S X D 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 D M X D M S 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 M D 1 M D 1 M 0 0 M D D 1 0 1 1 0 1 M D 0 1 1 0 M D 1 1 0 0 M S S K D 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 M D 1 1 M D 0 1 M D SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 instruction set (continued) Table 2. Instruction Set Summary (continued) AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS MNEMONIC INSTRUCTION BIT CODE NO. DESCRIPTION WORDS 15 14 13 12 11 10 9 8 ADRK Add to auxiliary register short immediate 1 0 1 1 1 1 1 1 0 7 CMPR† Compare auxiliary register with auxiliary register AR0 1 1 1 0 0 1 1 1 0 LAR Load auxiliary register 1 0 0 1 1 0 LARK Load auxiliary register short immediate 1 1 1 0 0 0 LARP Load auxiliary register pointer 1 0 1 0 1 0 1 0 1 M LDP Load data memory page pointer 1 0 1 0 1 0 0 1 0 M LDPK Load data memory page pointer immediate 1 1 1 0 0 1 0 LRLK† Load auxiliary register long immediate 2 1 1 0 1 0 MAR Modify auxiliary register 1 0 1 0 1 0 SAR Store auxiliary register 1 0 1 1 1 0 SBRK Subtract from auxiliary register short immediate 1 0 1 1 1 1 6 5 4 0 1 0 1 M R 0 0 0 0 1 0 0 0 CM 0 R 1 D 0 0 1 R 1 1 K R 0 2 K R 1 3 D 0 0 0 0 0 DP M D D M 1 K T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS MNEMONIC INSTRUCTION BIT CODE NO. DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 APAC Add P register to accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 LPH† Load high P register 1 0 1 0 1 0 0 1 1 M LT Load T register 1 0 0 1 1 1 1 0 0 M LTA Load T register and accumulator previous product 1 0 0 1 1 1 1 0 1 M LTD Load T register, accumulate previous product, and move data 1 0 0 1 1 1 1 1 1 M LTP† Load T register and store P register in accumulator 1 0 0 1 1 1 1 1 0 M LTS† Load T register and subtract previous product 1 0 1 0 1 1 0 1 1 M MAC† Multiply and accumulate 2 0 1 0 1 1 1 0 1 M MACD† Multiply and accumulate with data move 2 0 1 0 1 1 1 0 0 M MPY Multiply (with T register, store product in P register) 1 0 0 1 1 1 0 0 0 M MPYA Multiply and accumulate previous product 1 0 0 1 1 1 0 1 0 M MPYK Multiply immediate 1 1 0 1 MPYS Multiply and subtract previous product 1 0 0 1 1 1 0 1 1 M MPYU Multiply unsigned 1 1 1 0 0 1 1 1 1 M PAC Load accumulator with P register 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 0 SPAC Subtract P register from accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 SPH Store high P register 1 0 1 1 1 1 1 0 1 M SPL Store low P register 1 0 1 1 1 1 1 0 0 M SPM† Set P register output shift mode 1 1 1 0 0 1 1 1 0 0 SQRA† Square and accumulate 1 0 0 1 1 1 0 0 1 M D SQRS† Square and subtract previous product 1 0 1 0 1 1 0 1 0 M D D D D D D D D D D K D D K D D D D 0 0 0 1 0 PM † These instructions are not included in the SMJ32010 instruction set. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 instruction set (continued) Table 2. Instruction Set Summary (continued) BRANCH/CALL INSTRUCTIONS MNEMONIC INSTRUCTION BIT CODE NO. DESCRITPION WORDS 15 14 13 12 11 10 9 8 7 B Branch unconditionally 2 1 1 1 1 1 1 1 1 1 6 5 4 3 BACC† Branch to address specified by accumulator 1 1 1 0 0 1 1 1 0 0 BANZ Branch on auxiliary register not zero 2 1 1 1 1 1 0 1 1 1 D BBNZ† Branch if TC bit ≠ 0 2 1 1 1 1 1 0 0 1 1 D BBZ† Branch if TC bit = 0 2 1 1 1 1 1 0 0 0 1 D BC Branch on carry 2 0 1 0 1 1 1 1 0 1 D BGEZ Branch if accumulator ≥ 0 2 1 1 1 1 0 1 0 0 1 D BGZ Branch if accumulator > 0 2 1 1 1 1 0 0 0 1 1 D BIOZ Branch on I/O status = 0 2 1 1 1 1 1 0 1 0 1 D BLEZ Branch if accumulator ≤ 0 2 1 1 1 1 0 0 1 0 1 D BLZ Branch if accumulator < 0 2 1 1 1 1 0 0 1 1 1 D BNC Branch on no carry 2 0 1 0 1 1 1 1 1 1 D BNV† Branch if no overflow 2 1 1 1 1 0 1 1 1 1 D BNZ Branch if accumulator ≠ 0 2 1 1 1 1 0 1 0 1 1 D BV Branch on overflow 2 1 1 1 1 0 0 0 0 1 D BZ Branch if accumulator = 0 2 1 1 1 1 0 1 1 0 1 CALA Call subroutine indirect 1 1 1 0 0 1 1 1 0 0 CALL Call subroutine 2 1 1 1 1 1 1 1 0 1 RET Return from subroutine 1 1 1 0 0 1 1 1 0 0 2 1 0 1 0 1 1 0 0 1 1 0 2 1 0 1 1 D 0 1 0 0 D 0 1 0 0 D 0 1 0 0 5 4 3 I/O AND DATA MEMORY OPERATIONS MNEMONIC INSTRUCTION BIT CODE NO. DESCRITPION WORDS 15 14 13 12 11 10 9 8 7 BLKD Block move from data memory to data memory 2 1 1 1 1 1 1 0 1 M D BLKP† Block move from program memory to data memory 2 1 1 1 1 1 1 0 0 M D DMOV Data move in data memory 1 0 1 0 1 0 1 1 0 M FORT† Format serial port registers 1 1 1 0 0 1 1 1 0 0 IN Input data from port 1 1 0 0 0 OUT Output data to port 1 1 1 1 0 RFSM Reset serial port frame synchronization mode 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 RTXM† Reset serial port transmit mode 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 RXF† Reset external flag 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 SFSM Set serial port frame synchronization mode 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 1 STXM† Set serial port transmit mode 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 SXF† Set external flag 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 TBLR Table read 1 0 1 0 1 1 0 0 0 M D TBLW Table write 1 0 1 0 1 1 0 0 1 M D † These instructions are not included in the SMJ32010 instruction set. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 6 D 0 FO 0 0 1 D M PA M PA D SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 instruction set (continued) Table 2. Instruction Set Summary (concluded) CONTROL INSTRUCTIONS MNEMONIC INSTRUCTION BIT CODE NO. DESCRIPTION WORDS 15 14 13 12 1 1 0 0 1 11 10 9 8 7 6 5 4 3 2 1 0 BIT† Test bit BITT† Test bit specified by T register 1 0 1 0 1 0 1 1 1 M CONF‡ Configure RAM blocks as Data or program 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 DINT Disable interrupt 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 EINT Enable interrupt 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 IDLE† Idle until interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 LST Load status register ST0 1 0 1 0 1 0 0 0 0 M LST1† Load status register ST1 1 0 1 0 1 0 0 0 1 M NOP No operation 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 POP Pop top of stack to low accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 POPD† Pop top of stack to data memory 1 0 1 1 1 1 0 1 0 M PSHD† Push data memory value onto stack 1 0 1 0 1 0 1 0 0 M PUSH Push low accumulator onto stack 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 RC Reset carry bit 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 RHM Reset hold mode 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 ROVM Reset overflow mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 RPT† Repeat instruction as specified by data memory value 1 0 1 0 0 1 0 1 1 M RPTK† Repeat instruction as specified by immediate value 1 1 1 0 0 1 0 1 1 RSXM† Reset sign-extension mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 0 RTC Reset test/control flag 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 SC Set carry bit 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 SHM Set hold mode 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 SOVM Set overflow mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 SST Store status register ST0 1 0 1 1 1 1 0 0 0 M SST1† Store status register ST1 1 0 1 1 1 1 0 0 1 M SSXM† Set sign-extension mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 STC Set test/control flag 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 TRAP† Software interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 M D D D CNF D D D D D K D D † These instructions are not included in the SMJ32010 instruction set. ‡ This instruction replaces CNFD and CNFP in the SMJ320C25 instruction set. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 development support Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development support products to assist the user in all aspects of TMS320 second-generation-based design and development. These products range from development and application software to complete hardware development and evaluation systems. Table 3 lists the development support products for the second-generation TMS320 devices. System development may begin with the use of the simulator, Software Development System (SWDS), or emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation, from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with hardware and software breakpoint trace and timing capabilities (XDS). Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and simulator for software development, the XDS for hardware development, and the Software Development System for both software development and limited hardware development. Many third-party vendors offer additional development support for the second-generation TMS320s, including assembler/linkers, simulators, high-level languages, applications software, algorithm development tools, applications boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for further information about TMS320 development support products offered by both Texas Instruments and its third-party suppliers. Additional support for the TMS320 products consists of an extensive library of product and applications documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs). These workshops provide insight into the architecture and the instruction set of the second-generation TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274–2320. Or, keep informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service (BBS) at (713) 274–2323. The BBS serves 2400-, 1200-, and 300-bps modems. Also, TMS320 application source code may be downloaded from the BBS. Table 3 gives a complete list of SMJ320C26 software and hardware development tools. 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 development support (continued) Table 3. Software and Hardware Support MACRO ASSEMBLER/LINKER HOST COMPUTER OPERATING SYSTEMS PART NUMBER VMS TMDS3242250-08 MS/PS DOS TMDS3242850-02 ULTRIX TMDS3242260-08 UNIX TMDS3242550-08 DEC VAX IBM PC VAX SUN 3 C COMPILER AND MACRO ASSEMBLER/LINKER HOST COMPUTER OPERATING SYSTEMS PART NUMBER VMS TMDS3242255-08 MS/PC DOS TMDS3242855-02 ULTRIX TMDS3242265-08 SUN 3 UNIX TMDS3242555-08 HOST COMPUTER OPERATING SYSTEMS PART NUMBER VMS TMDS3242251-08 MS/PC DOS TMDS3242851-02 DEC VAX IBM PC VAX SIMULATOR DEC VAX IBM PC EMULATOR MODEL POWER SUPPLY XDS/22 INCLUDED PART NUMBER TMDS3262292 SOFTWARE DEVELOPMENT SYSTEM ON PC HOST COMPUTER OPERATING SYSTEMS IBM PC MS/PC DOS IBM PC † Includes assembler/linker MS/PC DOS POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PART NUMBER TMDX3268828 TMDX3268821† 19 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VCC‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to VSS. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. recommended operating conditions VCC VSS Supply voltage NOM MAX 4.5 5 5.5 Supply voltage UNIT V 0 D15–D0, FSX VIH MIN High-level High level in input ut voltage V 2.2 CLKIN, CLKR, CLKX 3.50 All others 3.00 V D15–D0, FSX, CLKIN, CLKR, CLKX 0.8 All others 0.7 µA A VIL Lo le el inp Low-level inputt voltage oltage IOH IOL High-level output current 300 µA Low-level output current 2 mA TA TC Minimum operating free-air temperature °C –55 Maximum operating case temperature °C 125 electrical characteristics over specified free-air temperature range (unless otherwise noted) PARAMETER VOH VOL High-level output voltage IOZ II High-impedance-state output leakage current ICC Supply current CI Input capacitance Low-level output voltage Input current TEST CONDITIONS MIN TYP§ VCC = MIN, IOH = MAX VCC = MIN, IOL = MAX 2.4 3 0.3 VCC = MAX VI = VSS to VCC Normal Idle/HOLD POST OFFICE BOX 1443 UNIT V 0.6 V ± 20 µA ± 10 µA 185 VCC = MAX MAX, fx = MAX CO Output capacitance § All typical values are at VCC = 5 V, TA = 25°C. 20 MAX • HOUSTON, TEXAS 77251–1443 100 mA 15 pF 15 pF SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 CLOCK CHARACTERISTICS AND TIMING The SMJ320C26 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental or overtone mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit (see the application report, Hardware Interfacing to the TMS320C25). PARAMETER TEST CONDITIONS MIN TA = –55°C MIN TC = 125°C MAX 6.7 fx Input clock frequency† C1, C2 † This parameter is not production tested. X1 TYP MAX UNIT 40.0 MHz 10 pF X2/CLKIN CRYSTAL C1 C2 Figure 1. Internal Clock Option external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions (see Note 1) PARAMETER MIN TYP† MAX UNIT 100 600 ns 5 32 ns CLKOUT1/CLKOUT2/STRB fall time 5 ns CLKOUT1/CLKOUT2/STRB rise time 5 ns 2Q 2Q+8 ns 2Q 2Q+8 ns Q Q+6 ns tc(C) td(CIH-C) CLKOUT1/CLKOUT2 cycle time tf(C) tr(C) tw(CL) tw(CH) CLKOUT1/CLKOUT2 low pulse duration 2Q–8 CLKOUT1/CLKOUT2 high pulse duration 2Q–8 Q–6 CLKIN high to CLKOUT1/CLKOUT2/STRB high/low td(C1-C2) CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc. † This parameter is not production tested. NOTE 1: Q = 1/4tc(C) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 timing requirements over recommended operating conditions (see Note 1) MIN MAX UNIT tc(CI) tw(CIL) CLKIN cycle time 25 150 ns CLKIN low pulse duration, tc(C) = 25 ns (see Note 2) 10 15 ns tw(CIH) tsu(S) CLKIN high pulse duration, tc(CI) = 25 ns (see Note 2) 10 15 ns 5 Q–5 ns SYNC setup time before CLKIN low th(S) SYNC hold time from CLKIN low 8 NOTES: 1. Q = 1/4tc(C) 2. CLKIN duty cycle [tr(CI) + tw(CIH)]/tc(CI) must be within 40-60%. CLKIN rise and fall times must be less than 5 ns. IOH/IOL From Output Under Test Test Point CL = 80 pF Figure 2. Test Load Circuit 90% VIH (MIN) 10% VIL (MAX) 0 (a) Input 2.4 V VOH (MIN) 2.2 V 0.8 V 0 VOL (MAX) 0.6 V (b) Outputs Figure 3. Voltage Reference Levels 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 1) PARAMETER td(C1-S) td(C2-S) STRB from CLKOUT1 (if STRB is present) tsu(A) th(A) Address setup time before STRB low (see Note 3) tw(SL) tw(SH) STRB low pulse duration (no wait states, see Note 4) tsu(D)W th(D)W Data write setup time before STRB high (no wait states) ten(D) tdis(D) Data bus starts being driven after STRB low (write cycle) CLKOUT2 to STRB (if STRB is present) MIN TYP MAX UNIT Q–6 Q Q+6 ns –6 0 6 ns Q–12 Address hold time after STRB high (see Note 3) ns Q–8 ns 2Q–5 2Q STRB high pulse duration (between consecutive cycles, see Note 4) Data write hold time from STRB high 2Q ns ns 2Q–20 ns Q–10 0† Q ns ns Data bus three-state after STRB high (write cycle) – 10† td(MSC) MSC valid from CLKOUT1 † This parameter is not production tested. 2Q+5 Q Q+15† ns 0 10 ns timing requirements over recommended operating conditions (see Note 1) MIN ta(A) tsu(D)R Read data access time from address time (read cycle) (see Notes 3 and 5) th(D)R td(SL-R) Data read hold time from STRB high td(C2H-R) th(SL-R) READY valid after CLKOUT2 high th(C2H-R) td(M-R) READY hold after CLKOUT2 high MAX 3Q–40 Data read setup time before STRB high 23 ns READY valid after STRB low (no wait states) Q–22 Q – 22† Q+3 Q + 3† READY valid after MSC valid ns ns ns ns 2Q –25† 0† th(M-R) READY hold time after MSC valid † This parameter is not production tested. ns ns 0 READY hold time after STRB low (no wait states) UNIT ns ns RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Note 1) PARAMETER td(RS) td(IACK) CLKOUT1 to IACK valid td(XF) XF valid before falling edge of STRB MIN TYP CLKOUT1 low to reset state entered – 8† POST OFFICE BOX 1443 Q–12 • HOUSTON, TEXAS 77251–1443 0 MAX 22† 8 UNIT ns ns ns 23 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 timing requirements over recommended operating conditions (see Note 1) MIN tsu(IN) th(IN) INT/BIO/RS setup before CLKOUT1 high (see Note 6) tw(IN) tw(RS) NT/BIO low pulse duration INT/BIO/RS hold after CLKOUT1 high (see Note 6) RS low pulse duration MAX UNIT 32 ns 0 ns tc(C) 3tc(C) ns ns NOTES: 1. Q = 1/4tc(C) 3. A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address.” 4. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states. 5. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R. 6. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagram will occur. INT/BIO fall time must be less than 8 ns. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 HOLD TIMING switching characteristics over recommended operating conditions (see Note 1) PARAMETER MIN –1† td(C1L-AL) tdis(AL-A) HOLDA low after CLKOUT1 low tdis(C1L-A) td(HH-AH) Address three-state after CLKOUT1 low (HOLD mode) (see Note 7) HOLDA low to address three-state TYP MAX 10 0 HOLD high to HOLDA high ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode) (see Note 7) † This parameter is not production tested. UNIT ns ns 20† ns 25 8† ns ns timing requirements over recommended operating conditions (see Note 1) MIN td(C2H-H) HOLD valid after CLKOUT2 high NOTES: 1. Q = 1/4tc(C) 7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.” POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MAX UNIT Q–24 ns 25 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 1) PARAMETER MIN MAX UNIT td(CH-DX) td(FL-DX) DX valid after CLKX rising edge (see Note 8) 80 ns DX valid after FSX falling edge (TXM = 0) (see Note 8) 45 ns td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 45 ns timing requirements over recommended operating conditions (see Note 1) MIN MAX UNIT kHz fsx tc(SCK) Serial port frequency 1.25 5,000 Serial port clock (CLKX/CLKR) cycle time 200 800,000 tw(SCK) tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 9) 80 ns Serial port clock (CLKX/CLKR) high pulse duration (see Note 9) 80 ns tsu(FS) th(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 18 ns FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns tsu(DR) th(DR) DR setup time before CLKR falling edge 10 ns DR hold time after CLKR falling edge 20 ns ns NOTES: 1. Q = 1/4tc(C) 8. The last occurrence of FSX falling and CLKX rising. 9. The duty cycle of the serial port clock must be within 40–60%. Serial port clock (CLKX/CLKR) rise and fall times must be less than 25 ns. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.2 volts unless otherwise noted. tc(CI) tf(CI) tr(CI) X/2CLKIN th(S) tsu(S) tsu(S) tw(CIL) tw(CIH) SYNC td(CIH-C) tc(C) td(CIH-C) tw(CL) CLKOUT1 tw(CH) td(CIH-C) tr(C) tf(C) STRB tc(C) td(CIH-C) tw(CL) CLKOUT2 td(C1-C2) td(C1-C2) td(C1-C2) tw(CH) td(C1-C2) tf(C) tr(C) Figure 4. Clock Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION td(C1-S) CLKOUT1 td(C1-S) CLKOUT2 td(C2-S) td(C2-S) STRB A15–A0, BR, PS, DS, OR IS tw(SL) tsu(A) tw(SH) th(A) VALID ta(A) R/W td(SL-R) tsu(D)R READY th(D)R th(SL-R) D15–D0 DATA IN Figure 5. Memory Read Timing 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB tsu(A) A15–A0, BR, PS, DS, OR IS th(A) VALID R/W READY th(D)W tsu(D)W DATA OUT D15–D0 ten(D) tdis(D) Figure 6. Memory Write Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB A15–A0, BR PS, DS, R/W, OR IS VALID th(C2H-R) td(C2H-R) td(C2H-R) th(C2H-R) READY D15–D0, (FOR READ OPERATION) td(M-R) th(M-R) td(M-R) th(M-R) DATA IN D15–D0, (FOR WRITE OPERATION) MSC td(MSC) td(MSC) Figure 7. One Wait-State Memory Access Timing 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION CLKOUT1 tsu(IN) tsu(IN) th(IN) td(RS) RS tw(RS) A15–A0 FETCH LOCATION 0 D15–D0 VALID PS BEGIN PROGRAM EXECUTION STRB CONTROL SIGNALS† IACK SERIAL PORT CONTROLS‡ † Control signals are DS, IS, R/W, and XF. ‡ Serial port controls are DX and FSX. Figure 8. Reset Timing CLKOUT1 STRB tsu(IN) tw(N) th(IN) INT2–INT0 tf(IN) A15–A0 FETCH N FETCH N + 1 td(IACK) FETCH N + 2 FETCH 1 td(IACK) IACK Figure 9. Interrupt Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION CLKOUT1 STRB FETCH BIOZ FETCH BRANCH ADDRESS FETCH NEXT INSTRUCTION A15–A0 PC = N PC = N + 1 tsu(IN) BIO PC = N + 2 th(IN) PC = N + 3 OR BRANCH ADDRESS VALID Figure 10. BIO Timing CLKOUT1 STRB td(XF) A15–A0 FETCH SXF/RXF VALID VALID VALID PC = N PC = N + 1 PC = N + 2 PC = N + 3 XF VALID Figure 11. External Flag Timing 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB td(C2H-H) (see note A) HOLD A15–A0 N N+1 PS, DS, OR IS VALID VALID N+2 R/W tdis(C1L-A) D15–D0 IN IN tdis(AL-A) HOLDA td(C1L-AL) FETCH N N+1 – – N– 2 N – 1 N – EXECUTE NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. Figure 12. HOLD Timing (Part A) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 ten(A-C1L) STRB td(C2H-H) (see note A) HOLD PS, DS, OR IS VALID R/W D15–D0 IN td(HH-AH) HOLDA N+2 A15–A0 N+2 – – – N+2 – – – N+1 FETCH EXECUTE NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. Figure 13. HOLD Timing (Part B) 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION tc(SCK) tw(SCK) tr(SCK) CLKR th(FS) th(DR) tf(SCK) tw(SCK) FSR tsu(FS) tsu(DR) N = 8, 16 DR Figure 14. Serial Port Receive Timing tc(SCK) tr(SCK) tw(SCK) CLKX tw(SCK) tf(SCK) th(FS) td(CH-DX) FSX (INPUT, TXM = 0) tsu(FS) td(FL-DX) tsu(FS) td(CH-DX) N=1 DX td(CH-FS) N = 8, 16 td(CH-FS) FSX (OUTPUT, TXM = 1) Figure 15. Serial Port Transmit Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 5962-8861903XA OBSOLETE CPGA GB 68 TBD Call TI Call TI 5962-8861903YA OBSOLETE LCCC FD 68 TBD Call TI Call TI SM320C26BFJM OBSOLETE JLCC FJ 68 TBD Call TI N / A for Pkg Type SM320C26BGBM OBSOLETE CPGA GB 68 TBD Call TI Call TI SMJ320C26BFDM OBSOLETE LCCC FD 68 TBD Call TI Call TI SMJ320C26BGBM OBSOLETE CPGA GB 68 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SMJ320C26B : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2012 • Catalog: TMS320C26B NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 MECHANICAL DATA MCPG023A – OCTOBER 1997 – REVISED DECEMBER 2001 GB (S-CPGA-P68) CERAMIC PIN GRID ARRAY 0.970 (24,63) 0.950 (24,13) 0.536 (13,61) 0.800 (20,32) TYP 0.524 (13,31) J H G F E D C B A1 Corner A 1 2 3 4 5 6 7 8 9 Bottom View 0.088 (2,23) 0.072 (1,83) 0.100 (2,54) 0.194 (4,98) 0.166 (4,16) 0.055 (1,39) 0.045 (1,14) 0.050 (1,27) DIA 4 Places 0.018 (0,46) DIA TYP 4040114-14/D 11/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Index mark may appear on top or bottom depending vendor. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edges of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold plated or solder dipped. G. Falls within MIL STD 1835 CMGA1-PN, CMGA13-PN and JEDEC MO-067 AA, MO-066 AA respectively POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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