MK32VT1672A-8YC (98.07.06) Semiconductor MK32VT1672A-8YC 16,777,216 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK): DESCRIPTION The Oki MK32VT1672A-8YC is a fully decoded, 16,777,216 x 72bit synchronous dynamic random access memory composed of eighteen 64Mb DRAMs (8Mx8) in TSOP packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line Package supports any application where high density and large capacity of storage memory are required, like for example PCs or servers. FEATURES • • • • • • • • • • 16-Meg Word x 72-bit (2Bank 8Byte) organization 168-pin Dual Inline Memory Module All DQ Pins have 10Ω Damping Resister Single 3.3V power supply, ±0.3V tolerance Input :LVTTL compatible Output :LVTTL compatible Refresh : 4,096 cycles/64 ms Programmable data transfer mode • /CAS latency (2, 3) • Burst length (1, 2, 4, 8, Full) • Data scramble (sequential, interleave) /CAS before /RAS auto-refresh, Self-refresh capability Serial Presence Detect (SPD) With EEPROM PRODUCT ORGANIZATION Product Name MK32VT1672A-8YC Operation Frequency (Max.) 125 MHz Access Time (Max.) tAC2 tAC3 10.0ns Note. Specification are subject to change without notice. 6.0ns MK32VT1672A-8YC (98.07.06) BLOCK DIAGRAM CKE1 CKE0 /CS0 DQMB0 /CS2 DQMB2 /CS1 DQ0 DQM /CS CKE DQ0 DQ7 DQ7 DQM /CS CKE DQ0 1 10KΩ /CS3 DQM /CS CKE DQ0 DQ16 DQM /CS CKE DQ0 DQ23 DQ7 DQ7 DQ24 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ31 DQ7 DQ7 DQ48 DQM /CS CKE DQ0 DQM /CS CKE DQ0 8 17 DQ55 DQ7 DQ7 DQ56 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ63 DQ7 6 10 DQ7 15 DQMB3 DQMB1 DQ8 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ15 DQ7 DQ7 DQM /CS CKE DQ0 DQM /CS CKE DQ0 3 12 11 2 7 16 DQMB6 DQMB4 DQ32 DQ39 DQ7 DQ7 DQMB7 DQMB5 DQ40 DQM /CS CKE DQ0 DQ47 DQ7 DQM /CS CKE DQ0 4 13 9 DQ7 DQMB1 DQMB5 CB0 DQM /CS CKE DQ0 CB7 DQ7 Serial PD DQM /CS CKE DQ0 SDA WP 19 SCL 14 5 18 DQ7 A0 A1 A2 DQ7 47KΩ SA0 SA1 SA2 1 10 6 15 2 11 7 16 3 CLK0 /RAS,/CAS,/WE A0-A11,BA0,BA1 12 CLK1 4 13 5 14 1 á 8 CLK2 18 9 3.3pF 3.3pF Vcc 18 Two Decoupling Capacitors per SDRAM Vss 0.1uF 0.33uF Note. The Value of all resistors is 10Ω expect WP and CKE1. MODULE (Front) (Back) 1 85 OUTLINE 10 11 94 95 40 41 124 125 17 CLK3 84 168 MK32VT1672A-8YC (98.07.06) PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Front Pin name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 Vss N.C N.C Vcc /WE DQMB0 DQMB1 /CS0 N.C Vss A0 A2 A4 A6 A8 A10 BA1 Vcc Vcc CLK0 Pin Name Vcc Vss CLK# /CS# CKE# A0-A11 BA0, BA1 /RAS /CAS Back side Pin No. Pin name 85 Vss 86 DQ32 87 DQ33 88 DQ34 89 DQ35 90 Vcc 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 96 Vss 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 102 Vcc 103 DQ46 104 DQ47 105 CB4 106 CB5 107 Vss 108 N.C 109 N.C 110 Vcc 111 /CAS 112 DQMB4 113 DQMB5 114 /CS1 115 /RAS 116 Vss 117 A1 118 A3 119 A5 120 A7 121 A9 122 BA0 123 A11 124 Vcc 125 CLK1 126 N.C Function Power Supply (3.3V) Ground (0V) System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Front side Pin No. Pin name 43 Vss 44 N.C 45 /CS2 46 DQMB2 47 DQMB3 48 N.C 49 Vcc 50 N.C 51 N.C 52 CB2 53 CB3 54 Vss 55 DQ16 56 DQ17 57 DQ18 58 DQ19 59 Vcc 60 DQ20 61 N.C 62 N.C 63 CKE1 64 Vss 65 DQ21 66 DQ22 67 DQ23 68 Vss 69 DQ24 70 DQ25 71 DQ26 72 DQ27 73 Vcc 74 DQ28 75 DQ29 76 DQ30 77 DQ31 78 Vss 79 CLK2 80 N.C 81 WP 82 SDA 83 SCL 84 Vcc Pin Name /WE DQMB# DQ# , CB# WP SDA SCL SA# N.C Back side Pin No. Pin name 127 Vss 128 CKE0 129 /CS3 130 DQMB6 131 DQMB7 132 N.C 133 Vcc 134 N.C 135 N.C 136 CB6 137 CB7 138 Vss 139 DQ48 140 DQ49 141 DQ50 142 DQ51 143 Vcc 144 DQ52 145 N.C 146 N.C 147 N.C 148 Vss 149 DQ53 150 DQ54 151 DQ55 152 Vss 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 Vcc 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 Vss 163 CLK3 164 N.C 165 SA0 166 SA1 167 SA2 168 Vcc Function Write Enable Data Input / Output Mask Data Input / Output Write Protect Data I/O for SPD CLK input for SPD Socket Position Address for SPD No Connection MK32VT1672A-8YC (98.07.06) SERIAL PRESENCE DETECT Byte No. SPD Hex Value 0 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 08 04 0C 09 02 48 00 01 80 60 02 80 08 08 01 8F 04 06 01 01 00 0E C0 A0 00 00 1E 10 14 30 10 20 10 20 10 00-00 12 5C 41,45,20,20,20,20,20,20 01 / 06 4D,4B,33,32,56,54,31,36,37, 32,41,2D,38,59,43,20,20,20 20, 20 91, 92 00-00 93-125 64 126 F5 127 FF-FF 128-255 73-90 Remark Notes Defines the number of bytes written into SPD memory Total number of bytes of SPD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width of this assembly ... Data width continuation Voltage interface level Cycle time (CL=3) Access time from CLK (CL=3) DIMM configuration type Refresh rate / type Primary SDRAM width Error checking SDRAM width Minimum CLK delay Burst lengths supported Number of banks on each SDRAM /CAS latency /CS latency /WE latency SDRAM module attributes SDRAM device attributes : General Cycle time (CL=2) Access time from CLK (CL=2) Cycle time (CL=1) Access time from CLK (CL=1) Minimum ROW pulse width /RAS to /RAS bank delay /RAS to /CAS delay Minimum /RAS precharge time Density of each bank on module 128 byte Manufacturer’s part number MK32VT1672A-8YC 256 byte SDRAM 12 rows 9 columns 2 bank 72 bits 0 LVTTL CL=3 tCC=8ns CL=3 tAC3=6ns ECC Normal / Self x8 x8 tCCD: 1 CLK 1, 2, 4, 8, F 4 banks 2, 3 0 0 CL=2 tCC2=12ns CL=2 tAC2=10ns Not support Not support tRP=30ns tRRD=16ns tRCD=20ns tRAS=48ns 64MB Command and address signal input setup time 2ns Command and address signal input hold time 1ns Data signal input setup time 2ns Data signal input hold time 1ns R.F.U SPD data revision code 1.2 Checksum for byte 0-62 Manufacturer’s JEDEC ID code Manufacturing location Revision code R.F.U Intel specification frequency Intel specification /CAS latency Unused storage locations 100MHz CLK0-3, CL=3 MK32VT1672A-8YC (98.07.06) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 to Vcc + 0.5 V Vcc supply voltage Vcc, VccQ -0.5 to 4.6 V Storage temperature Tstg - 55 to 125 °C Power dissipation PD* 18 W Short circuit current IOS 50 mA Topr 0 to 70 °C Operating temperature *: Ta=25°C Recommended Operating Conditions Parameter Power supply voltage Input high voltage Input low voltage Symbol Vcc, VccQ VIH VIL Min. 3.0 2.0 -0.3 (Voltages referenced to Vss = 0V) Typ. Max. Unit 3.3 - 3.6 Vcc + 0.3 0.8 V V V Capacitance Parameter Input capacitance (A0-A11, BA0, BA1, /RAS, /CAS, /WE) Input capacitance (/CS0, /CS1, /CS2, /CS3) Input capacitance (DQMB0-DQMB7) Input capacitance (CKE0, CKE1) I/O capacitance (DQ0 - DQ63 , CB0 - CB7) Input capacitance (CLK0, CLK1, CLK2, CLK3) (Vcc = 3.3V ± 0.3 V , Ta = 25°C f = 1MHz) Symbol Max. Unit CIN1 104 pF CIN2 34 pF CIN3 22 pF CIN4 58 pF CI/O 25 pF CCLK 50 pF MK32VT1672A-8YC (98.07.06) DC CHARACTERISTICS (Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Stand by) Average Power Supply Current (Clock Suspension) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) Notes: 1. 2. 3. Condition Symbol Module Spec. Unit Note CKE Others Min. Max. VOH VOL ILI ILO - IOH = -2.0mA IOL = 2.0mA 2.4 -180 -20 0.4 180 20 V V uA uA ICC1 CKE ≥ VIH tCC=min. tRC=min. No Burst - 1395 mA 1, 2 ICC2 CKE ≥ VIH tCC=min. - 540 mA 3 ICC3S CKE ≤ VIL tCC=min. - 324 mA 2 ICC3 CKE ≥ VIH, /CS ≥ VIH tCC=min. - 810 mA 3 ICC4 CKE ≥ VIH tCC=min. - 1755 mA 1, 2 ICC5 CKE ≥ VIH tCC=min. tRC=min. - 1935 mA 2 ICC6 CKE ≤ 0.2V tCC=min. - 36 mA ICC7 CKE ≤ VIL tCC=min. - 36 mA - Measured with the output open. Address and data can be changed once or not be changed during one cycle. Address and data can be changed once or not be changed during two cycle. MODE SET ADDRESS KEYS A9 0 1 Write Burst Write Burst Burst Write Single bit Write Note: A6 0 0 0 0 1 1 1 1 /CAS Latency A5 A4 CL 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Burst Type A3 BT 0 Sequential 1 Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 BT=0 0 Reserved 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Full page A7, A8, A10, A11, BA0, BA1 and All should stay "L" during mode set cycle. BT=1 Reserved 2 4 8 Reserved Reserved Reserved Reserved MK32VT1672A-8YC (98.07.06) POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and enter the system clock. 2. After the Vcc voltage has reached the specified level, take a pause of 200µs or more with the input being NOP. 3. Enter the precharge all bank command. 4. Apply CBR auto-refresh eight or more times. 5. Enter the mode register setting command. MK32VT1672A-8YC (98.07.06) AC CHARACTERISTIC Parameter Symbol (Vcc = 3.3V ± 0.3V, Ta = 0 ~ 70°C) NOTE 1, 2 Module Spec. Unit Note Min. Max. Clock Cycle Time CL=3 CL=2 tCC 8 12 - ns ns Access Time from Clock CL=3 CL=2 tAC - 6 ns 3, 4 tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP 10 8 - ns ns ns ns ns ns ns ns ns ns 3, 4 Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock /RAS Cycle Time /RAS Precharge Time 3 3 2 1 3 3 80 30 /RAS Active Time /RAS to /CAS Delay Time tRAS tRCD 48 20 100,000 - ns ns Write Recovery Time /RAS to /RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time tWR tRRD tREF tPDE tT 8 16 - 64 - ns ns ms ns 3 /CAS to /CAS Delay Time (Min) Clock Disable Time from CKE Data Output High Impedance Time from DQMB Data Input Mask Time from DQMB Data Input Time from Write Command Data Output High Inpedance CL=3 Time from Precharge Command CL=2 Active Command Input Time from MODE Register Set Command Input (Min) ICCD ICKE 1 1 ns Cycle Cycle 2 Cycle IDOD IDWD 0 0 3 2 Cycle Cycle Cycle Cycle 2 Cycle Write Command Input Time from Output IOWD 2 Cycle NOTES: 1) 2) 3) 4) 5) tSI+1CLK - IDOZ IROH IMRD 3 AC measurements assume tT=1ns. The reference level for timing of input signals is 1.4V. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF (RLoad is 50ohm). An access time is measured at 1.4V. If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL. 1.4v 50Ω OUTPUT OUTPUT LOAD 50pF . MK32VT1672A-8YC (98.07.06) FUNCTION TRUTH TABLE (Table1) (1/2) Current State Idle Row Active Read Write Read with Auto Precharge Write with Auto Precharge /CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L /RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L /CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L /WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X Action NOP NOP 2 ILLEGAL 2 ILLEGAL Row Active 4 NOP 5 Auto-Refresh or Self-Refresh Mode Register write NOP NOP Read Write 2 ILLEGAL Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop 3 Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 2 ILLEGAL Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop 3 Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 2 ILLEGAL 3 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL MK32VT1672A-8YC (98.07.06) FUNCTION TRUTH TABLE (Table1) (2/2) Current State Precharge Write Recovery Row Active Refresh Auto Resister Access /CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L /RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L /CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X /WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X Action NOP Idle after tRP NOP Idle after tRP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 4 NOP ILLEGAL NOP NOP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Æ Æ Æ Æ ABBREVIATIONS RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No Operation command Notes: 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. MK32VT1672A-8YC (98.07.06) FUNCTION TRUTH TABLE (CKE) (Table2) Current State (n) Self Refresh Power Down All Banks idle (ABI) Any State Other than Listed Above 6 CKEn-1 H L L L L L L H L L L L L L H H H H H H H H L H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X H L L L L L L X X X X X /RAS X X H H H L X X X H H H X X X X H H H L L L X X X X X /CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X /WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down ABI Exit Power Down ABI ILLEGAL ILLEGAL 6 ILLEGAL NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension Æ Æ Æ Æ Notes: 6. Power-down and self refresh can be entered only when all the banks are in an idle state.