FEDL63193-04 1Semiconductor ML63193 This version: Sep. 2001 Previous version: Mar. 2000 4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Driver and Melody Circuit. GENERAL DESCRIPTION The ML63193 is CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers (64 SEG. × 16 COM.), and operates at 0.9 V (Min). The ML63193 is suitable for applications as games, toys, watches, remote controller, etc. Which are provided with a LCD display. The ML63193 is an M6318x series mask ROM-version product of OLMS-63K family, which employs Oki’s original CPU core nX-4/250. FEATURES • Extensive instruction set 408 instructions: Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations, bit operations, ROM table reference, stack operations, flag operations, jump, conditional branch, call/return, control • Wide variety of addressing modes Indirect addressing mode for 4 types of data memory with current bank register, extra bank register, HL register and XY register Data memory bank internal direct addressing mode • Processing speed 2 clocks per machine cycle, with most instructions executed in 1 machine cycle Minimum instruction execution time : 61 µs (@ 32.768 kHz system clock) : 1 µs (@ 2 MHz system clock) • Clock generation circuit Low-speed clock High-speed clock : Crystal oscillation or RC oscillation selected with mask option (30 kHz to 80 kHz) : Ceramic oscillation or RC oscillation selected with software (2 MHz max) • Program memory space 64 K words Basic instruction length is 16 bits/1word. • Data memory space 2048 nibbles • Stack level Call stack level Register stack level : 16 levels : 16 levels 1/37 FEDL63193-04 1Semiconductor ML63193 • I/O Ports Input ports: Selectable as input pull-up resistor/input pull-down resistor/high impedance input. I/O ports: Selectable as input pull-up resistor/input pull-down resistor/high impedance input. Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/ CMOS output. Can be interfaced with external peripherals that use a different power supply than this device uses.VDDI is the power supply pin for ports. Number of ports: Input port : 1 port × 4 bits Input-output port : 5 ports × 4 bits • Melody output Melody frequency Tone length Tempo Melody data Buzzer driver signal output : 529 Hz to 2979 Hz : 63 varieties : 15 varieties : Stored in program memory : 4 kHz • LCD driver Number of segments Duty Bias Frame frequency : : : : Contrast Display modes • Multiplier/divider circuit Multiplier Divider 1024 Max. (64 SEG. × 16 COM.) Selectable as 1/1 to 1/16 duty Selectable as 1/4 or 1/5 bias (regulator built-in) ex. 64 Hz (at 1/16 duty), 128 Hz (at 1/8 duty), 256 Hz (at 1/4 duty), 512 Hz (at 1/2 duty), 1024 Hz (at 1/1 duty) : 16 levels adjustable : Selectable as all-ON mode/all-OFF mode/power down mode/ normal display mode : (8 bits)×(8 bits) → Product (16 bits) : (16 bits)/(8 bits) → Quotient (16 bits), Remainder (8 bits) • System reset function System reset through RESET pin (selectable as built-in 2 kHz RESET-Sampling circuit by mask option) System reset by power-on detection (When not using 2 kHz RESET-Sampling circuit) System reset by low-speed oscillation halt • Battery check Low-voltage supply check The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of BLDCON). LD1 LD0 Judgment Voltage (V) Remarks 0 0 1.05 ± 0.10 Ta = 25°C 0 1 1.20 ± 0.10 Ta = 25°C 1 0 1.80 ± 0.10 Ta = 25°C 1 1 2.40 ± 0.10 Ta = 25°C 2/37 FEDL63193-04 1Semiconductor • Timers and Counter 8-bit timer Watchdog timer 100 Hz timer 15-bit time-base counter ML63193 :4 Selectable as auto-reload mode/capture mode/ clock frequency measurement mode :1 :1 Measurable in steps of 1/100 sec. :1 1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read • Serial port Mode : Selectable as UART mode, synchronous mode UART communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps Clock frequency in synchronous mode : Internal clock mode (32.768 kHz), External clock frequency Data length : 5 to 8 bits • Shift register Shift clock Data length : 1× or 1/2 × system clock, timer 1 overflow, external clock : 8 bits • Interrupt factors External interrupt Internal interrupt :4 : 14 (watchdog timer interrupt is a nonmaskable interrupt) • Operating temperature : –20 to +70 °C • Power supply backup Backup circuit (voltage multiplier) enables operation at 0.9 V minimum. • Power supply voltage When backup used When backup not used : 0.9 V to 2.7 V (Operating frequency: 30 k to 80 kHz) 1.2 V to 2.7 V (Operating frequency: 300 k to 500 kHz) 1.5 V to 2.7 V (Operating frequency: 200 k to 1 MHz) : 1.8 V to 5.5 V (Operating frequency: 200 k to 2 MHz) • Package: Chip (128 pads) : (Product name: ML63193-xxxWA) 144-pin plastic LQFP (LQFP144-P-2020-0.50-K) : (Product name: ML63193-xxxTC) xxx indicates a code number. 3/37 FEDL63193-04 1Semiconductor ML63193 MASK OPTION In the ML63193 uses the mask option to specify the following functions: • Low-Speeed clock oscillation circuit Specify the crystal oscillation circuit or the RC oscillation circuit for the low-speed clock oscillation circuit. • Reset signal sampling Specify whether or not the reset signal will be sampled at 2 kHz. When specifying “will carry out 2 kHz sampling,” hold the RESET pin at a “H” level for 1 ms or more. To use the mask option, assign mask option data in the application program in accordance with the formats below. The mask option area is an application program execution disabled area. Mask Option Data Assignment Format Function Mask option area Low-speed clock oscillation circuit (crystal oscillation circuit/RC oscillation circuit) Reset signal sampling (will/will not carry out 2 kHz sampling) bit bit 0 0FFE0H bit 1 data Option to be selected 0 Crystal oscillation circuit 1 RC oscillation circuit 0 Will carry out 2 kHz sampling 1 Will not carry out 2 kHz sampling 4/37 FEDL63193-04 1Semiconductor ML63193 BLOCK DIAGRAM Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines ( Indicate interface signals of the VDDI power supply system. ) CPU core nX-4/250 TIMING CONTROL CBR H L RA EBR X Y A SP C Z ALU RSP STACK CAL.S:16-level REG.S:16-level G PC MIE INSTRUCTION DECODER ROM 64KW BUS CONTROL IR INT 4 RAM 2048N TIMER 8bit (4ch) INT 2 SIO RXC* TXC* RXD* TXD* SFT SCLK* SIN* SOUT* INT INT193 1 RESET RST MULDIV INT 1 INT TST2 TST 4 BLD XT0 XT1 OSC0 OSC VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDL INT INPUT PORT MD MDB P0.0 - P0.3 1 INT 1 MELODY 100HzTC P9.0 - P9.3 OSC1 VDDH VDD CB1 CB2 TBC DATA BUS TST1 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* INT 1 BACK UP BIAS PA.0 - PA.3 WDT I/O PORT INT PB.0 - PB.3 PC.0 - PC.3 3 PE.0 - PE.3 LCD & DSPR COM1 - 16 SEG0 - 63 VDDI VSS 5/37 FEDL63193-04 1Semiconductor ML63193 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 (NC) (NC) (NC) PC.3 PC.2 PC.1 PC.0 PE.3 PE.2 PE.1 PE.0 VDDI MDB MD TST2 TST1 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS (NC) (NC) (NC) (NC) SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG49 SEG48 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 (NC) (NC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (NC) (NC) SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 (NC) (NC) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (NC) SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS P0.3 P0.2 P0.1 P0.0 P9.3 P9.2 P9.1 P9.0 PA.3 PA.2 PA.1 PA.0 PB.3 PB.2 PB.1 PB.0 (NC) (NC) PIN CONFIGURATION (TOP VIEW) 144-Pin Plastic LQFP (TC: LQFP144-P-2020-0.50-K) Note: Pins marked as (NC) are no-connection pins which are left open. 6/37 FEDL63193-04 1Semiconductor ML63193 PAD CONFIGURATION 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PC.3 PC.2 PC.1 PC.0 PE.3 PE.2 PE.1 PE.0 VDDI MDB MD TST2 TST1 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS Pad Layout PB.0 96 PB.1 97 PB.2 98 PB.3 99 PA.0 100 PA.1 101 PA.2 102 PA.3 103 P9.0 104 P9.1 105 P9.2 106 P9.3 107 P0.0 108 P0.1 109 P0.2 110 P0.3 111 VSS 112 COM1 113 COM2 114 COM3 115 COM4 116 COM5 117 COM6 118 COM7 119 COM8 120 SEG0 121 SEG1 122 SEG2 123 SEG3 124 SEG4 125 SEG5 126 SEG6 127 SEG7 128 ML63193 Y X COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (0,0) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Chip size Chip thickness Coordinate origin Pad hole size Pad size Minimum pad pitch : 5.72 mm × 5.72 mm : 350 µm (280 µm: available as required) : center of chip : 100 µm × 100 µm : 110 µm × 110 µm : 140 µm Note: The chip substrate voltage is VSS. 7/37 FEDL63193-04 1Semiconductor ML63193 Pad Coordinates Center of chip: X = 0, Y = 0 Pad Name SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pad Name SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 23 SEG30 885 –2714 66 VDD1 2011 2714 24 SEG31 1025 –2714 67 VDD2 1871 2714 25 SEG32 1166 –2714 68 VDD3 1730 2714 26 SEG33 1306 –2714 69 VDD4 1590 2714 27 SEG34 1447 –2714 70 VDD5 1450 2714 28 SEG35 1587 –2714 71 C1 1309 2714 29 SEG36 1727 –2714 72 C2 1169 2714 30 SEG37 1868 –2714 73 1028 2714 31 32 33 SEG38 SEG39 SEG40 2008 2149 2714 –2714 –2714 –2149 74 75 76 VDDH CB1 CB2 888 748 607 2714 2714 2714 34 SEG41 2714 –2008 77 35 36 37 SEG42 SEG43 SEG44 2714 2714 2714 –1868 –1727 –1587 78 79 80 38 SEG45 2714 –1447 81 39 SEG46 2714 –1306 40 SEG47 2714 41 SEG48 2714 42 SEG49 43 SEG50 Pad No. X (µm) Y (µm) Pad No. –2204 –2063 –1923 –1783 –1642 –1502 –1361 –1221 –1081 –940 –800 –659 –519 –379 –238 –98 43 183 323 464 604 745 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 X (µm) Y (µm) VSS 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2152 –604 –464 –323 –183 –43 98 238 379 519 659 800 940 1081 1221 1361 1502 1642 1783 1923 2063 2204 2714 VDD 467 2714 RESET 326 186 46 2714 2714 2714 XT1 –95 2714 82 XT0 –235 2714 –1166 83 TST1 –376 2714 –1025 84 TST2 –516 2714 2714 –885 85 MD –656 2714 2714 –745 86 MDB –797 2714 VDDL OSC1 OSC0 8/37 FEDL63193-04 1Semiconductor ML63193 Center of chip: X = 0, Y = 0 Pad No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pad Name VDDI PE.0 PE.1 PE.2 PE.3 PC.0 PC.1 PC.2 PC.3 PB.0 PB.1 PB.2 PB.3 PA.0 PA.1 PA.2 PA.3 P9.0 P9.1 P9.2 P9.3 X (µm) Y (µm) Pad No. –937 2714 108 Pad Name P0.0 –1078 –1218 –1358 –1499 –1639 –1780 –1920 –2060 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 2714 2714 2714 2714 2714 2714 2714 2714 2246 2106 1966 1825 1685 1544 1404 1264 1123 983 842 702 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P0.1 P0.2 P0.3 VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 X (µm) Y (µm) –2714 562 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 –2714 421 281 140 0 –140 –281 –421 –562 –702 –842 –983 –1123 –1264 –1404 –1544 –1685 –1825 –1966 –2106 –2246 9/37 FEDL63193-04 1Semiconductor ML63193 PIN DESCRIPTIONS The basic functions of each pin of the ML63193 are described in Table 1. A symbol with a slash “/” denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input-output pin. Table 1 Pin Descriptions (Basic Functions) Function Power Supply Symbol Pin No. Pad No. Type VDD 50 76 — Positive power supply pin VSS 39,91 65,112 — Negative power supply pin VDD1 40 66 VDD2 41 67 VDD3 42 68 VDD4 43 69 VDD5 44 70 C1 45 71 C2 46 72 VDDI 61 87 VDDL 51 77 VDDH 47 73 CB1 48 74 Power supply pins for LCD bias (internally generated): — Capacitors (0.1 µF) should be connected between these pins and VSS. — Capacitor connection pins for LCD bias generation: A capacitor (0.1 µF) should be connected between C1 and C2. — Positive power supply pin for external interface (Power supply for input, and input-output ports) — Positive power supply pin for internal logic (internally generated): A capacitor (0.1 µF) should be connected between this pin and VSS. — Voltage multiplier pin for power supply backup (internally generated): A capacitor (1.0 µF) should be connected between this pin and VSS. Pins to connect a capacitor for voltage multiplier. — CB2 Oscillation Description 49 75 XT0 56 82 I XT1 55 81 O OSC0 53 79 I OSC1 52 78 O A capacitor (1.0 µF) should be connected between CB1 and CB2. Low-speed clock oscillation pins: An option for using crystal oscillation or RC oscillation is chosen by the mask option. If the crystal oscillation is chosen, a crystal should be connected between XT0 and XT1, and capacitor (CG) should be connected between XT0 and VSS. If the RC oscillation is chosen, external oscillation resistor (ROSL) should be connected between XT0 and XT1. High-speed clock oscillation pins: A ceramic resonator and capacitors (CL0, CL1) or external oscillation resistor (ROSH) should be connected to these pins. 10/37 FEDL63193-04 1Semiconductor ML63193 Table 1 Pin Descriptions (Basic Functions) (continued) Function Symbol Pin No. Pad No. Type Description TST1 57 83 I TST2 58 84 I Input pins for testing. A pull-down resistor is internally connected to these pins. The user cannot use these pins. Test System reset input pin. Setting this pin to “H“ level puts this device into a reset state. Then, setting this pin to “ L” level starts executing an instruction from address 0000H. Reset RESET 54 80 I An option for using RESET sampling circuit or not using is chosen by the mask option. When using RESET sampling circuit, the system reset mode is entered by holding the RESET pin at a “ H” level for 1ms or more. A pull-down resistor is internally connected to this pin. Melody MD 59 85 O Melody output pin (non-inverted output) MDB 60 86 O Melody output pin (inverted output) 11/37 FEDL63193-04 1Semiconductor ML63193 Table 1 Pin Descriptions (Basic Functions) (continued) Function Port Symbol Pin No. Pad No. P0.0/INT5 87 108 P0.1/INT5 88 109 P0.2/INT5 89 110 P0.3/INT5 90 111 P9.0 83 104 P9.1 84 105 P9.2 85 106 P9.3 86 107 PA.0 79 100 PA.1 80 101 PA.2 81 102 PA.3 82 103 PB.0/INT0/ TM0CAP/ TM0OVF 75 96 PB.1/INT0/ TM1CAP/ TM1OVF 76 97 PB.2/INT0/ T02CK 77 98 PB.3/INT0/ T13CK 78 99 PC.0/INT1/ RXD 66 92 PC.1/INT1/ TXC 67 93 PC.2/INT1/ RXC 68 94 PC.3/INT1/ TXD 69 95 PE.0/SIN 62 88 PE.1/SOUT 63 89 PE.2/SCLK 64 90 PE.3/INT2 65 91 Type I I/O I/O Description 4-bit input port: Pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. 4-bit input output ports: In input mode, pull-up resister input, pull-down resister input, or high-impedance input is selectable for each bit. In output mode, P-channel open drain output, Nchannel open drain output, CMOS output, or highimpedance output is selectable for each bit. I/O I/O I/O 12/37 FEDL63193-04 1Semiconductor ML63193 Table 1 Pin Descriptions (Basic Functions) (continued) Function LCD Symbol Pin No. Pad No. COM1 92 113 COM2 93 114 COM3 94 115 COM4 95 116 COM5 96 117 COM6 97 118 COM7 98 119 COM8 99 120 COM9 27 57 COM10 28 58 COM11 29 59 COM12 30 60 COM13 31 61 COM14 32 62 COM15 33 63 COM16 34 64 SEG0 100 121 SEG1 101 122 SEG2 102 123 SEG3 103 124 SEG4 104 125 SEG5 105 126 SEG6 106 127 SEG7 107 128 SEG8 111 1 SEG9 112 2 SEG10 113 3 SEG11 114 4 SEG12 115 5 SEG13 116 6 SEG14 117 7 SEG15 118 8 SEG16 119 9 Type Description LCD common signal output pins O LCD segment signal output pins O 13/37 FEDL63193-04 1Semiconductor ML63193 Table 1 Pin Descriptions (Basic Functions) (continued) Function LCD Symbol Pin No. Pad No. SEG17 120 10 SEG18 121 11 SEG19 122 12 SEG20 123 13 SEG21 124 14 SEG22 125 15 SEG23 126 16 SEG24 127 17 SEG25 128 18 SEG26 129 19 SEG27 130 20 SEG28 131 21 SEG29 132 22 SEG30 133 23 SEG31 134 24 SEG32 135 25 SEG33 136 26 SEG34 137 27 SEG35 138 28 SEG36 139 29 SEG37 140 30 SEG38 141 31 SEG39 142 32 SEG40 3 33 SEG41 4 34 SEG42 5 35 SEG43 6 36 SEG44 7 37 SEG45 8 38 SEG46 9 39 SEG47 10 40 SEG48 11 41 SEG49 12 42 Type Description LCD segment signal output pins O 14/37 FEDL63193-04 1Semiconductor ML63193 Table 1 Pin Descriptions (Basic Functions) (continued) Function LCD Symbol Pin No. Pad No. SEG50 13 43 SEG51 14 44 SEG52 15 45 SEG53 16 46 SEG54 17 47 SEG55 18 48 SEG56 19 49 SEG57 20 50 SEG58 21 51 SEG59 22 52 SEG60 23 53 SEG61 24 54 SEG62 25 55 SEG63 26 56 Type Description LCD segment signal output pins O 15/37 FEDL63193-04 1Semiconductor ML63193 Table 2 shows the secondary functions of each pin of the ML63193. Table 2 Pin Descriptions (Secondary Functions) Function External Interrupt Capture Timer Symbol Pin No. Pad No. Type Description PB.0/INT0 75 96 I External 0 interrupt input pins The change of input signal level causes an interrupt to occur. The Port B Interrupt Enable register (PBIE) enables or disables an interrupt for each bit. PB.1/INT0 76 97 PB.2/INT0 77 98 PB.3/INT0 78 99 PC.0/INT1 66 92 PC.1/INT1 67 93 I External 1 interrupt input pins The change of input signal level causes an interrupt to occur. The Port C Interrupt Enable register (PCIE) enables or disables an interrupt for each bit. PC.2/INT1 68 94 PC.3/INT1 69 95 PE.3/INT2 65 91 I External 2 interrupt input pin The change of input signal level causes an interrupt to occur. P0.0/INT5 87 108 I External 5 interrupt input pins The change of input signal level causes an interrupt to occur. The Port 0 Interrupt Enable register (P0IE) enables or disables an interrupt for each bit. P0.1/INT5 88 109 P0.2/INT5 89 110 P0.3/INT5 90 111 PB.0/ TM0CAP 75 96 I Timer 0 capture input pin PB.1/ TM1CAP 76 97 I Timer 1 capture input pin PB.0/ TM0OVF 75 96 O Timer 0 overflow flag output pin PB.1/ TM1OVF 76 97 O Timer 1 overflow flag output pin PB.2/T02CK 77 98 I External clock input pin for timer 0 and timer 2. PB.3/T13CK 78 99 I External clock input pin for timer 1 and timer 3 16/37 FEDL63193-04 1Semiconductor ML63193 Table 2 Pin Descriptions (Secondary Functions) (continued) Function Symbol Pin No. Pad No. Type PC.0/RXD 66 92 I PC.1/TXC 67 93 Description Serial port receive data input pin I/O Sync serial port clock input-output pin Transmit clock output when this device is used as a master processor. Transmit clock input when this device is used as a slave processor. Serial Port PC.2/RXC 68 94 I/O Sync serial port clock input-output pin Receive clock output when this device is used as a master processor. Receive clock input when this device is used as a slave processor. PC.3/TXD 69 95 O Serial port transmit data output pin PE.0/SIN 62 88 I Shift register receive data input pin PE.1/SOUT 63 89 O Shift register transmit data output pin I/O Shift register clock input-output pin. Clock output when this device is used as a master processor. Clock input when this device is used as a slave processor. Shift Register PE.2/SCLK 64 90 17/37 FEDL63193-04 1Semiconductor ML63193 ABSOLUTE MAXIMUM RATINGS (VSS = 0 V) Symbol Condition Rating Unit Power supply voltage 1 Parameter VDD1 Ta = 25°C –0.3 to +1.6 V Power supply voltage 2 VDD2 Ta = 25°C –0.3 to +2.9 V Power supply voltage 3 VDD3 Ta = 25°C –0.3 to +4.2 V Power supply voltage 4 VDD4 Ta = 25°C –0.3 to +5.5 V Power supply voltage 5 VDD5 Ta = 25°C –0.3 to +6.8 V Power supply voltage 6 VDD Ta = 25°C –0.3 to +6.0 V Power supply voltage 7 VDDI Ta = 25°C –0.3 to +6.0 V Power supply voltage 8 VDDH Ta = 25°C –0.3 to +6.0 V Input voltage 1 VIN1 VDD input, Ta = 25°C –0.3 to VDD + 0.3 V Input voltage 2 VIN2 VDDI input, Ta = 25°C –0.3 to VDDI + 0.3 V Output voltage 1 VOUT1 VDD1 output, Ta = 25°C –0.3 to VDD1 + 0.3 V Output voltage 2 VOUT2 VDD2 output, Ta = 25°C –0.3 to VDD2 + 0.3 V Output voltage 3 VOUT3 VDD3 output, Ta = 25°C –0.3 to VDD3 + 0.3 V Output voltage 4 VOUT4 VDD4 output, Ta = 25°C –0.3 to VDD4 + 0.3 V Output voltage 5 VOUT5 VDD5 output, Ta = 25°C –0.3 to VDD5 + 0.3 V Output voltage 6 VOUT6 VDD output, Ta = 25°C –0.3 to VDD + 0.3 V Output voltage 7 VOUT7 VDDI output, Ta = 25°C –0.3 to VDDI + 0.3 V Output voltage 8 VOUT8 VDDH output, Ta = 25°C –0.3 to VDDH + 0.3 V Storage temperature TSTG — –55 to +150 °C 18/37 FEDL63193-04 1Semiconductor ML63193 RECOMMENDED OPERATING CONDITIONS • When backup is used (VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-speed RC Oscillation Frequency Ceramic Oscillation Frequency High-speed RC Oscillation Frequency Symbol Condition Rating Unit Top — –20 to +70 °C VDD — 0.9 to 2.7 V VDDI — 0.9 to 5.5 V fXT CG = 5 to 25 pF 32.768 to 76.8 kHz ROSL = 1.0 MΩ 36 ± 30% ROSL = 1.1 MΩ 33 ± 30% fROSL fCM fROSH ROSL = 1.2 MΩ 30 ± 30% VDD = 0.9 to 1.2 V Not applied VDD = 1.2 to 2.7 V 300 k to 500 k VDD = 1.5 to 2.7 V 200 k to 1 M VDD = 0.9 to 1.2 V Not applied VDD = 1.2 to 2.7 V ROSH = 400 kΩ 200 k ± 30% ROSH = 100 kΩ 700 k ± 30% ROSH = 75 kΩ 1 M ± 30% kHz Hz Hz • When backup is not used (VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-speed RC Oscillation Frequency Ceramic Oscillation Frequency Symbol Condition Rating Unit Top — –20 to +70 °C VDD — 1.8 to 5.5 V VDDI — 1.8 to 5.5 V fXT CG = 5 to 25 pF 32.768 to 76.8 kHz ROSL = 1.0 MΩ 36 ± 30% ROSL = 1.1 MΩ 33 ± 30% ROSL = 1.2 MΩ 30 ± 30% VDD = 1.8 to 5.5 V 200 k to 2 M fROSL fCM ROSH = 100 kΩ High-speed RC Oscillation Frequency fROSH VDD = 1.8 to 3.6 V Hz 700 k ± 30% ROSH = 75 kΩ 1 M ± 30% ROSH = 51 kΩ 1.35 M ± 30% VDD = 1.8 to 3.5 V, ROSH = 30 kΩ kHz Hz 2 M ± 30% 19/37 FEDL63193-04 1Semiconductor ML63193 • Typical characteristics of low-speed RC oscillation When backup is used/backup is not used (VDD = VDDI = 1.5 V/VDD = VDDI = 3.0 V) Reference data fROSL [kHz] 1000 100 10 100 1000 ROSL [kΩ] 10000 • Typical characteristics of high-speed RC oscillation When backup is used (VDD = VDDI = 1.5 V) Reference data fROSH [kHz] 10000 1000 100 10 100 1000 ROSH [kΩ] 20/37 FEDL63193-04 1Semiconductor ML63193 • Typical characteristics of high-speed RC oscillation When backup is not used (VDD = VDDI = 3.0 V) Reference data fROSH [kHz] 10000 1000 100 10 100 1000 ROSH [kΩ] 21/37 FEDL63193-04 1Semiconductor ML63193 ELECTRICAL CHARACTERISTICS DC Characteristics (1) (VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified) Parameter Symbol Condition 1/5 bias, 1/4 bias Min. Typ. Max. Unit 1.7 1.8 1.9 V mV/ °C VDD2 Voltage VDD2 VDD2 Voltage Temperature Deviation ∆VDD2 — — –4.0 — VDD1 Voltage VDD1 1/5 bias, 1/4 bias Typ.–0.1 1/2 × VDD2 Typ.+0.1 1/5 bias Typ.–0.3 2/3 × VDD2 Typ.+0.3 VDD3 Voltage VDD3 1/4 bias (connect VDD3 and VDD2) Typ.–0.2 VDD2 Typ.+0.2 VDD4 Voltage VDD4 1/5 bias Typ.–0.4 2 × VDD2 Typ.+0.4 1/4 bias Typ.–0.3 3/2 × VDD2 Typ.+0.3 VDD5 Voltage VDD5 1/5 bias Typ.–0.5 5/2 × VDD2 Typ.+0.5 1/4 bias Typ.–0.4 2 × VDD2 Typ.+0.4 High-speed clock oscillation stopped 2.8 — 3.0 2.0 — 2.7 1.0 1.5 2.0 1.2 — 5.5 VDDH Voltage (Backup used) VDDH (Ta = 25°C) High-speed clock oscillation (Ceramic oscillation, 1 MHz) VDD = 1.2 to 5.5 V Note: V VDD = 1.5 V High-speed clock oscillation stopped VDDL 1 High-speed clock oscillation (Ceramic oscillation, 1 MHz) VDD = 1.5 V VDDL Voltage Measuring Circuit 1. “VDD2” changes in the range from 1.8 to 2.4 V according to the valve of Display Contrast register (DSPCNT) 22/37 FEDL63193-04 1Semiconductor ML63193 DC Characteristics (2) (VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Crystal Oscillation Start Voltage VSTA Oscillation start time: within 5 seconds 1.2 — — Backup used 0.9 — — Backup not used 1.7 — — Crystal Oscillation Hold Voltage VHOLD Crystal Oscillation Stop Detect Time TSTOP — 0.1 — 5.0 External RC Oscillator Capacitance CG — 5 — 25 Internal RC Oscillator Capacitance CD — 20 25 30 CL0, CL1 CSA2.00 MG (Murata MFG.–make) used VDD = 3.0 V — 30 — Internal RC Oscillator Capacitance COS — 8 12 16 POR Voltage VPOR1 VDD = 1.5 V 0 — 0.4 VDD = 3.0 V 0 — 0.7 Non-POR Voltage VPOR2 VDD = 1.5 V 1.2 — 1.5 External Ceramic Oscillator Capacitance BLD Judgment Voltage BLD Judgment Voltage Temperature Deviation Unit Measuring Circuit V ms pF 1 VBLDC ∆VBLDC VDD = 3.0 V 2 — 3 LD1 = 1, LD0 = 1, Ta = 25°C 2.30 2.40 2.50 LD1 = 1, LD0 = 0, Ta = 25°C 1.70 1.80 1.90 LD1 = 0, LD0 = 1, Ta = 25°C 1.10 1.20 1.30 LD1 = 0, LD0 = 0, Ta = 25°C 0.95 1.05 1.15 VBLDC = 2.40 V (LD1 = 1, LD0 = 1) — –3.5 — VBLDC = 1.80 V (LD1 = 1, LD0 = 0) — –2.3 — VBLDC = 1.20 V (LD1 = 0, LD0 = 1) — –1.6 — VBLDC = 1.05 V (LD1 = 0, LD0 = 0) — –1.2 — V mV/ °C Notes: 1. “TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. 2. “POR” denotes Power On Reset. (When not using RESET sampling circuit) 3. “VPOR1” indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises up to VDD. 4. “VPOR2” indicates that POR dose not occur when VDD falls from VDD VPOR2 and again rises up to VDD. 23/37 FEDL63193-04 1Semiconductor ML63193 DC Characteristics (3) • When backup is used (Low-speed clock = Crystal oscillation (32.768 kHz), VDD = VDDI = 1.5 V, VSS = 0 V, Display contrast register (DSPCNT) = 0H, Ta = –20 to +70°C unless otherwise specified) Parameter Supply Current 1 Supply Current 2 Symbol IDD1 IDD2 Condition Min. Typ. Max. Ta = –20 to +50°C — 5.6 6.5 Ta = –20 to +70°C — 5.6 15.0 CPU is in HALT state. LCD is in Power Down mode. Ta = –20 to +50°C — 4.5 5.0 (High-speed clock Ta = –20 to +70°C — 4.5 13.0 Ta = –20 to +50°C — 23 26 Ta = –20 to +70°C — 23 30 CPU is in operation at high-speed oscillation. (approx. 700 kHz RC oscillation, — 1100 1500 — 950 1200 CPU is in HALT state. (High-speed clock oscillation stopped) Unit Measuring Circuit µA 1 oscillation stopped) Supply Current 3 Supply Current 4 Supply Current 5 IDD3 IDD4 CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped) ROSH = 100 kΩ) IDD5 CPU is in operation at high-speed oscillation. (1 MHz Ceramic oscillation) 24/37 FEDL63193-04 1Semiconductor ML63193 DC Characteristics (4) • When backup is not used (Low-speed clock = Crystal oscillation (32.768 kHz), VDD = VDDI = 3.0 V, VSS = 0 V, Display contrast register (DSPCNT) = 0H, Ta = –20 to +70°C unless otherwise specified) Parameter Supply Current 1 Supply Current 2 Symbol IDD1 IDD2 Condition Min. Typ. Max. Ta = –20 to +50°C — 2.6 3.5 Ta = –20 to +70°C — 2.6 7.0 CPU is in HALT state. LCD is in Power Down mode. Ta = –20 to +50°C — 2.0 2.8 (High-speed clock Ta = –20 to +70°C — 2.0 6.0 Ta = –20 to +50°C — 12 13 Ta = –20 to +70°C — 12 16 CPU is in operation at high-speed oscillation. (approx. 700 kHz RC oscillation, — 1000 1200 — 1100 1300 CPU is in HALT state. (High-speed clock oscillation stopped) Unit Measuring Circuit µA 1 oscillation stopped) Supply Current 3 Supply Current 4 Supply Current 5 IDD3 IDD4 CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped) ROSH = 100 kΩ) IDD5 CPU is in operation at high-speed oscillation. (2 MHz Ceramic oscillation) 25/37 FEDL63193-04 1Semiconductor ML63193 DC Characteristics (5) (VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified) Parameter Output Current 1 (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) Symbol IOH1 IOL1 Condition VOH1 = VDDI – 0.5 V VOL1 = 0.5 V (PE.0 to PE.3) IOH2 VOH2 = VDD – 0.7 V Output Current 2 (MD, MDB) IOL2 IOH3 Output Current 3 (SEG0 to SEG63) (COM1 to COM16) Output Current 4 (OSC1) Output Leakage Current (P2.0 to P2.3) VOL2 = 0.7 V Min. Typ. Max. VDDI = 1.5 V –2.5 –1.4 –0.4 VDDI = 3.0 V –6.0 –3.5 –1.0 VDDI = 5.0 V –8.5 –5.0 –1.5 VDDI = 1.5 V 0.4 1.4 2.5 VDDI = 3.0 V 1.0 3.0 6.0 VDDI = 5.0 V 1.5 3.7 8.5 VDD = 1.5 V –4.0 –2.0 –0.5 VDD = 3.0 V –11.0 –6.0 –2.0 VDD = VDDH = 5.0 V –14.0 –9.0 –4.0 VDD = 1.5 V 0.5 2.0 4.0 VDD = 3.0 V 2.0 5.5 11.0 VDD = VDDH = 5.0 V 4.0 7.0 14.0 – — –4 VOH3 = VDD5 – 0.2 V (VDD5 level) IOHM3 VOHM3 = VDD4 + 0.2 V (VDD4 level) 4 — — IOHM3S VOHM3S = VDD4 – 0.2 V (VDD4 level) — — –4 IOMH3 VOMH3 = VDD3 + 0.2 V (VDD3 level) 4 — — IOMH3S VOMH3S = VDD3 – 0.2 V (VDD3 level) — — –4 IOML3 VOML3 = VDD2 + 0.2 V (VDD2 level) 4 — — IOML3S VOML3S = VDD2 – 0.2 V (VDD2 level) — — –4 IOLM3 VOLM3 = VDD1 + 0.2 V (VDD1 level) 4 — — IOLM3S VOLM3S = VDD1 – 0.2 V (VDD1 level) — — –4 IOL3 VOL3 = VSS + 0.2 V (VSS level) 4 — — IOH4R VOH4R = VDDH – 0.5 V (RC oscillation) IOL4R VOL4R = 0.5 V (RC oscillation) IOH4C VOH4C = VDDH – 0.5 V (ceramic oscillation) IOL4C VOL4c = 0.5 V (ceramic oscillation) VDD = VDDH = 3.0 V –2.5 –1.3 –0.25 VDD = VDDH = 5.0 V –3.5 –1.7 –0.5 VDD = VDDH = 3.0 V 0.25 1.5 2.5 VDD = VDDH = 5.0 V 0.5 1.8 3.5 VDD = VDDH = 3.0 V –500 –250 –100 VDD = VDDH = 5.0 V –800 –350 –200 VDD = VDDH = 3.0 V 200 500 800 VDD = VDDH = 5.0 V 400 700 1000 IOOH VOH = VDDI — — 0.3 IOOL VOL = VSS –0.3 — — Unit Measuring Circuit mA µA 2 mA µA (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) 26/37 FEDL63193-04 1Semiconductor ML63193 DC Characteristics (6) (VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified) Parameter Symbol IIH1 Input Current 1 (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) IIL1 VIL1 = VSS (when pulled up) Max. VDDI = 1.5 V 2 20 45 VDDI = 3.0 V 30 120 260 VDDI = 5.0 V 70 350 650 VDDI = 1.5 V –45 –20 –2 VDDI = 3.0 V –260 –120 –30 VDDI = 5.0 V –350 –70 IIH1Z 0 — 1 IIL1Z VIL1 = VSS (in a high impedance state) –1 — 0 VIL2 = VSS VDD = VDDH = 3.0 V –350 –170 –30 (when pulled up) VDD = VDDH = 5.0 V –750 –450 –200 IIH2R VIH2R = VDDH (RC oscillation) 0 — 1 IIL2R VIL2R = VSS (RC oscillation) –1 — 0 IIL2C IIH3 VIH2C = VDDH VDD = VDDH = 3.0 V 0.5 1.8 4.0 (ceramic oscillation) VDD = VDDH = 5.0 V 3 6 10 VIL2C = VSS VDD = VDDH = 3.0 V –4.0 –1.8 –0.5 (ceramic oscillation) VDD = VDDH = 5.0 V –10 –6 –3 VDD = 1.5 V 10 180 350 VDD = 3.0 V 150 1100 2400 VDD = VDDH = 5.0 V 0.5 2.7 5.0 VIH3 = VDD IIL3 Input Current 4 (TST1, TST2) Typ. –650 IIH2C Input Current 3 (RESET) VIH1 = VDDI (when pulled down) Min. VIH1 = VDDI (in a high impedance state) IIL2 Input Current 2 (OSC0) Condition IIH4 IIL4 VIL3 = VSS –1 — 0 VDD = 1.5 V 50 750 1500 VDD = 3.0 V 0.5 3.0 5.5 VDD = VDDH = 5.0 V 2.0 6.5 11.0 –1 — 0 VIH4 = VDD VIL4 = VSS Unit Measuring Circuit µA 3 mA µA mA µA 27/37 FEDL63193-04 1Semiconductor ML63193 DC Characteristics (7) (VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified) Parameter Input Voltage 1 (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) Input Voltage 2 (OSC0) Symbol VIH1 VIL1 VIH2 VIL2 Input Voltage 3 (RESET), (TST1), (TST2) VIH3 VIL3 Hysteresis Width 1 (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) ∆VT1 (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) Hysteresis Width 2 (RESET), (TST1), (TST2) Input Pin Capacitance (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) ∆VT2 CIN Condition Min. Typ. Max. VDDI = 1.5 V 1.2 — 1.5 VDDI = 3.0 V 2.4 — 3.0 VDDI = 5.0 V 4.0 — 5.0 VDDI = 1.5 V 0 — 0.3 VDDI = 3.0 V 0 — 0.6 VDDI = 5.0 V 0 — 1 VDD = VDDH = 3.0 V 2.4 — 3.0 VDD = VDDH = 5.0 V 4.0 — 5.0 VDD = VDDH = 3.0 V 0 — 0.6 VDD = VDDH = 5.0 V 0 — 1 VDD = 1.5 V 1.35 — 1.5 VDD = 3.0 V 2.4 — 3.0 VDD = 5.0 V 4.0 — 5.0 VDD = 1.5 V 0 — 0.15 VDD = 3.0 V 0 — 0.6 VDD = 5.0 V 0 — 1 VDDI = 1.5 V 0.05 0.1 0.3 VDDI = 3.0 V 0.2 0.5 1.0 VDDI = 5.0 V 0.25 1.0 1.5 VDD = 1.5 V 0.05 0.1 0.3 VDD = 3.0 V 0.2 0.5 1.0 VDD = 5.0 V 0.25 1.0 1.5 — — — 5 Unit Measuring Circuit V 4 pF 1 (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) 28/37 FEDL63193-04 1Semiconductor ML63193 Measuring circuit 1 CB1 XT0 3 CB2 C1 XT1 4 Cb12 *2 C12 *1 1 2 C2 OSC0 OSC1 VSS VDD VDDI A VDD2 VDD1 Ca Cb V VDD4 VDD3 Cd Cc V Ca, Cb, Cc, Cd, Ce, Cl, C12 Ch, Cb12 CG CL0 CL1 Ceramic Resonator *1 RC Oscillator V : : : : : : VDDH VDD5 Ch Ce V VDDL V Cl V V 0.1 µF 1 µF 15 pF 30 pF 30 pF CSA2.00MG (2 MHz) CSB1000J (1 MHz) (Murata MFG.-make) *2 RC Oscillator 1 3 2 4 ROSH ROSL Ceramic Oscillator CL0 1 Ceramic Resonator 2 Crystal Oscillator CG 3 Crystal 4 CL1 29/37 FEDL63193-04 1Semiconductor ML63193 Measuring circuit 2 *4 VIH *3 VIL INPUT OUTPUT VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH A VDDL *3 Input logic circuit to determine the specified measuring conditions. *4 Measured at the specified output pins. Measuring circuit 3 *5 INPUT A OUTPUT VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL Measuring circuit 4 VIH *5 VIL INPUT VSS OUTPUT VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH Waveform Monitoring VDDL *5 Measured at the specified input pins. 30/37 FEDL63193-04 1Semiconductor ML63193 AC Characteristics (Serial Interface, Serial Port) (1) Synchronous Communication (VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. TXC/RXC Input Fall Time tf — — — 1.0 TXC/RXC Input Rise Time tr — — — 1.0 TXC/RXC Input “L” Level Pulse Width tCWL — 0.8 — — TXC/RXC Input “H” Level Pulse Width tCWH — 0.8 — — TXC/RXC Input Cycle Time tCYC — 2.0 — — — 30.5 — TXC/RXC Output Cycle Time CPU is in operating at tCYC (O) 32.768 kHz Unit µs TXD Output Delay Time tDDR Output load capacitance 10 pF — — 0.4 RXD Input Setup Time tDS — 0.5 — — RXD Input Hold Time tDH — 0.8 — — Synchronous communication timing (“H” level = 4.0 V, “L” level = 1.0 V) tCYC VDDI TXC (PC.1)/ RXC (PC.2) VSS tr tf tCWH tCWL tDDR tDDR VDDI TXD (PC.3) VSS tDS tDH tDS VDDI RXD (PC.0) VSS 31/37 FEDL63193-04 1Semiconductor ML63193 (2) UART Communication Parameter Symbol Condition Min. Typ. Max. Transmit Baud Rate TBRT TBRT = 1/fBRT TCR = 1/fOSC TBRT – TCR TBRT TBRT + TCR Receive Baud Rate RBRT RBRT = 1/fBRT RBRT × 0.97 RBRT RBRT × 1.03 Unit s fBRT: Baud rates (1200, 2400, 4800, 9600 bps) UART communication timing (“H” level = 4.0 V, “L” level = 1.0 V) TBRT VDDI TXD (PC.3) VSS RBRT VDDI RXD (PC.0) VSS 32/37 FEDL63193-04 1Semiconductor ML63193 AC Characteristics (Serial Interface, Shift Register) (VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VDDI = 5.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. SCLK Input Fall Time tf — — — 1.0 SCLK Input Rise Time tr — — — 1.0 SCLK Input “L” Level Pulse Width tCWL — 0.8 — — SCLK Input “H” Level Pulse Width tCWH — 0.8 — — SCLK Input Cycle Time tCYC 1.8 — — — 30.5 — — 0.5 — CPU is in operating at 32.768 kHz tCYC1(O) SCLK Output Cycle Time tCYC2(O) CPU is in operating at 2 MHz VDD = VDDH = 1.8 to 3.5 V SOUT Output Delay Time tDDR CL = 10 pF — — 0.4 SIN Input Setup Time tDS — 0.5 — — SIN Input Hold Time tDH — 0.8 — — Unit µs AC characteristics timing (“H” level = 4.0 V, “L” level = 1.0 V) tCYC VDDI SCLK (PE.2) VSS tr tf tCWH tCWL tDDR tDDR VDDI SOUT (PE.1) VSS tDS tDH tDS VDDI SIN (PE.0) VSS 33/37 FEDL63193-04 1Semiconductor ML63193 APPLICATION CIRCUITS • Crystal oscillation is selected as low-speed oscillation by mask option. • RC oscillation is selected as high-speed oscillation by software. • Ports are powered from external memory power source. • CV is an IC power supply bypass capacitor. • Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12, Ch, and CG, are for reference only. LCD Crystal 32.768 kHz CG COM1-16 SEG0-63 XT0 OSC0 ROSH 5 to 25 pF 1.5 V Ch 1.0 µF XT1 OSC1 VDDH PE.3 PE.2 PE.1 PE.0 PC.3 PC.2 PC.1 PC.0 VDD Cv 1.0 µF CB1 1.0 µF Cb12 0.1 µF CB2 Cl VDDL 0.1 µF Ce VDD5 0.1 µF Cd VDD4 0.1 µF Cc VDD3 0.1 µF Cb VDD2 0.1 µF Ca VDD1 C1 C12 0.1 µF Push SW C2 Buzzer RESET TST1 TST2 MD MDB PB.3 PB.2 PB.1 PB.0 ML63193 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 VDDI VDD VSS Note: VDDI is the power supply pin for the input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup 34/37 FEDL63193-04 1Semiconductor ML63193 • Crystal oscillation is selected as low-speed oscillation by mask option. • Ceramic oscillation is selected as high-speed oscillation by software. • Ports, external memory, and IC share their power supply. • Cv is an IC power supply bypass capacitor. • Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG, CL0, and CL1 are for reference only. LCD Crystal 32.768 kHz CG 5 to 25 pF VDD COM1-16 CL0 30 pF SEG0-63 XT0 OSC0 XT1 VDDH OSC1 VDD PE.3 PE.2 PE.1 PE.0 PC.3 PC.2 PC.1 PC.0 CL1 30 pF 5.0 V 0.1 µF Cv Cl Open 0.1 µF Ce 0.1 µF Cd 0.1 µF Cc 0.1 µF Cv 0.1 µF Ca 0.1 µF CB1 CB2 VDDL VDD5 VDD4 VDD3 VDD2 VDD1 C1 C12 0.1 µF Push SW Buzzer C2 RESET TST1 TST2 MD Ceramic Resonator (Example: 1 MHz) ML63193 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 MDB VSS Note: VDDI VDD VDDI is the power supply pin for the input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup 35/37 FEDL63193-04 1Semiconductor ML63193 PACKAGE DIMENSIONS (Unit : mm) LQFP144-P-2020-0.50-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 1.37 TYP. 5/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 36/37 FEDL63193-04 1Semiconductor ML63193 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 37/37