FEDL70511LA-03
1Semiconductor
ML70511LA
This version:
Dec. 2001
Previous version: Jun. 2001
Bluetooth Baseband Controller IC
GENERAL DESCRIPTION
The ML70511LA is a CMOS digital IC for use in 2.4 GHz band Bluetooth™ systems. This IC incorporates the
ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of
applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth Protocol
Stack Software, data/voice communications are possible while maintaining interconnectivity with other Bluetooth
systems.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Compliant to Bluetooth Specification (Ver. 1.1)
The ARM7TDMI is installed as the CPU (operation at a maximum of 32 MHz in this LSI)
1-Ch, 16-bit auto-reload timer
3-Ch, 18-bit auto-reload timer
Interrupt controller (17 causes)
Built-in 8 kbyte, 4-Way Unified Cache
Built-in 32 kbyte
Up to a total of 2 Mbyte of SRAM, ROM, and Flash ROM can be connected to the external memory bus.
Selectable master clock (12/13/16 MHz).
PCM-CVSD transcoder is installed.
Installed interfaces:
- UART(*) interface (Up to 921.6 Kbps)
- USB(*) interface (conforms to USB1.1)
- UART/ synchronous serial port interface
- General-purpose I/O interface (programmable interrupts)
- PCM interface (PCMLinear/A-law/µ-law can be selected)
- JTAG interface
(*)
This mark indicates interfaces that support the HCI command.
• Built-in Regulator and Power-on-Reset
• Single power supply voltage: 3.0 to 3.6 V
• Package: 144-pin BGA (P-LFBGA144-1111-0.80)
(Dimensions: 11 mm × 11 mm × 1.5 mm; pin pitch: 0.8 mm)
ARM and ARM7TDMI are registered trademarks of ARM Ltd., UK.
Thumb is trademark of ARM Ltd., UK.
BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry.
The information contained herein can change without notice owing to the product being under development.
1/26
FEDL70511LA-03
1Semiconductor
ML70511LA
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Rating
Unit
VDD
—
–0.3 to +4.5
V
Input voltage
VI
—
–0.3 to +4.5
V
Allowable power dissipation
Pd
—
1.35
W
Storage temperature
Tstg
—
–55 to 150
°C
Power supply voltage
RECOMMENDED OPERATING CONDITIONS
Symbol
Conditions
Min.
Typ.
Max.
Unit
Power supply voltage
Parameter
VDD
—
3.0
3.3
3.6
V
“H” level input voltage
Vih
—
2.2
—
3.6
V
“L” level input voltage
Vil
—
0
—
0.8
V
Operating temperature
Ta
—
–40
—
85
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics (1) (Except USB port)
(VDD = 3.3 V ±0.3 V, Ta = –40 to 85°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
“H” level output voltage
Parameter
Voh
Ioh = –2 mA
2.4
—
—
V
“L” level output voltage
Vol
Iol = 2mA
—
—
0.4
V
Input leak current
Ii
Vi = GND to 3.6 V
–10
—
10
µA
Output leak current
Power supply current (during
operation)
Power supply current (during
stand-by)
Io
Vo = GND to VDD
During 32 MHz
operation
–10
—
10
µA
0
50
70
mA
CLK Stopped
—
200
800
µA
Iddo
Idds
DC Characteristics (2) USB port (D+, D–)
(VDD = 3.3 V ±0.3 V, Ta = –40 to 85°C)
Parameter
Differential input sensitivity
Differential common mode
range
Single ended receiver threshold
“H” output voltage
“L” output voltage
Output leakage current
Symbol
VDI
VCM
Conditions
{(D+) – (D–)}
Min.
0.2
Typ.
—
Max.
—
Unit
V
Includes VDI
0.8
—
2.5
V
VSE
VOH
VOL
ILO
—
15 KΩ to GND
1.5 KΩ to 3.6 V
0 V < VIN < VDD
0.8
2.8
—
–10
—
—
—
—
2.0
3.6
0.3
+10
V
V
V
µA
2/26
FEDL70511LA-03
1Semiconductor
ML70511LA
PIN PLACEMENT
1
2
3
NC
PLL_PS
PLL
LOCK
4
5
6
GND
MRE
PLL_LE
RXC
TEST_L
MWE
TEST TEST_L TEST_L
RESET
BBWSEL
PU
_OUT
RX_
POW
TXD
PLL_
POW
MCS0
MCS1
VDD
PLL_
OFF
PLL_
DATA
TX_
POW
TEST_H RESET
D+
PLL_
CLK
GND
RSSI_
CLK
LVDD
RXD
TXC_IN
GND
RSSI
VDD
PCM
OUT
CIO15
TDO
PCM
SYNC
CIO12
GND
CIO9
GND
7
8
D-
TEST_L
9
10
11
12
SCLK
FSEL0 TXCSEL AGND1 TEST_L
13
NC
A
SCLK
SEL
GND
TMS
TCK
GND
TRST
VDD
SCLK
B
GND
TEST_L
VTM
TEST_L AVDD1
C
TEST_L TEST_L
SCLK REMAP0 XCLK
FSEL1
D
REGVBG AGND0 REGVDD AVDD0
E
GND
REMAP1REGOUT
REG
GND
F
MBS0
MOE1
GND
MOE0
TDI
MBS1
VDD
MD0
GND
CIO11
CIO14
MD1
MD4
VDD
MD2
CIO13
CIO10
CIO7
MA15
MA11
VDD
MA6
MA3
MD13
MD7
MD3
MD5
CIO6
CIO8
CIO2
CIO0
MA17
GND
MA9
MA7
MA0
VDD
MD9
MD6
MD8
CIO4
CIO5
MA19
MA16
MA14
MA12
MA10
GND
MA5
MA2
MD14
MD11
MD10
NC
CIO3
CIO1
MA18
GND
MA13
MA8
MA4
MA1
MD15
MD12
GND
NC
PCMCLK PCMIN
G
H
J
K
L
M
N
TOP VIEW
3/26
FEDL70511LA-03
1Semiconductor
ML70511LA
PIN DESCRIPTIONS
RF I/F
Direction
Internal
[*0]
Pull Up/Down
Initial
Value
Pin
Placement
TXD
O
—
L
C2
Transmit data output
(To ML7050LA Pin# A8)
RXD
I
—
—
F1
Receive data input
(To ML7050LA Pin# H5)
PLL_DATA
O
—
L
D2
PLL setting data output
(To ML7050LA Pin# H3)
PLL_CLK
O
—
L
E1
PLL_LE
O
—
L
B1
PLL_OFF
O
—
L
D1
PLL Open-loop/Closed-loop control signal
output (To ML7050LA Pin# G8)
PLL_POW
O
—
H
C3
Local transmit circuit power control signal
output (To ML7050LA Pin# A7)
TX_POW
O
—
H
D3
RX_POW
O
—
H
C1
RSSI
I
Pull down
—
F4
Receive field strength data input
RSSI_CLK
O
—
H
E3
RSSI transfer clock
PLL_PS
O
—
L
A2
PLL power control signal output
PLLLOCK
I
Pull down
—
A3
PLL lock signal input
RXC
O
—
L
B2
Pin Name
Description
PLL setting clock output
(To ML7050LA Pin# G3)
PLL setting load enable output
(To ML7050LA Pin# H4)
Transmit power control signal output
(To ML7050LA Pin# B6)
Receive power control signal output
(To ML7050LA Pin# B3)
Bluetooth receive clock output (1 MHz)
Bluetooth transmit clock input (1 MHz)
TXC_IN
I
Pull down
—
F2
When the transmit clock is used by a clock
(RXC) that is generated from the receive
data, set TXCSEL(Pin# A10) to H and
connect to RXC(Pin# B2).
Bluetooth transmit clock setting pin
TXCSEL
I
Pull down
—
A10
L: Select 1 MHz divided by internal PLL.
H: Select TXC_IN input signal.
[*0]
“I” = Input, “O” = Output, “I/O” = Input/Output, “Oc” = Open Collector
4/26
FEDL70511LA-03
1Semiconductor
ML70511LA
CLK and Configuration
Internal
Pull Up/Down
Initial
Value
Pin
Placement
I
—
—
D13
XCLK
I
—
—
D11
SCLKSEL
I
Pull down
—
B10
SCLKFSEL0
I
Pull down
—
A9
SCLKFSEL1
I
Pull down
—
D9
RESET
I
—
—
D5
Hardware reset pin (Reset = L)
RESET_OUT
O
—
—
B9
BBWSEL
I
Pull down
—
B8
REMAP0
I
—
—
D10
REMAP1
I
—
—
F11
Hardware reset pin (Reset = L), Output
BANK0 region bit width select pin
L: 8-bit
H: 16-bit
REMAP select pin during boot up
REMAP[1:0] = “00” Forbidden
“01” Forbidden
“10” External MCS1 device
“11” External MCS0 device
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Pin Name
Direction
SCLK
Description
Master clock (12, 13 or 16 MHz) input pin
(Power level: CMOS level)
User clock input pin
System clock select pin
L: Select CLK divided by internal PLL
H: Select XCLK input signal
Master clock select pin
SCLKFSEL[1:0] = “00” : 12 MHz
“01” : 13 MHz
“10” : 16 MHz
“11” : Forbidden
Memory I/F
Pin Name
Direction
MA[19:0]
O
—
L
[*1]
External address bus
MD[15:0]
I/O
Pull up
—
[*2]
External data bus
[*1]
[*2]
Description
MWE
O
—
H
B4
External write enable signal output
MRE
O
—
H
A5
External read enable signal output
MCS0
O
—
H
C4
External space 0 chip select
MCS1
O
—
H
C5
MBS0
O
—
H
G10
External lower byte select
MBS1
O
—
H
H10
External upper byte select
MOE0
O
—
H
G13
External MCS0 device output enable
(MCS0 and MRE OR output)
MOE1
O
—
H
G11
External MCS1 device output enable
(MCS1 and MRE OR output)
MA19: M3; MA18: N4; MA17: L5;
MA13: N6; MA12: M6; MA11: K6;
MA6: K8;
MA5: M9; MA4: N8;
External space 1 chip select
MA16: M4; MA15: K5; MA14: M5
MA10: M7; MA9: L7;
MA8: N7;
MA3: K9;
MA2: M10; MA1: N9;
MA7: L8
MA0: L9
MD15: N10; MD14: M11; MD13: K10; MD12: N11; MD11: M12; MD10: M13
MD9: L11; MD8: L13; MD7: K11; MD6: L12; MD5: K13; MD4: J11; MD3: K12;
MD2: J13; MD1: J10; MD0: H12
5/26
FEDL70511LA-03
1Semiconductor
ML70511LA
USB I/F
Internal
Pull Up/Down
Initial
Value
Pin
Placement
I/O
—
Z
D6
USB data
D–
I/O
—
Z
A7
USB data
VBUS
(GPIO0)
I
—
—
L4
USB detection pin
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Pin Name
Direction
D+
Description
UART I/F
Pin Name
Direction
Description
SOUT
O
—
H
H1
ACE transmit serial data
(Pin shared with GPIO15)
SIN
I
—
—
J4
ACE receive serial data
(Pin shared with GPIO14)
DCD
I
—
—
K2
Data carrier detection
(Pin shared with GPIO13)
RTS
O
—
H
J1
ACE transmit data ready
(Pin shared with GPIO12)
CTS
I
—
—
J3
ACE transmit ready
(Pin shared with GPIO11)
DSR
I
—
—
K3
Receive data ready
(Pin shared with GPIO10)
DTR
O
—
H
K1
Receive ready
(Pin shared with GPIO9)
RI
I
—
—
L2
Ring indicator
(Pin shared with GPIO8)
Internal
Pull Up/Down
Initial
Value
Pin
Placement
SIO I/F
Pin Name
Direction
STXD
O
—
H
K4
Serial data output
(Pin shared with GPIO7)
SRXD
I
—
—
L1
Serial data input
(Pin shared with GPIO6)
STDCLK
I/O
—
—
M2
Clock for serial data output (Pin shared
with GPIO5) During initialization: input
SRDCLK
I/O
—
—
M1
Clock for serial data input (Pin shared with
GPIO4) During initialization: input
6/26
Description
FEDL70511LA-03
1Semiconductor
ML70511LA
µPLAT_SIO I/F
Internal
Initial
Value
Pin
Placement
—
H
N2
Serial data output (Pin shared with GPIO3)
—
—
L3
Serial data input (Pin shared with GPIO2)
Pull Up/Down
Initial
Value
Pin
Placement
—
—
[*3]
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Pull down
—
H4
Pin Name
Direction
UTXD
O
URXD
I
Internal
Pull Up/Down
Description
GPIO I/F
Pin Name
Direction
GPIO[15:0]
I/O
Description
Parallel I/O data
During initialization: input
JTAG I/F
Pin Name
Direction
TDI
I
TDO
O
—
L
H2
Serial data output
TRST
I
Pull down
—
C13
Reset pin
Description
Serial data input
TMS
I
Pull down
—
B12
Mode setting pin
TCK
I
Pull down
—
B13
Serial data clock
Internal
Initial
Value
Pin
Placement
PCM I/F
Pin Name
Direction
PCMOUT
O
—
L
G2
PCM data output
PCMIN
I
Pull down
—
G4
PCM data input
Pull Up/Down
Description
PCM sync signal (8 kHz),
PCMSYNC
I/O
Pull down
—
H3
During initialization: input
(can be switched by an internal register)
PCM clock (64 kHz/128 kHz)
PCMCLK
I/O
Pull down
—
G3
During initialization: input
(can be switched by an internal register)
[*3]
CIO15:
CIO14:
CIO13:
CIO12:
CIO11:
CIO10:
CIO9:
CIO8:
CIO7:
CIO6:
CIO5:
CIO4:
CIO3:
CIO2:
CIO1:
CIO0:
H1
J4
K2
J1
J3
K3
K1
L2
K4
L1
M2
M1
N2
L3
N3
L4
GPIO15/SOUT (UART I/F)
GPIO14/SIN (UART I/F)
GPIO13/DCD (UART I/F)
GPIO12/RTS (UART I/F)
GPIO11/CTS (UART I/F)
GPIO10/DSR (UART I/F)
GPIO9/DTR (UART I/F)
GPIO8/RI (UART I/F)
GPIO7/STXD (SIO I/F)
GPIO6/SRXD (SIO I/F)
GPIO5/STXDCLK (SIIO I/F)
GPIO4/SRXDCLK (SIO I/F)
GPIO3/UTXD (µPLAT_SIO I/F)
GPIO2/URXD (µPLAT_SIO I/F)
GPIO1
GPIO0/VBUS (USB I/F)
7/26
FEDL70511LA-03
1Semiconductor
ML70511LA
TEST I/F
Internal
Pull Up/Down
Initial
Value
Pin
Placement
I
—
—
[*4]
Test pin (input)
TEST_H
I
—
—
D4
Test pin (input)
TEST_PU
Oc
—
L
B5
Test monitor pin
VTM
I
—
—
C9
Test pin
NC
—
—
—
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Pin Name
Direction
TEST_L
A1, A13,
N1, N13
Description
No Connection
Power, GND
Pin Name
Direction
VDD
—
—
—
[*5]
I/O power pin 3.3 V ±0.3 V
LVDD
—
—
—
E4
I/O power pin 3.3 V ±0.3 V (Same voltage
to the VDD for ML7050LA)
GND
—
—
—
[*6]
Digital block ground pin
AVDD0
—
—
—
E13
Analog block power pin 2.5 V ±0.25 V
Description
AVDD1
—
—
—
C11
(Connect to REGOUT pin: F12)
AGND0
—
—
—
E11
Analog block ground pin
AGND1
—
—
—
A11
(Connect to REGGND pin: F13)
REGVDD
—
—
—
E12
Regulator power pin (3.0 to 3.6 V)
REGGND
—
—
—
F13
Regulator ground pin
REGOUT
—
—
—
F12
Regulator output
REGVBG
—
—
—
E10
Regulator reference voltage tuning
[*4]
[*5]
[*6]
TEST_L (TEST5): A8
TEST_L (TEST4): D8
TEST_L (TEST3): C8
TEST_L (TEST2): B7
TEST_L (TEST1): D7
TEST_L (TEST0): B6
TEST_L (PLLSEL): C10
TSET_L (PLLEN): A12
TSET_L (SVCO1): B3
C6, G1, K7, J12, H11, D12, L10
B11, C7, A6, A4, E2, F3, J2, N5, L6, M8, N12, H13, G12, F10, C12
8/26
FEDL70511LA-03
1Semiconductor
ML70511LA
REFERENCE FOR VOLTAGE SUPPLY CIRCUIT
ML70511LA
REGVDD
REGVBG
REGOUT
10
0.018
1
REGGND
AVDD0
0.1
AGND0
AVDD1
0.1
AGND1
VDD
GND
VDD
10
10
0.1
0.1
Capacitors shold locate close to LSI pins.
Unit: µF
GND
Feed lines should be separated
from LSI pins.
Example for ML70511LA voltage supply circuit
The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric
Industry Co., Ltd. for detailed information.
9/26
10/26
XMC(BIU)
Cache/
Bus I/F
APB Ctl
ARM7
TDMI
TIC
System
Control
UART
I/F
SIO
I/F
PIO
I/F
USB
USB I/F
PCM/
CVSD
BT-BB
Core
PCM Codec
I/F
CTL/
WDT
I/F
I/F
I/F
PIO I/F
I/F
AMBA APB
Arbiter
AMBA AHB
SIO
SIO I/F
I/F
I/F
I/F
IRC
Timer
UART I/F
I/F
3ch
TIMER
APB Ctl
I/F
I/F
32 kB
RAM
SIO I/F
Default
Slave
AMBA APB
8 Mbit
SRAM
16
RFLSI
Clock
CLK
GEN
8 Mbit
Flash
ROM
FEDL70511LA-03
1Semiconductor
ML70511LA
BLOCK DIAGRAM
ML70511LA
FEDL70511LA-03
1Semiconductor
ML70511LA
DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block
• Generates from the SCLK (12/13/16 MHz) clock that is supplied to each block
• STOP/HALT function
• External clock selection function
CTL/WDT Block
•
•
•
•
•
•
•
•
Control of the frequency division function of the internal main clock
Control of clock supplied to each peripheral
Control of reset of each peripheral
STOP/HALT control
External clock selection control
CIO switching function
Watchdog timer function (interrupt/reset)
3 types of count stop functions
Timer Block
•
•
•
•
3 channels
18 bit timer counter for each channel
Iterrupt at counter overflow
Independent mode for each channel (one shot/interval/free run)
Baseband Core Block
RF LSI
Tx SCO Buffer
Audio
I/F
Tx ACL Buffer
Security
APB
TXD
Packet
Composer
Codec
Timing
FHCNT
RF
CNT
CNT
ARM
I/F
Rx SCO Buffer
Packet
Decomposer
Rx ACL Buffer
11/26
RXD
FEDL70511LA-03
1Semiconductor
ML70511LA
• RF Controller
- RF power supply control (PLL, TX, RX)
- Local PLL frequency division ratio setting
- Receive clock regeneration function
- Synchronization detection (synchronizing within the permissable error limit of SyncWord)
- Receive clock re-timing function
• FH Controller hopping
- Sequence control
- Frequency hopping selection function
- CRC computation's initial value selection function
• Timing Generator
- Bluetooth clock generation
- Operation interrupts depend on mode (slot, scan, sniff, hold, park)
- Sync detection timing generation (sync window ±10 µs)
- PLL setting timing generation
- Transmit/Receive timing generation
- Multi-master timing management function
• Packet Composer
- Access code generation (SyncWord generation, appending PR*TRAILER)
- Packet header generation (HEC generation, scrambling, FEC encoding)
- Payload generation (CRC generation, encryption, scrambling, FEC encoding)
- Packet synthesis
• Packet Decomposer
- Packet decomposition (separating the packet header and the payload)
- Packet header processing (FEC decoding, descrambling, HEC error detection, header information
separation)
- Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload
separation)
• Security
- Various key generation functions (initialization, link key, encryption key)
- Certification function
- Encryption function
12/26
FEDL70511LA-03
1Semiconductor
ML70511LA
USB Block
• Conforms to USB standard Ver. 1.1.
• Supports 12 Mbps transfer
• Supports 4 data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous
transfer)
• Built-in USB transceiver circuit
• 5 or 6 built-in end points, and built-in FIFO for data storage
• 8-, 16-, 32-bit read/write is possible for the FIFOs of EP0 to EP5 (with byte control)
UART Block
•
•
•
•
•
•
•
•
•
•
Full-duplex buffering method
All status reporting function
Built-in 64-byte transmit/receive FIFO
Modem control based on CTS, DCD, and DSR
Programmable serial interface
5-, 6-, 7-, 8-bit characters
Generation and verification of odd parity, even parity, or no parity
1, 1.5, or 2 stop bits
Programmable Baud Rate Generator (1200 bps to 921.6 kbps)
Error servicing for parity, overrun, and framing errors
13/26
FEDL70511LA-03
1Semiconductor
ML70511LA
SIO Block
• UART/Synchronous type serial port interface
• UART Mode:
- Data length: can be selected as 7 or 8 bits
- Supports odd parity, even parity, or no parity
- Error servicing for parity, overrun, and framing errors
- Supports 1 or 2 stop bits
- Full-duplex communication is possible
• Clock synchronization mode:
- Data length: can be selected as 7 or 8 bits
- Error servicing for overrun errors
- Full-duplex communication is possible
µPLAT-SIO Block
•
•
•
•
•
•
•
Start-stop synchronization type serial port interface
Built-in dedicated baud rate generator
Data length of 7 or 8 bits can be selected
1 or 2 stop bits can be selected.
Supports odd or even parity
Error servicing for parity, overrun, and framing errors
Full-duplex communication is possible
PCM-CVSD Transcoder Block
• Application side I/O:
- PCM Codec
- APB-Bus (USB)
• Application-side format:
- PCM linear (8, 16 bits/sample, 64 kHz sampling frequency)/A-law/µ-law
• Bluetooth-side format:
- CVSD/A-law/µ-law
• All combinations of the above conversions are supported
• PCMSYMC/PCMCLK I/O can be switched (in the input state after initialization)
GPIO Block
•
•
•
•
•
All 16 bits
Input/Output selection possible for each bit
Interrupts can be used for all bits
Interrupt masks and interrupt modes can be set for all bits
In the input state immediately after a reset
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ML70511LA
APPLICATION NOTES
Operation During Boot Up
• Remapping during boot up is performed according to external pins REMAP[1:0].
REMAP1
L
L
H
H
REMAP0
L
H
L
H
:
:
:
:
Forbidden
Forbidden
Devices connected to external MCS1
Devices connected to external MCS0
• Bit width that corresponds to BANK0 during boot up is set according to external pin BBWSEL.
BBWSEL = L :
BBWSEL = H :
8-bit
16-bit
Clock Selection
• The CPU clock supply source is selected according to external pin SCLKSEL.
SCLKSEL = L :
SCLKSEL = H :
Use 32/16/8/4 MHz clock that was divided down from the internal PLL output of 192
MHz that was generated from external pin SCLK. (Initial value is 32 MHz.)
Use external pin XCLK.
Note: The clock supply source can also be set by the CLKCNT register in the CTL/WDT block.
• Bluetooth transmission clock is selected according to external pin TXCSEL.
TXCSEL = L :
TXCSEL = H :
Use 1 MHz clock that was divided down from the internal PLL output (192 MHz).
Use external pin TXC_IN.
Note: This clock can also be set by the CLKCNT register in the CTL/WDT block.
• SCLK selection (12/13/16 MHz).
SCLKFSEL[1:0] = “00” : 12 MHz
“01” : 13 MHz
“10” : 16 MHz
“11” : Forbidden
HCI Transport Selection
• HCI is selected (USB/UART) according to the logical value of GPIO0 at initial powerup of ML70511LA.
GPIO0 = L
GPIO0 = H
:
:
UART is used as HCI.
USB is used as HCI.
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ML70511LA
USB Peripheral Circuit
• Please contact Oki Electric Industry Co., Ltd. when using USB.
Setting the UART Baud Rate
• Use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands to set the UART baud
rate.
Available baud rate settings:
1200/2400/4800/7200/9600/19.2K/38.4K/56K/57.6K/115.2K/230.4K/345.6K/460.8K/921.6K
(Initial value is 115.2 kbps.)
Setting the PCM-CVSD Transcoder
• Please use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands in HCI to set the
PCM-CVSD transcoder parameters.
• It is possible to set the following parameters using the VCCTL command:
- PCMSYNC/PCMCLK mode (in the input state after initialization)
- Mute reception (initial setting: OFF)
- Mute transmission (initial setting: OFF)
- Air coding
CVSD (initial setting)/µ-law/A-law
- Interface coding
Linear (initial setting)/µ-law/A-law
- PCM format (data width of one PCM Linear sample)
8-bit (initial setting)/14-bit/16-bit
- Serial interface format
Short frame (initial setting)/long frame
- Application interface mode
PCM Codec I/F (initial setting)/APB I/F
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ML70511LA
External Memory
• ML70511LA specifications for the devices that are connected to MCS0 and MCS1 are explained below.
• When the device is connected to MCS0:
- 1 memory bank
- Bus width: 8 or 16 bits
- Byte access control: MBS*/MWE
- Supported devices:
Normal SRAM, Flash Memory, Page mode Flash memory
Bus timing to the device connected to MCS0
MRE
MWE
XA
MCS0
MBS*
XD_I
[*1]
(read)
XD_O
(write)
[*1]
[*2]
[*1]
1 or 2
clocks
[*2]
1 or 2 clocks
Access time:
3, 4, 5, 6, 7, 8 clock cycles (including 1 clock cycle for set-up)
6, 8, 10, 12, 14, 16 clock cycles (including 2 clock cycles for set-up)
Data OFF time:
1, 2, 3, 4 clock cycles
Note: Oki software settings:
- Insert the maximum wait immediately after reset.
- Page mode: OFF
- During operation (32 MHz operation),
Access time: 3 clock cycles
Data OFF time: 1 clock cycle
Note: A device with an access time of 120 nsec or less is recommended.
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1 clock fixed
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ML70511LA
• When the device is connected to MCS1:
- 1 memory bank
- Bus width: 8-bit or 16-bit
- Byte access control: MBS*/MWE
Bus timing to the device connected to MCS1 (IOWRTYPE = 0)
MRE
MWE
XA
MCS1
MBS*
[*3]
XD_I
[*1]
(read)
[*1]
XD_O
(write)
[*3]
[*2]
1 clock fixed
Bus timing to the device connected to MCS1 (IOWRTYPE = 1)
MRE
MWE
XA
MCSn1
MBS*
(read)
XD_O
(write)
[*1]
[*3]
XD_I
[*4]
[*1]
[*3]
[*2]
1 clock fixed
[*1]
[*2]
[*3]
[*4]
Access time:
2, 4, 8, 16, 32 clock cycles (including 1 clock cycle for set-up)
Data OFF time:
1, 2, 3, 4 clock cycles
Address set-up time:
1, 2, 3, 4 clock cycles
Write data set-up time:
0 clock cycles (IOWRTYPE = 0)
0, 1, 2, 3 clock cycles (IOWRTYPE = 1)
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ML70511LA
Relation between address set-up time and write data set-up time (when IOWRTYPE = 1)
- Address set-up time:
1 clock cycle (write data set-up: 0 clock cycles)
2 clock cycles (write data set-up: 1 clock cycle)
3 clock cycles (write data set-up: 2 clock cycles)
4 clock cycles (write data set-up: 3 clock cycles)
Note:
Oki software settings:
- Insert the maximum wait immediately after reset.
- IOWRTYPE = 0
- During operation (32 MHz operation),
Access time: 2 clock cycles
Data OFF time: 1 clock cycle
Address set-up time: 1 clock cycle
Note: A device with an access time of 120 nsec or less is recommended.
• Miscellaneous
- MA0 is not used with devices that have a 16-bit data bus.
Connect MA1 to device A0. (MA0 is Open.)
- Connect MA0 to device A0 for devices that have an 8-bit data bus.
- MOE0 is the AND signal for MCS0 and MRE.
Perform an open process when this is not in use.
- MOE1 is the AND signal for MCS1 and MRE.
Perform an open process when this is not in use.
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ML70511LA
Process when interface pins are unused
• The following tables show the processes that are performed when interface pins are not used.
RF I/F
Pin Name
Process When Pin Not Used
PLL_DATA
Open
PLL_CLK
Open
PLL_LE
Open
PLL_OFF
Open
PLL_POW
Open
TX_POW
Open
RX_POW
Open
RSSI
Pull down or GND
RSSI_CLK
Open
PLL_PS
Open
PLLLOCK
Pull down or GND
RXC
Open
TXC_IN
Pull down or GND
TXCSEL
Pull down or GND
Comments
GPIO
Pin Name
Process When Pin Not Used
GPIO0
Pull up or VDD
GPIO1
Pull down or GND
GPIO2
Pull down or GND
GPIO3
Pull up or VDD
GPIO4
Pull down or GND
GPIO5
Pull down or GND
GPIO6
Pull up or VDD
GPIO7
Pull up or VDD
GPIO8
Pull up or VDD
GPIO9
Pull up or VDD
GPIO10
Pull down or GND
GPIO11
Pull up or VDD
GPIO12
Pull up or VDD
GPIO13
Pull down or GND
GPIO14
Pull up or VDD
GPIO15
Pull up or VDD
Comments
This process is not applicable when used as
VBUS (USB I/F).
This process is not applicable when used as
UTXD (µPLAT SIO I/F).
This process is not applicable when used as
STXD (SIO I/F).
This process is not applicable when used as
DTR (UART I/F).
This process is not applicable when used as
RTS (UART I/F).
This process is not applicable when used as
SOUT (UART I/F).
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ML70511LA
Memory I/F
Pin Name
MA[19:0]
Process When Pin Not Used
Comments
Open
When connected
For 16-bit devices:
• Open MA0.
• Connect from MA1 in order from A0 of the
connected device.
For 8-bit devices:
• Connect to each corresponding address.
MD[15:0]
Open
MWE
Open
MRE
Open
MCS0
Open
MCS1
Open
MBS0
Open
MBS1
Open
MOE0
Open
MOE1
Open
Only use when connecting to a device that has
only one, but not both of MCS* or MRE.
Process When Pin Not Used
Comments
USB I/F
Pin Name
D+
Open
D–
Open
VBUS
(GPIO0)
When using UART: Pull down or GND
When using USB: Pull up or VDD
This process is not applicable when used as
GPIO.
UART I/F
Pin Name
Process When Pin Not Used
SOUT
(GPIO15)
Open
SIN
(GPIO14)
Pull up or VDD
DCD
(GPIO13)
Pull down or GND
RTS
(GPIO12)
Open
CTS
(GPIO11)
Pull down or GND
DSR
(GPIO10)
Comments
This process is not applicable when used as
GPIO.
This process is not applicable when used as
GPIO.
Pull down or GND
DTR
(GPIO9)
Open
RI
(GPIO8)
Pull up or VDD
This process is not applicable when used as
GPIO.
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ML70511LA
SIO I/F
Pin Name
Process When Pin Not Used
STXD
(GPIO7)
Open
SRXD
(GPIO6)
Pull up or VDD
STDCLK
(GPIO5)
Pull down or GND
SRDCLK
(GPIO4)
Pull down or GND
Comments
This process is not applicable when used as
GPIO.
µPLAT_SIO I/F
Pin Name
Process When Pin Not Used
UTXD
(GPIO3)
Open
URXD
(GPIO2)
Pull down or GND
Comments
This process is not applicable when used as
GPIO.
JTAG I/F
Pin Name
Process When Pin Not Used
TDI
Open
TDO
Open
TRST
Open
TMS
Open
TCK
Open
Comments
PCM I/F
Pin Name
Process When Pin Not Used
PCMOUT
Open
PCMIN
Open
PCMSYNC
Open
PCMCLK
Open
Comments
Processes of Other Pins
TEST I/F, etc.
Pin Name
Process When Pin Not Used
TEST_L
GND
TEST_H
VDD
TEST_PU
Open
VTM
Open
RESET
Pull up or VDD
RESET_OUT
Open
NC
Open
Comments
• The unused pin configurations are subject to change according to the specific application.
Please contact Oki Electric Industry Co., Ltd. for detailed board layout information.
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ML70511LA
ABOUT BLUETOOTH SOFTWARE
• At Oki Electric Industry Co., Ltd., we have made available as Pack 1 the software protocol stack of the lower
layer up to HCI that conforms to the Bluetooth Specification Ver. 1.1 for external Flash memory.
Pack 1 contents: Baseband Controller, LMP, HCI.
• Please contact Oki Electric Industry about upper software protocol stack above HCI.
• Please contact Oki Electric Industry Co., Ltd. for more information regarding software contents, pricing, etc.
VENDOR SPECIFIC COMMANDS
• Parameters can be set with the Pack 1 software by using the following Vendor Specific Commands.
• Please contact Oki Electric Industry Co., Ltd. for more information.
(Command example) HCI_VS_Set_LC_Parameters:
Sets the link control information.
The following table shows the link control information that can be set.
Link Control Information
Comments
0: µ-law, 1: A-law, 2: Linear
PCM for SCO Link
UART baud rate
0:
9600 bps
1:
19.2 kbps
2:
38.4 kbps
3:
56 kbps
4:
115.2 kbps
5:
230.4 kbps
6:
345.6 kbps
7:
57.6 kbps
8:
460.8 kbps
9:
921.6 kbps
Unit: 625 µsec
Poling rate
12: 12 MHz
Master clock setting for ML7050LA
13: 13 MHz
16: 16 MHz
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ML70511LA
SYSTEM DEVELOPMENT KIT (BT-SDK)
• At Oki Electric Industry Co., Ltd., we have made available the System Development Kit (BT-SDK) for the
following objectives:
- Software development of the upper Bluetooth layer
- Overall system software
- Device development with embedded ML7050LA or ML70511LA
Please contact Oki Electric Industry Co., Ltd. for more information regarding System Development Kit contents,
pricing, etc.
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ML70511LA
PACKAGE DIMENSIONS
(Unit: mm)
P-LFBGA144-1111-0.80
5
Package material
Ball material
Package weight (g)
Rev. No./Last Revised
Epoxy resin
Sn/Pb
0.3 TYP.
1/Aug.25,1999
Caution regarding the installation of surface mounted type packages:
Surface mounted type packages are very susceptible to heat during reflow mounting and package moisture content
when in storage. Therefore, please contact your Oki Electric Industry Co., Ltd. sales representative when considering
reflow experiments and let us know the product name, package name, pin count, package code, the desired mounting
conditions (reflow method, temperature, count), storage conditions, etc.
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1.
ML70511LA
NOTICE
The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting
from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical
or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by
us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics,
etc.). These products are not authorized for use in any system or application that requires special or enhanced
quality and reliability characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
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