PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
¡ Semiconductor
Pr
PEDL9040A-03
el
im
in
ThisML9040A-Axx/-Bxx
version: Oct. 2000
ar
y
Previous version: Sep. 2000
DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT
SEGMENT DRIVER
GENERAL DESCRIPTION
The ML9040A-Axx/-Bxx is a dot matrix LCD controller which is fabricated in low power CMOS
silicon gate technology. Character display on the dot matrix character type LCD can be
controlled in combination with a 4-bit or 8-bit microcontroller. This LSI consists of 16-dot
COMMON driver, 40-dot SEGMENT driver, display data RAM, character generator RAM,
character generator ROM and control circuit.
The ML9040A-Axx/-Bxx has the character generator ROM that can be programmed by custom
mask. The ML9040A-A01/-B01 is a standard version having 160 characters with lowercase (5
x 7 dots), and 32 characters with uppercase (5 x 10 dots) in this ROM.
FEATURES
• Easy interface with an 8-bit or 4-bit microcontroller.
• Dot matrix LCD controller/driver for lowercase (5 x 7 dots) or uppercase (5 x 10 dots).
• Automatic power ON reset.
• COMMON signal drivers (16) and SEGMENT signal drivers (40).
• Can control up to 80 characters when used in combination with MSM5259.
• Character generator ROM for 160 characters with lowercase (5 x 7 dots) and 32 characters with
uppercase (5 x 10 dots).
• Character patterns are programmable by character generator RAM. (Lowercase: 5 x 8 dots,
8 patterns, uppercase: 5 x 11 dots, 4 patterns).
• Built-in oscillation circuit to connect with external resistor or ceralock.
• 1/8 duty (1 line; 5 x 7 dots + cursor), 1/11 duty (1 line; 5 x 10 dots + cursor), or 1/16 duty (2
lines; 5 x 7 dots + cursor), selectable.
• Clear display even at 1/5 bias, 3.0V LCD driving voltage.
• LCD driving waveform
ML9040A-Axx: A mode
ML9040A-Bxx: B mode
• Package options:
80-pin plastic QFP(QFP80-P-1420-0.80-BK)(Product name: ML9040A-Axx/-BxxGA)
Al pad chip
(Product name: ML9040A-Axx/-BxxWA)
xx indicates code number.
01 indicates standard code number.
1/49
V1
V2
V3
V4
V5
DB4 - DB7
DB0 - DB3
E
RS
R/W
OSC1
OSC2
VDD
GND
4
4
Input/
output
buffer
8
8
Timing
generation
circuit
Busy flag
(BF)
Data
register
(DR)
Instruction
register
(IR)
7
8
8
Address
counter
(ADC)
7
Instruction
decoder
(ID)
7
8
Display data
RAM
(DD RAM)
8
Character
generator
RAM
(CG RAM)
Cursor blink
control
5
Character
generator
ROM
(CG RAM)
5
Parallel/
serial
conversion
40-bit
shift
register
16-bit
shift
register
40
40-bit
latch
16
COM1~16
DO
40 Seg- 40
ment
signal
SEG1~40
driver
16 Common
signal
driver
CP
DF
L
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
BLOCK DIAGRAM
2/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
INPUT AND OUTPUT CONFIGURATION
VDD
VDD
P
N
Applicable to pin E.
VDD
Applicable to pins R/W and RS.
VDD
P
VDD
N
VDD
P
N
P
Applicable to pins DO, CP, L, and DF.
N
Applicable to pins DB0 - DB7.
3/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
PIN CONFIGURATION (TOP VIEW)
ML9040A-Axx/-Bxx GA
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
79
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
20
45
21
44
22
43
23
42
24
41
SEG39
SEG40
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DB7
DB6
DB5
DB4
DB3
DB2
40
39
38
37
36
35
33
34
32
31
30
29
28
27
25
46
26
47
19
V1
V2
V3
V4
V5
L
CP
VDD
DF
DO
RS
R/W
E
DB0
DB1
18
OSC2
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
GND
OSC1
80-Pin Plastic QFP
4/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
PIN DESCRIPTIONS
Symbol
Description
R/W
Read/write selection input pin.
"H" : Read, and "L" : Write
RS
Register selection input pin.
"H" : Data register, and "L" : Instruction register
E
Input pin for data input/output with CPU and for instruction register activation.
DB0 - DB7
Input/output pins for data send/receive with CPU
OSC1, OSC2
Clock oscillating pins required for internal operation upon receipt of the LCD drive signal
and CPU instruction.
COM1 - COM16
LCD COMMON signal output pins.
SEG1 - SEG40
LCD SEGMENT signal output pins.
DO
Output pin to be connected to MSM5259 to expand the number of characters to be
displayed.
CP
Clock output pin used when DO pin data output shifts inside of MSM5259.
L
Clock output pin for the serially transferred data to be latched to MSM5259.
DF
The alternating current signal (Display Frequency) output pin.
VDD
Power supply pin.
GND
Ground pin.
V1, V2, V3, V4, V5
Bias voltage input pins to drive the LCD.
TEST
This is the pin for testing the IC chip.
Leave this pin open during normal use.
*This pin is available only for Al pad chip.
5/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
LCD Driving Voltage
Symbol
Condition
Rating
Unit
Applicable pin
VDD
Ta = 25°C
–0.3 to + 7.0
V
VDD, GND
V1, V2, V3
V4, V5
VDD – 8.0 to
Ta = 25°C
VDD + 0.3
V
V1, V2, V3
V4, V5
R/W, RS, E,
Input Voltage
VI
–0.3 to VDD + 0.3
Ta = 25°C
V
DB0 - DB7
OSC1
Power Dissipation
Storage Temperature
PD
—
500
mW
—
TSTG
—
–55 to + 150
°C
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Range
Unit
Applicable pin
Supply Voltage
Data Holding Voltage*1
VDD
VHOLD
—
—
4.5 to 5.5
3.0 to 5.5
V
V
VDD, GND
VDD, GND
LCD Driving Voltage*2
VLCD
1/4 bias, VDD–V5*3
3.0 to 6.0
V
*4
3.0 to 6.0
V
Operating Temperature
Top
–20 to + 75
°C
1/5 bias, VDD–V5
—
VDD, V5
—
*1 Voltage to assure Rf oscillation and register data retention.
*2 Voltage between VDD and V5.
*3 Voltages applicable to V1, V2, V3 and V4 are as follows.
V1 = VDD – 1/4 (VDD – V5)
V2 = V3 = VDD – 1/2 (VDD - V5)
V4 = VDD – 3/4 (VDD – V5)
*4 V1 = VDD – 1/5 (VDD – V5)
V2 = VDD – 2/5 (VDD – V5)
V3 = VDD – 3/5 (VDD – V5)
V4 = VDD – 4/5 (VDD – V5)
6/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Symbol
Condition
"H" Input Voltage
VIH1
—
"L" Input Voltage
VIL1
—
"H" Input Voltage
VIH2
—
"L" Input Voltage
VIL2
—
"H" Output Voltage
VOH1
"L" Output Voltage
VOL1
"H" Output Voltage
Typ.
Max.
Unit
2.2
—
VDD
V
RS, E, DB0 - DB7
–0.3
—
0.6
V
DB0 - DB7, RS, E, R/W
VDD–1.0
—
VDD
V
OSC1, R/W
–0.3
—
1.0
V
OSC1
IO = –0.205mA
2.4
—
—
V
IO = 1.2mA
—
—
0.4
V
VOH2
IO = –40mA
0.9VDD
—
—
V
DO, CP, L,
"L" Output Voltage
VOL2
IO = 40mA
—
—
0.1VDD
V
DF, OSC2
Driver ON Resistor
RCOM
IO = ±50mA, VLCD = 4V
—
—
20
kW
COM1 - COM16
IO = ±50mA, VLCD = 4V
—
—
30
kW
SEG1 - SEG40
VI = VSS
—
—
–1
mA
VI = VDD
—
—
1
mA
–50
–125
–250
mA
(COM pins)
Driver ON Resistor
RSEG
(SEG pins)
Input Leakage Current
IIL
Min.
VDD = 5.0V
VI = VSS
Input Current
IIL2
DB0 - DB7
E
R/W, RS
VI = VDD, excluding current
flowing over pullup resistor
Applicable pin
DB0 - DB7
—
—
2
mA
—
0.35
0.6
mA
VDD
—
0.55
0.8
mA
VDD
1/5 bias
3.0
—
6.0
1/4 bias
3.0
—
6.0
and output drive MOS
VDD = 5.0V,
resistor oscillation or
external clock input via
OSC1.
Supply Current (1)
IDD1
fOSC = 270kHz.
E is in "L" level.
Other inputs are open.
Output pins are
all no load.
*1
VDD = 5.0V,
ceramic oscillation,
fOSC = 250kHz.
Supply Current (2)
IDD2
E is in "L" level.
Other pins are open.
Output pins are
all no load.
LCD Driving Bias
VLCD1
Input Voltage
VLCD2
Schmitt voltage
width
Built-in reset
detection voltage
VDD–V5
*6
*1
V
VDD, V1, V2,
V3, V4, V5
VSUM
———
0.6
0.7
0.8
V
E
VRES
———
—
—
3.0
V
VDD
7/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
AC Characteristics
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Symbol
Parameter
Rf Clock Oscillation
Frequency
Clock Input
fOSC1
fIN
Frequency
Input Clock Duty
Input Clock Rise
Time
Input Clock Fall
Time
Condition
Rf = 91kW ± 2%
*2
OSC2 is open.
Input from OSC1
Min.
Typ.
Max.
Unit
Applicable pin
190
270
350
kHz
125
250
350
kHz
OSC1
OSC1
OSC2
fDUTY
*3
45
50
55
%
OSC1
tr
*4
—
—
0.2
ms
OSC1
tf
*4
—
—
0.2
ms
OSC1
245
250
255
kHz
Rf = 510kW,
Ceramic Unit
C1 = C2 = 200 pF,
Oscillation
fOSC
Frequency
Rd = 30kW, and
Ceralock CSB250A.
OSC1
OSC2
*5
*1 Applicable to the current that flows in pin VDD when power is input as follows:
VDD = 5V, GND = 0V, V1 = 3.8V, V2 = 2.6V, V3 = 1.4V, V4 = 0.2V, and V5 = -1V.
*2
OSC1
Rf
OSC2
Rf=91kW±2%
Minimum wiring is required between
OSC1 and Rf and between OSC2 and Rf.
8/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
*3 Applied to pulse input via OSC1.
fIN
waveform
tHW
0.5VDD
tLW
0.5VDD
0.5VDD
fDUTY = tHW/ (tHW + tLW) x 100(%)
*4 Applied to pulse input via OSC1.
fIN
waveform
VDD–1.0V
VDD–1.0V
1.0V
1.0V
tf
tr
C1
*5
OSC1
Ceralock
Rf
OSC2
Rd
C2
Ceralock : CSB250A (mfd. by MURATA MFG.Co.)
Rf : 510kW ±5%
Rd : 30kW ±5%
C1 : 200pF ±10%
C2 : 200pF ±10%
Please contact us when using this circuit.
*6 Input the voltage listed in the table below to V1 - V5:
N (LCD lines)
1-line mode
2-line mode
VLCD
4
V
VDD – LCD
2
V
VDD – LCD
2
3VLCD
VDD –
4
VLCD
5
2VLCD
VDD –
5
VDD – VLCD
VDD – VLCD
Pin
V1
V2
V3
V4
V5
VDD –
VDD –
3VLCD
5
4VLCD
VDD –
5
VDD –
VLCD is an LCD driving voltage. (For "N" (number of LCD lines),
refer to the initial set of the instruction code.)
9/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Switching Characteristics
• Timing for input from the CPU
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
R/W and RS setup time
tB
140
—
—
ns
E "H" pulse width
tW
280
—
—
ns
R/W and RS hold time
tA
10
—
—
ns
E rise time
tr
—
—
100
ns
E fall time
tf
—
—
100
ns
E "L" pulse width
tL
280
—
—
ns
E cycle time
tC
667
—
—
ns
DB0 to DB7 input data setup time
tI
180
—
—
ns
DB0 to DB7 input data hold time
tH
10
—
—
ns
R/W
RS
VIL1
VIL1
VIH1
VIH1
VIL1
VIL1
tB
tA
tW
tL
E
VIL1
VIH1
VIH1
VIL1
tH
tI
DB0 - DB7
VIL1
tf
tr
VIH1
VIL1 Input data
VIH1
VIL1
tC
10/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
• Timing for output to the CPU
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
R/W and RS setup time
tB
140
—
—
ns
E "H" pulse width
tW
280
—
—
ns
R/W and RS hold time
tA
10
—
—
ns
E rise time
tr
—
—
100
ns
E fall time
tf
—
—
100
ns
E "L" pulse width
tL
280
—
—
ns
E cycle time
tC
667
—
—
ns
DB0 to DB7 data output delay time
tD
—
—
220
ns
DB0 to DB7 data output hold time
tO
20
—
—
ns
R/W
VIH2
VIH2
RS
VIH1
VIH1
VIL1
VIL1
tB
tW
tA
tL
E
VIL1
VIH1
tr
VIH1
VIL1
tO
tD
DB0-DB7
VIL1
tf
VOH1
VOL1 Output data
VOH1
VOL1
tC
11/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
• Timing for output to MSM5259
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CP "H" pulse width
tHW1
800
—
—
ns
CP "L" pulse width
tLW
800
—
—
ns
DO setup time
tS
300
—
—
ns
DO holding time
tDH
300
—
—
ns
"L" clock set-up time
tSU
500
—
—
ns
"L" clock hold time
tHO
100
—
—
ns
"L" "H" pulse width
tHW2
800
—
—
ns
tM
–1000
—
1000
ns
DF delay time
VOH2
VOL2
DO
tHW1
VOH2 VOH2
CP
ts
tLW
VOL2
VOH2
VOL2
VOL2
tDH
VOH2
VOH2
VOL2
tSU
VOH2
L
DF
VOH2
tHO
VOL2
tHW2
tM
VOH2
12/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
FUNCTIONAL DESCRIPTION
Instruction Register (IR) and Data Register (DR)
These two registers are selected by the REGISTER SELECTION (RS) pin.
The DR is selected when the "H" level is input to the RS pin and IR is selected when the "L"
level is input.
The IR is used to store the address of the display data RAM (DD RAM) or character
generator RAM (CG RAM) and instruction code.
The IR can be written, but not be read by the microcomputer (CPU).
The DR is used to write and read the data to and from the DD RAM or CG RAM.
The data written to DR by the CPU is automatically written to the DD RAM or CG RAM
as an internal operation.
When an address code is written to IR, the data (of the specified address) is automatically
transferred from the DD RAM or CG RAM to the DR. Next, when the CPU reads the DR,
it is possible to verify DD RAM or CG RAM data from the DR data.
After the writing of DR by the CPU, the next adress in the DD RAM or CG RAM is selected
to be ready for the next CPU writing.
Likewise, after the reading out of DR by the CPU, DD RAM or CG RAM data is read out
by the DR to be ready for the next CPU reading.
Write/read to and from both registers is carried out by the READ/WRITE (R/W) pin.
Table 1 RS and R/W pins functions
R/W
RS
L
L
IR write
H
L
Read of busy flag (BF) and address counter (ADC)
L
H
DR write
H
H
DR read
Function
Busy Flag (BF)
When the busy flag is at "H", it indicates that the ML9040A-Axx/-Bxx is engaged in internal
operation.
When the busy flag is at "H", any new instruction is ignored.
When R/W = "H" and RS = "L", the busy flag is output from DB7.
New instruction should be input when busy flag is "L" level.
When the busy flag is at "H", the output code of the address counter (ADC) is undefined.
Address Counter (ADC)
The address counter (ADC) allocates the address for the DD RAM and CG RAM write/
read and also for the cursor display.
When the instruction code for a DD RAM address or CG RAM address setting is input to
IR, after deciding whether it is DD RAM or CG RAM, the address code is transferred from
IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM,
the ADC is incremented (decremented) by 1 internally.
The data of the ADC is output to DB0 - DB6 on the conditions that R/W = "H", RS = "L", and
BF = "L".
13/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfer e with the internal operation caused by LCD driving. Consequently, when data
is written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
ADC
DB6
DB0
MSB
LSB
Hexadecimal notation
(Example)
When DD RAM
address is 2A
L
H
Hexadecimal notation
L
H
L
2
H
L
A
(1) Corresponden ce between address and display position in the 1-line display mode
First
digit
00
2
01
3
02
4
03
5
04
79
4E
MSB
80
4F
Display position
DD RAM address (hex.)
LSB
(2) When the ML9040A-Axx/-Bxx alone is used, up to 8 characters can be displayed from
the first to eighth digit.
First
digit
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
(Display
shifted
to right)
(Display
shifted
to left)
First
digit
4F
First
digit
01
2
00
3
01
4
02
5
03
6
04
7
05
8
06
2
02
3
03
4
04
5
05
6
06
7
07
8
08
14/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(3) When the ML9040A-Axx/-Bxx is used with one MSM5259, up to 16 characters can be
displayed from the first to sixteenth digit as shown below:
First
digit
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
10
09
ML9040A-Axx/-Bxx display
11
0A
12
0B
13
0C
14
0D
15
0E
16
0F
MSM5259 display
When the display is shifted by instruction, the correspondence between the LCD
display and the DD RAM address changes as shown below:
(Display shifted to right)
First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
ML9040A-Axx/-Bxx display
(Display shifted to left)
MSM5259 display
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
(4) Since the ML9040A-Axx/-Bxx has a DD RAM capacity of up to 80 characters, up to 9
MSM5259 devices can be connected to ML9040A-Axx/-Bxx so that 80 characters can be
displayed.
First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
ML9040A-Axx/-Bxx display
MSM5259 (1) display
MSM5259 (2)
- (8) display
73 74 75 76 77 78 79 80
48 49 4A 4B 4C 4D 4E 4F
MSM5259 (9) display
15/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(5) Correspondence between address and display position in the 2-line display mode
First
digit
First line
00
2
01
3
02
4
03
5
04
39
26
40
27
Second line
40
41
42
43
44
66
67
Display position
DD RAM address (hex.)
(Note) The last address of the first line is not consecutive to the head address of the
second line.
(6) When ML9040A-Axx/-Bxx alone is used, up to 16 characters (8 characters x 2 lines) can
be displayed from the first to eighth digit.
First line
Second line
First
digit
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
40
41
42
43
44
45
46
47
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
(Display shifted to right)
First line
Second line
First
digit
27
2
00
3
01
4
02
5
03
6
04
7
05
8
06
67
40
41
42
43
44
45
46
First
digit
(Display shifted to left)
First line
01
2
02
3
03
4
04
5
05
6
06
7
07
8
08
Second line
41
42
43
44
45
46
47
48
(7) When the ML9040A-Axx/-Bxx is used with one MSM5259, up to 32 characters (16
characters x 2 lines) can be displayed from the first to the sixteenth digit.
First line
Second line
First
digit
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
10
09
11
0A
12
0B
13
0C
14
0D
15
0E
16
0F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
ML9040A-Axx/-Bxx display
MSM5259 display
16/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
(Display shifted to right)
First
digit
First line
27
2
00
Second line
67
40
3
01
4
02
5
03
6
04
7
05
8
06
9
07
10
08
11
09
12
0A
13
0B
14
0C
15
0D
16
0E
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
ML9040A-Axx/-Bxx display
MSM5259 display
(Display shifted to left)
First line
Second line
First
digit 2
01 02
3
03
4
04
5
05
6
06
7
07
8
08
9
09
10
0A
11
0B
12
0C
13
0D
14
0E
15
0F
16
10
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
41
ML9040A-Axx/-Bxx display
MSM5259 display
(8)Since the ML9040A-Axx/-Bxx has a DD RAM capacity of up to 80 characters, up to 4
MSM5259 devices can be connected to the ML9040A-Axx/-Bxx in the 2-line display
mode.
First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
First line
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
Second line 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51
ML9040A-Axx/-Bxx display
MSM5259 (1) display
33 34 35 36 37 38 39 40
20 21 22 23 24 25 26 27
60 61 62 63 64 65 66 67
MSM5259
MSM5259 (4) display
(2) - (3) display
Character Generator ROM (CG ROM)
The CG ROM is used to generate 5 x 7 dots (160 kinds) or 5 x 10 dots (32 kinds) character
patterns from an 8-bit DD RAM character code signal.
The correspondence between 8-bit character codes and character patterns of standard code
01 is shown in Table 2.
When the 8-bit character code of the CG ROM is written to the DD RAM, the character
pattern of the CG ROM corresponding to the code is displayed on the LCD display position
corresponding to the DD RAM address.
17/49
MSB
0000
0000
LSB
CG
RAM (1)
0001
(2)
0010
(3)
0011
(4)
0100
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
P
/
p
a
R
1
A
Q
a
q
ä
q
2
B
R
b
r
b
Q
#
3
C
S
c
s
e
•
(5)
$
4
D
T
d
t
m
W
0101
(6)
%
5
E
U
e
u
s
ü
0110
(7)
&
6
F
V
f
v
r
S
0111
(8)
7
G
W
n
w
g
p
1000
(1)
(
8
H
X
h
x
√
X
1001
(2)
)
9
I
Y
i
y
–1
1010
(3)
*
:
J
Z
j
z
j
1011
(4)
+
;
K
[
k
{
x
1100
(5)
<
L
¥
l
Ù
¢
1101
(6)
–
=
M
]
m
}
£
1110
(7)
.
>
N
^
n
Æ
n
1111
(8)
/
?
O
_
o
¨
!
°
ö
÷
PEDL9040A-03
@
ML9040A-Axx/-Bxx
18/49
0
¡ Semiconductor
Upper
4 bits
Table 2 Relationship Between Character Codes and Characters (Character Patterns) of
ML9040A-A01/-B01
Lower
4 bits
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Character Generator RAM (CG RAM)
The CG RAM is used to display user's original character patterns other than character
patterns in the CG ROM.
The CG RAM has a capacity (64 bytes = 512 bits) of writing 8 kinds of characters for 5 x 7
dots and 4 kinds of characters for 5 x 10 dots.
When displaying character patterns stored in the CG RAM, write 8-bit character codes (00
to 07 or 08 to 0F; hex.) on the left side as shown in Table 2. Then it is possible to output the
character pattern to the LCD display position corresponding to the DD RAM address.
The following explains how to write and read character patterns to and from the CG RAM.
(1) When the character pattern is 5 x 7 dots (see Table 3-1).
• A method of writing character pattern to the CG RAM by CPU:
Three bits of CG RAM addresses 0-2 correspond to the line position of the character
pattern.
First, set increment or decrement by the CPU, and then input the CG RAM address.
After this, write character patterns to the CG RAM through DB0 - DB7 line by line.
DB0 to DB7 correspond to CG RAM data 0-7 in Table 3-1.
It is displayed when "H" is set as input data and is not displayed when "L" is set as
input data.
Since the ADC is automatically incremented or decremented by 1 after the writing of
data to the CG RAM, it is not necessary to set the CG RAM address again.
The line, in which the CG RAM addresses 0-2 are all "H" ("7" in hexadecimal
notation), is the cursor position. It is ORed with the cursor at the cursor position and
displayed to LCD.
For this reason, it is necessary to set all input data that become cursor positions to "L".
Although CG RAM data 0-4 bits are output to the LCD as display data, CG RAM data
bits 5-7 are not output. The latter can be written and read to and from the RAM, it
is therefore allowed to be used as data RAM.
• A method of displaying the CG RAM character pattern to the LCD:
The CG RAM is selected when upper 4 bits of the character codes are all "L".
As character code bit 3 is invalid, the display of "0" in Table 3-1, is selected by
character code "00" (hex.) or "08" (hex.).
When the 8-bit character code of the CG RAM is written to the DD RAM, the character
pattern of the CG RAM is displayed on the LCD display position corresponding to
the DD RAM address. (DD RAM data, bits 0-2 correspond to CG RAM address, bits
3-5.)
19/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(2) When character pattern is 5 x 10 dots (see Table 3-2).
• A method of writing character pattern into the CG RAM by the CPU:
Four bits of CG RAM address, bits 0-3, correspond to the line position of the character
pattern.
First, set increment or decrement with the CPU, and then input the address of the CG
RAM.
After this, write the character pattern code into the CG RAM, line by line from DB0DB7.
DB0 to DB7 correspond to CG RAM data, bits 0-7, in Table 3-2.
It is displayed when "H" is set as input data, while it is not displayed when "L" is set
as input data.
As the ADC is automatically incremented or decremented by 1 after the writing of
data to the CG RAM, it is not necessary to set the CG RAM address again.
The line, the CGRAM addresses 0-3 of which are "A" in hexadecimal notation, is the
cursor position. The CGRAM data is 0Red with the cursor at the cursor position and
displayed to LCD. For this reason, it is necessary to set all input data that become
cursor positions to "L".
When the CG RAM data, bits 0-4, and CG RAM addresses, bits 0-3, are "0" to "A", they
are displayed on the LCD as the display data. When the CG RAM data, bits of 5-7,
and CG RAM, bit data is 0-4 and CG RAM address data is "B" to "F", it is not output
to the LCD.
But in this case, CG RAM can be used as RAM and it can be written into/read out.
So, it can be used as the data RAM.
• A method of displaying the CG RAM character pattern to the LCD:
The CG RAM is selected when 4-upper order bits of the character code are all "L".
As character code bits 0 and 3 are invalid, the display of "m" is selected by character
codes "00", "01", "08", and "09" (hex.) as in Table 3-2.
When the CG RAM character code is written to the DD RAM, the CG RAM character
pattern is displayed on the LCD display position corresponding to the DD RAM
address.
(DD RAM data bits 1 and 2 correspond to CG RAM address bits 4 and 5.)
20/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Table 3-1 Relationship between CG RAM data (character pattern), CG RAM address and
DD RAM data when the character pattern is 5 x 7 dots.
The example below indicates "OKI".
CG RAM address
5 4
MSB
3
2
1
0
LSB
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
L
L
H
H
H
CG RAM data
DD RAM data
(character pattern)
(character code)
7
6
MSB
5
4
3
2
1
0
LSB
L
H
L
H
L
H
L
H
X
X
L
H
H
H
H
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
H
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
X
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
H
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
X
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
X
X
X
X
X
7
6
MSB
5
L
L
L
L
X
L
L
L
L
L
L
L
X
L
L
H
L
L
L
L
X
H
H
H
4
3
2
1
0
LSB
X : Don't Care
21/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Table 3-2 Relationship between CG RAM data (character pattern), CG RAM address and
DD RAM data when the character pattern is 5 x 10 dots. The examples below
indicate m, g and .
W
CG RAM address
CG RAM data
DD RAM data
(character pattern)
(character code)
5 4
MSB
3
2
1 0
LSB
7
6
MSB
5
4
3
2
1 0
LSB
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
L
H
H
H
H
H
H
H
H
L
L
X
L
L
L
L
L
H
L
L
L
L
L
X
L
L
L
L
L
H
L
L
L
L
L
X
L
L
L
L
H
L
L
L
L
L
L
X
L
H
H
H
H
H
L
L
L
L
L
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
L
L
L
H
H
H
L
L
L
L
L
X
L
L
H
L
L
L
H
L
L
H
L
X
L
L
H
L
L
L
H
L
L
H
L
X
L
L
H
L
L
L
H
L
L
H
L
X
L
L
H
H
H
H
H
H
H
L
L
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
L
L
H
L
H
H
L
L
L
L
L
X
L
L
H
H
L
L
H
L
L
L
L
X
L
L
L
L
L
L
H
L
L
L
L
X
L
L
H
H
L
L
H
L
L
L
L
X
L
L
H
L
H
H
L
L
L
L
L
X
L
L
H
X
X
X
X
X
7
6
MSB
5
4
3
2
1 0
LSB
L
L
L
L
X
L
L
X
L
L
L
L
X
L
H
X
L
L
L
L
X
H
H
X
X : Don't Care
22/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Cursor/Blink Control Circuit
This is a circuit that generates the LCD cursor and blink.
This circuit is under the control of the CPU program.
The display of the cursor and blink on the LCD is made at a position corresponding to the
DD RAM address that is set in the ADC.
The figure below shows an example of the cursor/blink position when the value of ADC
is set to "07" (hex.).
DB6
ADC
L
DB0
L
L
L
H
0
First
digit
In 1-line display mode
00
2
01
H
H
6
05
7
06
7
3
02
4
05
5
04
8
07
9
08
79
4E
80
4F
Cursor and blink position
First
digit
In 2-line display mode
First line
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
39
26
40
27
Second line
40
41
42
43
44
45
46
47
48
66
67
Cursor and blink position
(Note) The cursor and blink are displayed even when the CG RAM address is set in the
ADC. For this reason, it is necessary to inhibit the cursor and blink display while
the CG RAM address is set in the ADC.
LCD Display Circuit (COM1 to COM16, SEG1 to SEG40, L, CP, DO, and DF)
As the ML9040A-Axx/-Bxx provides the COM signal outputs (16 outputs) and the SEG
signal outputs (40 outputs), it can display 8 characters (1-line display) or 16 characters (2line display) as a unit.
SEG1 to SEG40 are used to display 8-digit display on the LCD. To expand the display, an
MSM5259 is used.
The MSM5259, 40-dot segment driver, is used for expansion of the SEG signal output.
Interface with the MSM5259 is made through data output pin (DO), clock output pin (CP),
latch output pin (L), and display frequency pin (DF). The character pattern data is serially
transferred to MSM5259 through DO and CP. When the data of 72 characters 360-bit (= 5bit/ch. x 72 ch. = 1-line display) or 32 characters 160-bit (5-bit/ch. x 32 ch. = 2-line display)
is output, the latch pulse is also output through pin L. By this latch pulse, the data
transferred serially to MSM5259 is latched to be used as display data. The display
frequency signal (DF) required when LCD is displayed is also output from DF pin
synchronously with this latch pulse.
23/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Built-in Reset Circuit
The ML9040A-Axx/-Bxx is automatically initialized when the power is turned on.
During initialization, the busy flag (BF) holds "H" and does not accept instructions (other
than the busy flag read).
The busy flag holds "H" for 15 ms after VDD reaches 4.5V or more.
During initialization, the ML9040A-Axx/-Bxx executes the follwing instructions:
•
•
•
•
•
•
•
•
•
Display clear
Data length of interface with CPU: 8 bits (8B/4B = "H")
LCD: 1-line display (N = "L")
Character font: 5 x 7 dots (F = "L")
ADC: Increment (I/D = "H")
No display shift (SH = "L")
Display: Off (DI = "L")
Cursor: Off (C = "L")
No blink (B = "L")
It is required to satisfy the following power supply conditions.
4.5V
0.2V
0.2V
0.2V
VDD
tOFF
tON
0.1ms £ tON £ 100ms
1ms £ tOFF
Fig. 1. Power ON/OFF Waveform
24/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Data Bus Connected with CPU
The data bus connected with CPU is available either once for 8 bits or twice for 4 bits. This
allows the ML9040A-Axx/-Bxx to be interfaced with either an 8-bit or 4-bit CPU.
(1) When the interface data bus is 8 bits
Data bus DB0 to DB7 (8 lines) are all used and data input/output is carried out in one
step.
(2) When the interface data bus is 4 bits
The 8-bit data input/output is carried out in two steps by using only high-order 4 bits
of data bus DB4 to DB7 (4 lines)
The first time data input/output is made for 4-high order bits (DB4 to DB7) and the
second time data input/output is made for low-order 4 bits (DB0 to DB3). Even when
the data input/output can be completed through high-order 4 bits, be sure to make
another input/output of low-order 4 bits.
(Example: Busy flag Read).
Since the data input/output is carried out in two steps as one execution, no normal data
transfer is executed from the next input/output if accessed only once.
25/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
RS
R/W
E
Busy
(internal
operation)
IR7
No
Busy
Busy
DR7
DB7
DB6
IR6
ADC6
DR6
DB5
IR5
ADC5
DR5
DB4
IR4
ADC4
DR4
DB3
IR3
ADC3
DR3
DB2
IR2
ADC2
DR2
DB1
IR1
ADC1
DR1
DB0
IR0
ADC0
DR0
Instruction
register(IR)
write
Busy flag(BF)and address
counter(ADC)read
Data register
(DR)write
Fig. 2 8-Bit Data Transfer
26/49
¡ Semiconductor
RS
R/W
E
Busy(internal
operation)
DB7
IR7
IR3
No
Busy
ADC3
DR7
DR3
Busy
DB6
IR6
IR2
ADC6
ADC2
DR6
DR2
DB5
IR5
IR1
ADC5
ADC1
DR5
DR1
DB4
IR4
IR0
ADC4
ADC0
DR4
DR0
Instruction register
(IR)write
Busy flag(BF)and address
counter(ADC)read
PEDL9040A-03
27/49
ML9040A-Axx/-Bxx
Fig. 3 4-Bit Data Transfer
Data register
(DR)write
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Instruction Code
The instruction code is defined as the signal through which the ML9040A-Axx/-Bxx is
accessed by the CPU.
The ML9040A-Axx/-Bxx begins operation upon receipt of the instruction code input.
As the internal processing operation of ML9040A-Axx/-Bxx starts in a timing that does not
affect the LCD display, the busy status continues for longer than the CPU cycle time.
Under the busy status (when the busy flag is set to "H"), the ML9040A-Axx/-Bxx does not
execute any instructions other than the busy flag read.
Therefore, the CPU has to verify that the busy flag is set to "L" prior to the input of the
instruction code.
(1) Display clear:
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
L
L
L
L
L
H
When this instruction is executed, the LCD display is cleared.
I/D in the entry mode setting is set to "H" (increment). SH does not change.
When the cursor and blink are in display, the blinking position moves to the left end of the
LCD (the left end of the first line in the 2-line display mode).
(Note) All DD RAM data goes to "20" (hex.), while the address counter (ADC) goes to "00"
(hex.). The execution time is 1.53 ms (max.), when the OSC oscillation frequency
is 270 kHz.
(2) Cursor home
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
L
L
L
L
H
X
X : Don't Care
When this instruction is executed while the cursor and blink are being displayed, the
blinking position moves to the left end of the LCD (to the left end of the first line in the 2line display mode).
While the display is in shift, the display returns to its original position before shifting.
(Note) The address counter (ADC) goes to "00" (hex.). The execution time is 1.53 ms
(max.), when the OSC oscillation frequency is 270 kHz.
28/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(3) Entry mode setting
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
L
L
L
H I/D SH
1 When the I/D is set, the 8-bit character code is written or read to and from the DD
RAM, the cursor and blink shift to the right by 1 character position (I/D = "H";
increment) or to the left by 1 character position (I/D = "L"; decrement).
The address counter is incremented (I/D = "H") or decremented (I/D = "L") by 1 at
this time. Even after the character pattern code is written or read to and from the
CG RAM, the address counter (ADC) is incremented (I/D = "H") or decremented
(I/D = "L") by 1.
2 When SH = "H" is set, the character code is written to the DD RAM. Then the cursor
and blink stop and the entire display shifts to the left (I/D = "H") or to the right (I/
D = "L") by 1 character position.
When the character is read from the DD RAM during SH = "H", or when the
character pattern data is written or read to or from the CG RAM during SH = "H",
the entire display does not shift, but normal write/read is performed (the entire
display does not shift, but the cursor and blink shift to the right (I/D = "H") or to the
left (I/D = "L") by 1 character position.
When SH = "L" is set, the display does not shift, but normal write/read is performed.
The execution time when the OSC oscillation frequency is 270 kHz is 37 ms.
(4) Display mode setting
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
L
L
H
DI
C
B
1 The DI bit controls whether the character pattern is displayed or not displayed.
When DI is "H", this bit makes the LCD display the character pattern.
When DI is "L", the LCD character pattern is not displayed. The cursor and blink
are also cancelled at this time.
(Note) Unlike the display clear, the character code is not rewritten at all.
2 The cursor is not displayed when C = "L" and is displayed when DI = "H" and C =
"H".
3 The blink is cancelled when B = "L" and is executed when DI = "H" and B = "H".
In the blink mode, all dots (including the cursor) and displaying character pattern
and cursor are displayed alternately at 379.2 ms (in 5 x 7 dots character font) or 521.5
ms (in 5 x 10 dots character font) when the OSC oscillation frequency is 270 kHz. The
execution time when the OSC oscillation frequency is 270 kHz is 37 ms.
29/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(5) Cursor and display shift
Instruction code
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
L
H D/C R/L X
X
L
L
X : Don't Care
When D/C = "L" and R/L = "L", the cursor and blink positions are shifted to the left by
1 character position (ADC is decremented by 1).
When D/C = L and R/L = "H", the cursor and blink positions are shifted to the right by
1 character position (ADC is incremented by 1).
When D/C = "H" and R/L = "L", the entire display is shifted to the left by 1 character
position. The cursor and blink positions are also shifted with the display (ADC remains
unchanged).
When D/C = "H" and R/L = "H", the entire display is shifted to the right by 1 character
position. The cursor and blink positions are also shifted with the display (ADC remains
unchanged).
In the 2-line display mode, the cursor and blink positions are shifted from the first to
the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.)
in the first line. No such shifting is made in other cases.
When shifting the entire display, the display pattern, cursor, and blink positions are in
no case shifted between lines (from the first to the second line or vice versa).
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(6) Initial setting
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
H 8B/4B N
F
X
X
X : Don't Care
1 When 8B/4B = "H", the data input/output to and from the CPU is carried out
simultaneously by means of 8 bits DB7 to DB0.
When 8B/4B = "L", the data input/output to and from the CPU is carried out in two
steps through 4 bits of DB7 to DB4.
2 The 2-line display mode of the LCD is selected when N = "H", while the 1-line
display mode is selected when N = "L".
3 The 5 x 7 dots character font is selected when F = "L", while the 5 x 10 dots character
font is selected when F = "H" and N = "L".
This initial setting has to be accessed prior to other instructions except for the busy
flag read after the power is supplied to the ML9040A-Axx/-Bxx.
N
F
Number of
display lines
Character
font
Duty
ratio
Number
of biases
Number of
COMMOM signals
L
L
1 line
5 x 7 dots
1/8
4
8
L
H
1 line
5 x 10 dots
1/11
4
11
H
L
2 lines
5 x 7 dots
1/16
5
16
H
H
2 lines
5 x 7 dots
1/16
5
16
30/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Generate biases externally and input them to VDD, V1, V2, V3, V4, and V5.
When the number of biases is 4, input the same potential to V2 and V3. The execution
time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(7) CG RAM address setting
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
H
C5 C4 C3 C2 C1 C0
When CG RAM addresses, bits C5 to C0 (binary), are set, the CG RAM is specified, until
the DD RAM address is set.
Write/read of the character pattern to and from the CPU begins with addresses, bits C5
to C0, starting from CG RAM selection.
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(8) DD RAM address setting
Instruction code
R/W RS
L
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H
D6 D5 D4 D3 D2 D1 D0
When the DD RAM addresses D6 to D0 (binary) are selected, the DD RAM is specified
until the DD RAM address is set.
Write/read of the character code to and from the CPU begins with addresses D6 to D0
starting from DD RAM selection.
In the 1-line display mode (N = H), however, D6 to D0 (binary) must be set to one of the
values among "00" to "4F" (hex.).
Likewise, in the 2-line mode, D6 to D0 (binary) must be set to one of the values among
"00" to "27" (hex.) or "40" to "67" (hex.).
When any value other than the above is input, it is impossible to make a normal write/
read of character codes to and from the DD RAM.
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(9) DD RAM and CG RAM data write
Instruction code
R/W RS
L
H
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
E7 E6 E5 E4 E3 E2 E1 E0
When E7 to E0 (binary) codes are written to the DD RAM or CG RAM, the cursor and
display move as described in "(5) Cursor and display shift". The execution time, when
the OSC oscillation frequency is 270 kHz, is 37 ms.
31/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(10) Busy flag and address counter read (Execution time is 1 ms.)
Instruction code
R/W RS
H
L
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF O6 O5 O4 O3 O2 O1 O0
The busy flag (BF) is output by this instruction to indicate whether the ML9040A-Axx/
-Bxx is engaged in internal operations (BF = "H") or not (BF = "L").
When BF = "H", no new instruction is accepted. It is therefore necessary to verify BF =
"L" before inputting a new instruction.
When BF = "L", a correct address counter value is output. The address counter value
must match the DD RAM address or CG RAM address. The decision of whether it is
a DD RAM address or CG RAM address is made by the address previously set.
Since the address counter value when BF = "H" is sometimes incremented or decremented
by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
Instruction code
R/W RS
H
H
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7 P6 P5 P4 P3 P2 P1 P0
Character codes (bits P7 to P0) are read from the DD RAM, while character patterns (P7
to P0) from the CG RAM.
Selection of DD RAM or CG RAM is decided by the address previously set.
After reading those data, the address counter (ADC) is incremented or decremented by
1 as set by the shift mode mentioned in item "(3) shift mode set".
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(Note) Conditions for the reading of correct data:
1 When the DD RAM address set or CG RAM address set is input before
inputting this instruction.
2 When the cursor/display shift is input before inputting this instruction in
case the character code is read.
3 Data after the second reading from RAM when read more than 2 times.
Correct data is not output in any other case.
32/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Interface with LCD and MSM5259
Display examples when setting the 5 x 7 dots character font 1-line mode, 5 x 10 dots character font
1-line mode, and 5 x 7 dots character font 2-line mode through instructions are shown in Figures
4, 5, and 6, respectively.
When the 5 x 7 dots character font is set in the 1-line display mode, the COM signals COM9 to
COM16 are output for extinguishing.
Likewise, when the 5 x 10 dots character font (1-line is set), the COM signals COM12 to COM16
are output for display-off.
The display example shows a combination of 16 characters (32 characters for the 2-line display
mode) and the LCD. When the number of MSM5259s are increased according to the increase in
the number of characters, it is possible to display a maximum of 80 characters.
Besides, it is necessary to generate bias voltage required for LCD operation by splitting resistors
outside the IC to input it to ML9040A-Axx/-Bxx and MSM5259.
Examples of these bias voltages are shown in Figures 7, 8, 9, and 10. Basically, this can be done
by dividing the voltage by the resistors as shown in Figures 7 and 8. If the value of resistor R is
made larger to reduce system power consumption, the LCD operating margin decreases and the
LCD driving waveform is distorted. To prevent this, a by-pass capacitor is serially connected to
the resistor to lower voltage division impedance caused by the splitting of resistors as shown in
Figures 9 and 10.
As the values of R, VR, and C vary according to the LCD size used and VLCD (LCD drive voltage),
these values have to be determined through actual experimentation in combination with the
LCD.
(Example set values: R = 3.3 to 10kW, VR = 10 to 30kW, and C = 0.0022 mF to 0.047 mF)
Figure 17 shows an application circuit for the ML9040A-Axx/-Bxx and MSM5259 including a
bias circuit.
The bias voltage has to maintain the following potential relation:
VDD > V1 > V2 ≥ V3 > V4 > V5
• In the case of 1-line 16 characters display (5 x 7 dots/font)
COM1
LCD
COM8
SEG1
SEG40
DO
CP
ML9040A-Axx/-Bxx
DF
L
O1
O40
DI1
CP
MSM5259
LOAD
DF
DO20 DI21
Figure 4
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PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
• In the case of 16-character (1 line) display (5 x 10 dots/font)
COM1
LCD
COM11
SEG1
SEG40
O1
DO
CP
ML9040A-Axx/-Bxx
DF
O40
DI1
CP
MSM5259
LOAD
L
DF DO20
DI21
Figure 5
• In the case of 16-character (2 lines) display (5 x 7 dots/font)
COM1
COM7
COM8
COM9
LCD
COM15
COM16
SEG1
SEG40
ML9040A-Axx/-Bxx
DF
O1
DO
DI1
CP
CP
L
O40
MSM5259
LOAD
DF
DO20
DI21
Figure 6
34/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
• Bias voltage circuit (1-line display mode)
• Bias voltage circuit (2-line display mode)
VDD
VDD
R
R
V1
V1
R
V2
R
ML9040A-Axx/-Bxx
VLCD
R
V3
V2
VLCD
R
ML9040A-Axx/-Bxx
V3
V4
R
R
V4
V5
VR
VR
V5
Figure 8
Figure 7
• Bias voltage circuit (1-line display mode)
• Bias voltage circuit (2-line display mode)
VDD
VDD
R
C
V1
V2
R
V3
R
C
ML9040A-Axx/-Bxx
C
R
C
V2
VLCD
ML9040A-Axx/-Bxx
R
V3
C
V4
R
R
V1
R
C
VR
C
VLCD
C
V4
V5
R
C
Figure 9
C
VR
V5
Figure 10
C
(VLCD : LCD driving voltage)
35/49
SEG1-40
ML9040A-Axx/-Bxx
COM1-16
V1
V2
V3
V4
V5
VDD
GND
CP
L
DF
DO
+5V
DI21
C
R
R
R
C
R
C
R
C
C
VR
0V
DI21
DO20
VDD VSS V2 V3 VEE
DI1
CP
LOAD
DF
O1 - O40
MSM5259
DO40
¡ Semiconductor
C
VDD VSS V2 V3 VEE
DI21
DO20
DO40
DO20
DI1
CP
LOAD
DF
O1 - O40
MSM5259
DO40
VDD VSS V2 V3 VEE
DI1
CP
LOAD
DF
O1 - O40
MSM5259
LCD
PEDL9040A-03
ML9040A-Axx/-Bxx
• Application circuit
Figure 11
36/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
LCD Drive Waveforms
Figures 12, 13 and 17 show the LCD driving waveforms consisting of COM signal, SEG signal,
DF signal and L (latch pulse waveform) signal, in the duty of 1/8, 1/11 and 1/16 respectively.
The relation between duty and frame frequency is described in the table below.
Duty
Frame frequency
1/8
84.3 Hz
1/11
61.4 Hz
1/16
84.3 Hz
(Note) The OSC oscillation frequency is assumed to be 270 kHz.
37/49
PEDL9040A-03
¡ Semiconductor
8
COM1
COM2
COM8
COM9
COM16
VDD
V1
V2,V3
V4
V5
1
ML9040A-Axx/-Bxx
2
3
4
5
6
7
8
1
2
1 frame
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
Display-off
waveform
VDD
SEG
V1
(Output V2,V3
example) V4
V5
Display-on
waveform
DF
L
Figure 12. LCD Driving Waveforms (A mode) at 1/8 Duty
38/49
PEDL9040A-03
¡ Semiconductor
11
COM1
COM2
VDD
V1
V2,V3
V4
V5
1
2
3
4
5
6
7
8
9
10
11
1
2
1 frame
VDD
V1
V2,V3
V4
V5
COM11
VDD
V1
V2,V3
V4
V5
COM12
VDD
V1
V2,V3
V4
V5
COM16
ML9040A-Axx/-Bxx
VDD
V1
V2,V3
V4
V5
Display-off
waveform
SEG
(Output
example)
VDD
V1
V2,V3
V4
V5
Display-on
waveform
DF
L
Figure 13. LCD Driving Waveforms (A mode) at 1/11 Duty
39/49
PEDL9040A-03
¡ Semiconductor
16
COM1
COM2
COM16
VDD
V1
V2
V3
V4
V5
1
ML9040A-Axx/-Bxx
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16
1
2
1 frame
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
Display-off
waveform
SEG
(Output
example)
VDD
V1
V2
V3
V4
V5
Display-on
waveform
DF
L
Figure 14. LCD Driving Waveforms (A mode) at 1/16 Duty
40/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
COM1
COM2
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
COM8
VDD
V1
V2,V3
V4
V5
COM9
VDD
V1
V2,V3
V4
V5
COM16
SEG
(Output
example)
1 frame
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
Display turning-off
waveform
Display turning-on
waveform
DF
L
Figure 15. LCD Driving Waveforms (B mode) at 1/8 Duty
41/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
1011 1 2 3 4 5 6 7 8 9 1011 1 2 3 4 5
COM1
COM2
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
COM11
VDD
V1
V2,V3
V4
V5
COM12
VDD
V1
V2,V3
V4
V5
COM16
SEG
(Output
example)
1 frame
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
Display turning-off
waveform
Display turning-on
waveform
DF
L
Figure 16. LCD Driving Waveforms (B mode) at 1/11 Duty
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PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
COM1
COM2
COM16
SEG
(Output
example)
VDD
V1
V2
V3
V4
V5
1 frame
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
Display turning-off
waveform
Display turning-on
waveform
DF
L
Figure 17. LCD Driving Waveforms (B mode) at 1/16 Duty
43/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Initial Setting of Instruction
(1) When data input/output to and from the CPU is carried out by 8 bits (DB0 to DB7):
q
w
e
r
t
y
u
i
o
!0
!1
!2
!3
!4
!5
!6
!7
Turn on the power.
Wait for 15 ms or more after VDD has reached 4.5V or more.
Set 8B by initial setting of instruction.
Wait for 4.1 ms or more.
Set 8B by initial setting of instruction.
Wait for 100 ms or more.
Set 8B by initial setting of instruction.
Check the busy flag as No Busy.
Set 8B. Set LCD line number (N) and character font (F).
(After this, the LCD line number and character font cannot be changed.)
Check No Busy.
Clear the display by setting the display mode.
Check No Busy.
Clear the display.
Check No Busy.
Set the shift mode.
Check No Busy.
Initial setting completed.
Example of Instruction Code for Steps e, t, and u.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
H
H
X
X
X
X
L
L
X : Don't Care
44/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(2) When data input/output to and from the CPU is carried out by 4 bits (DB4 to DB7):
q
w
e
r
t
y
u
i
o
!0
!1
!2
!3
!4
!5
!6
!7
!8
!9
Turn on the power.
Wait for 15 ms or more after VDD has reached 4.5V or more.
Set 8B by initial setting of instruction.
Wait for 4.1 ms or more.
Set 8B by initial setting of instruction.
Wait for 100 ms or more.
Set 8B by initial setting of instruction.
Check the busy flag as No Busy.
Set 4B by initial setting of instruction.
Wait for 100 ms or more.
Set 4B, LCD line number (N) and character font (F) by initial setting of instruction.
(After this, the LCD line number and character font cannot be changed.)
Check No Busy.
Clear the display by setting the display mode.
Check No Busy.
Clear the display.
Check No Busy.
Set the shift mode.
Check No Busy.
Initialization completed.
Example of Instruction Code for Steps e, t, and u.
R/W RS
L
L
DB7 DB6 DB5 DB4
L
L
H
H
Example of Instruction Code for Step o.
R/W RS
L
L
DB7 DB6 DB5 DB4
L
L
H
L
Example of Instruction Code for Step i.
RS1 RS0 R/W DB7 DB6 DB5 DB4
H
L
H
BF Q6 Q5 Q4
Execute two-step accesses in 4 bits from Step !1 to Step !8.
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PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
PAD CONFIGURATION
Pad Layout
Chip size: 2.94 x 4.32 mm
Passivation film etched hole: 80 x 80 mm
Y
57
43
58
42
X
18
81
Pad Coordinates
17
1
Pad
Pad Name
X(µm)
Y (µm)
Pad
Pad Name
X(µm)
Y (µm)
1
SEG39
–1310
–1955
21
SEG19
1311
–1342
2
SEG38
–1156
–1955
22
SEG18
1311
–1206
3
SEG37
–1002
–1955
23
SEG17
1311
–1070
4
SEG36
–848
–1955
24
SEG16
1311
–934
5
SEG35
–694
–1955
25
SEG15
1311
–797
6
SEG34
–540
–1955
26
SEG14
1311
–661
7
SEG33
–386
–1955
27
SEG13
1311
–525
8
SEG32
–233
–1955
28
SEG12
1311
–389
9
SEG31
–79
–1955
29
SEG11
1311
–253
10
SEG30
75
–1955
30
SEG10
1311
–116
11
SEG29
229
–1955
31
SEG9
1311
20
12
SEG28
383
–1955
32
SEG8
1311
156
13
SEG27
537
–1955
33
SEG7
1311
292
14
SEG26
691
–1955
34
SEG6
1311
428
15
SEG25
845
–1955
35
SEG5
1311
565
16
SEG24
999
–1955
36
SEG4
1311
701
17
SEG23
1153
–1955
37
SEG3
1311
837
18
SEG22
1309
–1955
38
SEG2
1311
973
19
SEG21
1311
–1615
39
SEG1
1311
1109
20
SEG20
1311
–1478
40
TEST
1311
1296
46/49
PEDL9040A-03
¡ Semiconductor
Pad
Pad Name
ML9040A-Axx/-Bxx
X(mm)
Y(mm)
41
GND
1311
1426
42
OSC1
1311
1955
43
OSC2
1049
1955
44
V1
738
1955
45
V2
576
1955
46
V3
414
1955
47
V4
252
1955
48
V5
90
1955
49
L
—347
1955
50
CP
—491
1955
51
VDD
—610
1955
52
DF
—710
1955
53
DO
—810
1955
54
RS
—910
1955
55
RW
—1010
1955
56
E
—1111
1955
57
DB0
—1211
1955
58
DB1
—1311
1955
59
DB2
—1311
1783
60
DB3
—1311
1369
61
DB4
—1311
1184
62
DB5
—1311
1000
63
DB6
—1311
816
64
DB7
—1311
632
65
COM1
—1311
148
66
COM2
—1311
48
67
COM3
—1311
—52
68
COM4
—1311
—152
69
COM5
—1311
—253
70
COM6
—1311
—353
71
COM7
—1311
—453
72
COM8
—1311
—553
73
COM9
—1311
—653
74
COM10
—1311
—754
75
COM11
—1311
—854
76
COM12
—1311
—954
77
COM13
—1311
—1054
78
COM14
—1311
—1154
79
COM15
—1311
—1255
80
COM16
—1311
—1355
81
SEG40
—1311
—1455
47/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.27 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
48/49
PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
49/49