TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP www.ti.com SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION Check for Samples: TPS3619-33-EP, TPS3619-50-EP, TPS3620-33-EP, TPS3620-50-EP FEATURES APPLICATIONS • • • • • • • • • • • • 1 • • • • • • Supply Current of 40 mA (Max) Battery-Supply Current of 100 nA (Max) Precision Supply-Voltage Monitor 3.3 V, 5 V, and Other Options on Request Backup-Battery Voltage Can Exceed VDD Power-On Reset Generator with Fixed 100-ms Reset Delay Time Voltage Monitor for Power-Fail or Low-Battery Monitoring Battery Freshness Seal (TPS3619) Pin-to-Pin Compatible With MAX819, MAX703, and MAX704 8-Pin Mini Small-Outline Package (MSOP) Package • • • (1) DESCRIPTION The TPS3619 and TPS3620 families of supervisory circuits monitor and control processor activity by providing backup-battery switchover for data retention of CMOS RAM. During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above VIT. When the supply voltage drops below VIT, the output becomes active (low) again. SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • Fax Machines Set-Top Boxes Advanced Voice-Mail Systems Portable Battery-Powered Equipment Computer Equipment Advanced Modems Automotive Systems Portable Long-Time Monitoring Equipment Point-of-Sale Equipment Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability The product spectrum is designed for supply voltages of 3.3 V and 5 V. The TPS3619 and TPS3620 are available in an 8-pin MSOP package and are characterized for operation over a temperature range of –55°C to 125°C. Additional temperature ranges available - contact factory DGK PACKAGE (TOP VIEW) VOUT VDD GND PFI 1 8 2 7 3 6 4 5 VBAT RESET MR PFO ACTUAL SIZE 3,05 mm x 4,98 mm 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2010, Texas Instruments Incorporated TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TYPICAL OPERATING CIRCUIT Power Supply TPS3619 TPS3620 0.1 µF Microcontroller or Microprocessor Backup Battery VBAT VDD External Source RESET RESET Rx PFI Ry Switchover Capacitor MR Manual Reset I/O PFO VOUT GND VCC 0.1 µF GND PACKAGE INFORMATION (1) TA PRODUCT PACKAGE MARKING TPS3619-33 BZP TPS3619-50 TBD TPS3620-33 BTY TPS3620-50 TBD –55°C to 125°C (1) (2) ORDERABLE PART NUMBER TRANSPORT MEDIA, QUANTITY TPS3619-33MDGKEP (2) Tube, 80 TPS3619-33MDGKREP Tape and reel, 2500 TPS3619-50MDGK (2) Tube, 80 TPS3619-50MDGKREP (2) Tape and reel, 2500 TPS3620-33MDGKTEP Tape and reel, 250 TPS3620-33MDGKREP Tape and reel, 2500 TPS3620-50MDGKTEP (2) Tape and reel, 250 TPS3620-50MDGKREP (2) Tape and reel, 2500 For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or see the TI web site at www.ti.com. Product Preview. Parameters in electrical characteristics are subject to change. Standard and Application-Specific Versions TPS361 9 33 M DGK R EP Designator Reel Package Temperature Range DEVICE NAME NOMINAL VOLTAGE (1), VNOM TPS3619-33 DGK 3.3 V TPS3619-50 DGK 5V TPS3620-33 DGK 3.3 V TPS3620-50 DGK 5V Nominal Supply Voltage Functionality (1) Family 2 Submit Documentation Feedback For other threshold voltage versions, contact the local TI sales office for availability and lead time. Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP www.ti.com SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) UNIT VDD Supply voltage (2) MR and PFI pins 7V (2) –0.3 V to (VDD + 0.3 V) VOUT Continuous output current, IO 400 mA All other pins (2) ±10 mA Continuous total power dissipation See Dissipation Ratings Table Operating free-air temperature range, TA –55°C to 125°C Storage temperature range, Tstg –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 in) from case for 10 s (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. For reliable operation, the device must not be continuously operated at 7 V for more than t = 1000 h. Dissipation Ratings PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING DGK 470 mW 3.76 mW/°C 301 mW 241 mW 93.98 mW Recommended Operating Conditions at specified temperature range MIN MAX UNIT 1.65 5.5 V 1.5 5.5 V 0 VDD + 0.3 V VDD Supply voltage VBAT Battery supply voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IO Continuous output current at VOUT 300 mA Input transition rise and fall rate at MR 100 ns/V 1 V/ms Δt/ΔV Slew rate at VDD or VBAT TA Operating free-air temperature Copyright © 2006–2010, Texas Instruments Incorporated 0.7 × VDD V 0.3 × VDD –55 125 Submit Documentation Feedback Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP V °C 3 TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 www.ti.com Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS RESET VOH High-level output voltage PFO VOL Low-level output voltage RESET, PFO Power-up reset voltage (1) Vres Normal mode VOUT Battery-backup mode rDS(on) VDD – 0.4 VDD = 5 V, IOH = –3 mA VDD – 0.4 VDD = 1.8 V, IOH = –20 mA VDD – 0.3 VDD = 3.3 V, IOH = –80 mA VDD – 0.4 VDD = 5 V, IOH = –120 mA VDD – 0.4 0.4 0.4 IOL = 20 mA, VBAT > 1.1 V or VDD > 1.1 V 0.4 IOUT = 8.5 mA, VBAT = 0 V, VDD = 1.8 V VDD – 50 IOUT = 125 mA, VBAT = 0 V, VDD = 3.3 V VDD – 150 IOUT = 190 mA, VBAT = 0 V, VDD = 5 V VDD – 200 IOUT = 0.5 mA, VBAT = 1.5 V, VDD = 0 V VBAT – 50 IOUT = 7.5 mA, VBAT = 3.3 V VBAT – 150 TA = –55°C to 125°C TA = –55°C to 125°C VIT Vhys Hysteresis V VDD = 5 V, IOL = 3 mA VDD = 3.3 V VPFI UNIT 0.2 VDD = 5 V TPS36XX-50 MAX VDD = 3.3 V, IOL = 2 mA VBAT to VOUT on resistance Negative-going input threshold voltage (2) TYP VDD = 1.8 V, IOL = –400 mA VDD to VOUT on resistance TPS36XX-33 VIT– MIN VDD = 3.3 V, IOH = –2 mA V V mV 0.6 1 8 20 2.88 2.93 3.05 4.46 4.55 4.64 1.13 1.15 1.185 1.65 V < VIT < 2.5 V 20 2.5 V < VIT < 3.5 V 40 3.5 V < VIT < 5.5 V 60 PFI Ω V V mV 12 VBSW (3) VDD = 1.8 V 55 IIH High-level input current MR MR = 0.7 × VDD, VDD = 5 V –30 –76 mA IIL Low-level input current MR MR = 0 V, VDD = 5 V –110 –255 mA II Input current PFI –25 25 nA IOS Short-circuit current PFO IDD VDD supply current I(BAT) VBAT supply current CI Input capacitance (1) (2) (3) 4 PFO = 0 V VDD = 1.8 V –0.3 VDD = 3.3 V –1.1 VDD = 5 V –2.4 VOUT = VDD 40 VOUT = VBAT 40 VOUT = VDD –0.1 0.1 VOUT = VBAT 0.5 VI = 0 V to 5 V 5 mA mA mA pF The lowest supply voltage at which RESET becomes active. tr,VDD ≥ 15 ms/V. To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 mF) should be placed near the supply terminals. For VDD < 1.6 V, VOUT switches to VBAT, regardless of VBAT. Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP www.ti.com SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 Timing Requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER tw Pulse width TEST CONDITIONS at VDD VIH = VIT + 0.2 V, VIL = VIT – 0.2 V at MR VDD = VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 × VDD MIN MAX UNIT 6 ms 100 ns Switching Characteristics at RL = 1 MΩ, CL= 50 pF, TA= –55°C to 125°C PARAMETER TEST CONDITIONS VDD ≥ VIT + 0.2 V, MR ≥ 0.7 × VDD, See timing diagram td Delay time tPHL Propagation (delay) time, high-to-low-level output MIN TYP MAX UNIT 60 100 140 ms VDD to RESET VIL = VIT – 0.4 V, VIH = VIT + 0.4 V 2 5 PFI to PFO delay VIL = VPFI – 0.35 V, VIH = VPFI + 0.35 V 3 5 MR to RESET VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 0.1 1 ms Timing Diagram VBAT VDD VIT t VOUT t RESET td td t Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP 5 TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 www.ti.com Table 1. FUNCTION TABLE VDD > VIT VDD > VBAT MR VOUT RESET 0 0 L VBAT L 0 0 H VBAT L 0 1 L VDD L 0 1 H VDD L 1 0 L VDD L 1 0 H VDD H 1 1 L VDD L 1 1 H VDD H PFI > VPFI PFO 0 L 1 H CONDITION: VDD > VDD(MIN) TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION GND 3 I Ground MR 6 I Manual reset PFI 4 I Power-fail comparator input PFO 5 O Power-fail comparator output RESET 7 O Active-low reset VBAT 8 I Backup battery VDD 2 I Supply input voltage VOUT 1 O Supply output voltage 6 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP www.ti.com SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 FUNCTIONAL BLOCK DIAGRAM VBAT + _ Switch Control VOUT VDD MR + _ PFI + _ RESET Logic + Timer RESET PFO Reference Voltage of 1.15 V Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP 7 TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS − Static Drain-Source On-State Resistance − Ω 500 VDD = 3.3 V VBAT = GND 900 TA = 85°C 800 TA = 25°C 700 TA = 0°C TA = −40°C 600 50 75 100 125 150 175 200 IO − Output Current − mA VIT − Normalized Threshold Voltage at RESET − V I DD − Supply Current − µ A or VDD Mode VBAT = GND TA = 0°C TA = −40°C 10 5 0 1 2 3 4 VDD − Supply Voltage − V Figure 3. 8 15 TA = 85°C 12.5 TA = 25°C TA = 0°C 10 7.5 5 2.5 TA = −40°C 4.5 6.5 8.5 10.5 12.5 IO − Output Current − mA NORMALIZED THRESHOLD AT RESET vs FREE-AIR TEMPERATURE TA = 85°C 0 17.5 SUPPLY CURRENT vs SUPPLY VOLTAGE TA = 25°C 15 VBAT = 3.3 V Figure 2. VBAT Mode VBAT = 2.6 V 20 20 Figure 1. 30 25 STATIC DRAIN-SOURCE ON-STATE RESISTANCE (VBAT to VOUT) vs OUTPUT CURRENT r DS(on) − Static Drain-Source On-State Resistance − m Ω 1000 r DS(on) STATIC DRAIN-SOURCE ON-STATE RESISTANCE (VDD to VOUT) vs OUTPUT CURRENT Submit Documentation Feedback 5 6 14.5 1.001 1 0.999 0.998 0.997 0.996 0.995 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 TA − Free-Air Temperature − °C Figure 4. Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP www.ti.com SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT 5.1 VOH – High-Level Output Voltage at RESET – V VOH – High-Level Output Voltage at RESET – V 6 VDD = 5 V VBAT = GND 5 TA = −40°C TA = 25°C 4 TA = 0°C 3 2 TA = 85°C 1 0 TA = −40°C 4.9 TA = 25°C TA = 0°C 4.8 4.7 TA = 85°C VDD = 5 V VBAT = GND 4.6 4.5 0 −5 −10 −15 −20 −25 −30 IOH − High-Level Output Current − mA 0 −35 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 IOH − High-Level Output Current − mA Figure 5. Figure 6. HIGH-LEVEL OUTPUT VOLTAGE AT PFO vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT PFO vs HIGH-LEVEL OUTPUT CURRENT 6 5.55 VOH – High-Level Output Voltage at PFO – V VOH – High-Level Output Voltage at PFO – V Expanded View 5 TA = −40°C 5 TA = 25°C 4 TA = 0°C 3 TA = 85°C 2 VDD = 5.5 V PFI = 1.4 V VBAT = GND 1 0 0 −0.5 −1 −1.5 −2 IOH − High-Level Output Current − mA Figure 7. Copyright © 2006–2010, Texas Instruments Incorporated −2.5 Expanded View 5.50 TA = −40°C 5.45 TA = 25°C TA = 0°C 5.40 5.35 5.30 TA = 85°C 5.25 5.20 5.15 VDD = 5.5 V PFI = 1.4 V VBAT = GND 5.10 0 −20 −40 −60 −80 −100 −120 −140 −160 −180 −200 IOH − High-Level Output Current − µA Figure 8. Submit Documentation Feedback Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP 9 TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) LOW-LEVEL OUTPUT VOLTAGE AT RESET vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE AT RESET vs LOW-LEVEL OUTPUT CURRENT 500 VDD = 3.3 V VBAT = GND 3 VOL – Low-Level Output Voltage at RESET – mV VOL – Low-Level Output Voltage at RESET – V 3.5 2.5 TA = 0°C 2 TA = 25°C 1.5 TA = 85°C 1 TA = −40°C 0.5 0 5 10 15 20 IOL − Low-Level Output Current − mA TA = 0°C 200 TA = −40°C 100 1 2 3 4 IOL − Low-Level Output Current − mA 0 Figure 9. Figure 10. MINIMUM PULSE DURATION AT VDD vs THRESHOLD OVERDRIVE AT VDD MINIMUM PULSE DURATION AT PFI vs THRESHOLD OVERDRIVE AT PFI 5 9 4.6 8 7 6 5 4 3 2 1 5 VDD = 1.65 V 4.2 3.8 3.4 3 2.6 2.2 1.8 1.4 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Threshold Overdrive at VDD − V Figure 11. 10 TA = 25°C 300 10 0 0 TA = 85°C VDD = 3.3 V VBAT = GND 400 0 25 Minimum Pulse Duration at PFI − µ s Minimum Pulse Duration at VDD − µ s 0 Expanded View Submit Documentation Feedback 1 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Threshold Overdrive at PFI − V 0.9 1 Figure 12. Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP www.ti.com SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 DETAILED DESCRIPTION Battery Freshness Seal (TPS3619) The battery freshness seal of the TPS3619 family disconnects the backup battery from internal circuitry until it is needed. This function prevents the backup battery from being discharged until the final product is put to use. The following steps explain how to enable the freshness seal mode. 1. Connect VBAT (VBAT > VBAT min) 2. Ground PFO 3. Connect PFI to VDD (PFI = VDD) 4. Connect VDD to power supply (VDD > VIT) and retain for 5 ms < t < 35 ms The battery freshness seal mode is removed automatically by the positive-going edge of RESET when VDD is applied. Power-Fail Input/Output Comparator (PFI and PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The PFI is compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold (VIT(PFI)) of 1.15 V (typ), the PFO goes low. If VIT(PFI) goes above V(PFI) plus about 12-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to ensure that the current in the PFI pin can be ignored, compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1%, to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, PFI should be connected to ground and PFO left unconnected. Backup-Battery Switchover In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors do not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω switch) when VDD falls below the VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred, either until VDD crosses VBAT or until VDD rises above VIT. VOUT connects to VDD through a 1-Ω (max) PMOS switch when VDD crosses the reset threshold. Table 2. FUNCTION TABLE VDD > VBAT VDD > VIT VOUT 1 1 VDD 1 0 VDD 0 1 VDD 0 0 VBAT Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP 11 TPS3619-33-EP, TPS3619-50-EP TPS3620-33-EP, TPS3620-50-EP VDD – Normal Supply Voltage – V SGLS350C – JULY 2006 – REVISED SEPTEMBER 2010 www.ti.com VDD Mode VIT Hysteresis VBAT Mode VBSW Hysteresis Undefined VBAT – Backup-Battery Supply Voltage – V Figure 13. Normal Supply Voltage vs Backup-Battery Supply Voltage 12 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS3619-33MDGKREP ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3620-33MDGKREP ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3620-33MDGKTEP ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06670-01XE ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06670-03XE ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 OTHER QUALIFIED VERSIONS OF TPS3619-33-EP, TPS3620-33-EP : • Catalog: TPS3619-33, TPS3620-33 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS3619-33MDGKREP VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS3620-33MDGKREP VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS3620-33MDGKTEP VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3619-33MDGKREP VSSOP DGK 8 2500 358.0 335.0 35.0 TPS3620-33MDGKREP VSSOP DGK 8 2500 358.0 335.0 35.0 TPS3620-33MDGKTEP VSSOP DGK 8 250 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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