OKI Semiconductor MS81V26000 FEDSMS81V26000-02 Issue Date: Dec 15, 2004 1,114,112-Word × 24-Bit Field Memory GENERAL DESCRIPTION The OKI MS81V26000 is a high performance 26-Mbit, 1,100K × 24-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MS81V26000 is a FRAM for wide or low end use in general commodity TVs and VTRs exclusively. MS81V26000 is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture storage, data storage systems and others. More than two MS81V26000s can be cascaded directly without any delay devices among the MS81V26000s. (Cascading of MS81V26000 provides larger storage depth or a longer delay). Each of the 24-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams. The MS81V26000 provides high speed FIFO, First-In First-Out, operation without external refreshing: MS81V26000 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS81V26000’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additionally, the MS81V26000 has write mask function or input enable function (IE), and read-data skipping function or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MS81V26000. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture” on a TV screen. 1/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 FEATURES • • • • • • • • • • • Single power supply: 3.3 V ±0.3 V 1,114,112 words × 24 bits Fast FIFO (First-In First-Out) operation High speed asynchronous serial access Read/write cycle time 12 ns Access time 9 ns Randomly accessible leading address Variable length delay bit (350 to 1,114,112) Write/Read start address settable Write mask function (Input enable control) Data skipping function (Output enable control) Self refresh (No refresh control is required) Package options: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (MS81V26000-xxTB) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time (Min.) Package MS81V26000-12TB 9 ns 12 ns (83 MHz) 100-pin TQFP 2/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VSS DI4 DI5 DI6 DI7 VSS DI8 DI9 DI10 DI11 VSS VCC NC NC VSS VCC VSSQ DO11 DO10 VCCQ DO9 DO8 VSSQ DO7 DO6 PIN CONFIGURATION (TOP VIEW) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VCC VCCQ DO5 DO4 VSSQ VSS DO3 DO2 VCCQ DO1 DO0 VSS VSSQ VCC DO12 DO13 VCCQ DO14 DO15 VSS VSSQ DO16 DO17 VCCQ VCC VSS DI16 DI17 DI18 DI19 VSS DI20 DI21 DI22 DI23 VSS VCC NC NC VSS VCC VSSQ DO23 DO22 VCCQ DO21 DO20 VSSQ DO19 DO18 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC DI3 DI2 DI1 DI0 VSS WAD IE WE RSTW VCC SWCK VSS SRCK VCC RSTR RE OE RAD VSS DI12 DI13 DI14 DI15 VCC 100-Pin TQFP Pin Name SWCK SRCK WE RE IE OE RSTW RSTR Function Serial Write Clock Serial Read Clock Write Enable Read Enable Input Enable Output Enable Write Reset Clock Read Reset Clock WAD Write Address Input RAD Read Address Input DIN0 to 23 DOUT0 to 23 VCC VSS VCCQ VSSQ NC Data Input Data Output Power Supply (3.3 V) Ground (0 V) Power Supply for output Ground for output No Connection Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin, and the same GND voltage level must be provided to every VSS pin and VSSQ pin. 3/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 BLOCK DIAGRAM DO (X24) RAD Data-output Buffer OE Serial RE RSTR Read Controller SRCK Read Data Register (X24) 1,114,112 x 24 X Decoder Memory Read/Write Refresh Timing Generater Array (X24) Refresh Counter Write Data Register Data-input Buffer DI (X24) Serial WAD IE Write WE Controller RSTW SWCK 4/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 PIN DESCRIPTION Serial Write Clock: SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Reset: RSTW RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD. Write Enable: WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MS81V26000 is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 4. After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at address 0 is started after a time tWL form the cycle in which WE is brought high. After write reset, WE should be remained high for 2 cycles after driving WE high first. Input Enable: IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by IE is 4. Write Address Input: WAD These pins are used for write address input. Data Inputs: (DI0-23) These pins are used for serial data inputs. Write Reset: RSTW RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD. Data Out: (DO0-23) These pins are used for serial data outputs. Serial Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restriction on MS81V26000. Read Reset: RSTR RSTR is used to set the internal read address pointer. RSTR setup and hold times are referenced to the rising edge of SRCK. The SWCK latches the read address data (21bits serial LSB) from RAD. Read Enable: RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. 5/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 The latency for the read operation control by RE is 4. After read reset, RE must remain low for more than 1600 ns (tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought high. After read reset, RE should be remained high for 2 cycles after driving RE high first. Output Enable: OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. The latency for the read operation control by OE is 4. Read Address Input: RAD These pins are used for read address input. 6/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Conditon Rating Unit Power Supply Voltage VCC Ta = 25°C –0.5 to +4.6 V Input Output Voltage VT at Ta = 25°C, VSS –0.5 to +4.6 V Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature Topr — 0 to 70 °C Storage Temperature Tstg — –55 to +150 °C Max. Unit Recommended Operating Conditions Parameter Symbol Min. Typ Power Supply Voltage VCC 3.0 3.3 3.6 V Input High Voltage VIH 2.0 VCC VCC + 0.3 V Input Low Voltage VIL –0.3 0 +0.8 V DC Characteristics Parameter Symbol Condition Min. Max. Unit Input Leakage Current ILI 0 < VI < VCC + 0.3 V, Other Pins Tested at V = 0 V –10 +10 µA Output Leakage Current ILO 0 < VO < VCC –10 +10 µA Output “H” Level Voltage VOH IOH = –2 mA 2.4 — V Output “L” Level Voltage VOL IOL = 2 mA — 0.4 V Operating Current ICC1 Minimum Cycle Time, Output Open — 200 mA Standby Current ICC2 Input Pin = VIH/VIL — 5 mA Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Symbol Max. Unit Input Capacitance Parameter CI 6 pF Output Capacitance CO 7 pF 7/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 AC Characteristics (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C) Parameter Access Time from SRCK Symbol MS81V26000-12 Min. Max. Unit tAC — 9 ns DOUT Hold Time from SRCK tDDCK 3 — ns DOUT Enable Time from SRCK tDECK 3 9 ns SWCK “H” Pulse Width tWSWH 4 — ns SWCK “L” Pulse Width tWSWL 4 — ns Input Data Setup Time tDS 3 — ns Input Data Hold Time tDH 1 — ns WE Enable Setup Time tWENS 3 — ns WE Enable Hold Time tWENH 1 — ns WE Disable Setup Time tWDSS 3 — ns WE Disable Hold Time tWDSH 1 — ns IE Enable Setup Time tIENS 3 — ns IE Enable Hold Time tIENH 1 — ns IE Disable Setup Time tIDSS 3 — ns IE Disable Hold Time tIDSH 1 — ns WE “H” Pulse Width tWWEH 4 — ns WE “L” Pulse Width tWWEL 4 — ns IE “H” Pulse Width tWIEH 4 — ns IE “L” Pulse Width tWIEL 4 — ns RSTW Setup Time tRSTWS 3 — ns RSTW Hold Time tRSTWH 1 — ns SRCK “H” Pulse Width tWSRH 4 — ns SRCK “L” Pulse Width tWSRL 4 — ns RE Enable Setup Time tRENS 3 — ns RE Enable Hold Time tRENH 1 — ns RE Disable Setup Time tRDSS 3 — ns RE Disable Hold Time tRDSH 1 — ns OE Enable Setup Time tOENS 3 — ns OE Enable Hold Time tOENH 1 — ns OE Disable Setup Time tODSS 3 — ns OE Disable Hold Time tODSH 1 — ns RE “H” Pulse Width tWREH 4 — ns RE “L” Pulse Width tWREL 4 — ns OE “H” Pulse Width tWOEH 4 — ns OE “L” Pulse Width tWOEL 4 — ns RSTR Setup Time tRSTRS 3 — ns RSTR Hold Time tRSTRH 1 — ns SWCK Cycle Time tSWC 12 — ns SRCK Cycle Time tSRC 12 — ns tT 1 5 ns Transition Time (Rise and Fall) 8/20 FEDS81V26000-02 OKI Semiconductor Parameter MS81V26000 Symbol MS81V26000-12 Min. Max. Unit WE “L” Period before W Reset tLWE 4 — clk RE “L” Period before R Reset tLRE 4 — clk RE Delay after Reset tFRD 1,600 — ns WE Delay after Reset tFWD 1,600 — ns Write address input period TWAE 21 — Clk Read address input period TRAE 21 — clk Latency Parameter Symbol MS81V26000-12 Unit Write Latency tWL 4 clk Read Latency tRL 4 clk WE Write Control Latency tWEL 4 clk IE Write Control Latency tIEL 4 clk RE Read Control Latency tREL 4 clk OE Read Control Latency tOEL 4 clk AC Characteristic Measuring Conditions Output Compare Level Output Load Input Signal Level 1.4 V 1 TTL + 30 pF 2.4 V/0.4 V Input Signal Rise/Fall Time 1 ns Input Signal Measuring Reference Level 1.4 V Note: When transition time tT becomes 1 ns or more, the input signal reference levels for the parameter measurement are VIH (min.) and VIL (max.). 9/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 OPERATION MODE Write Operation Cycle The write operation is controlled by four control signals, SWCK, RSTW, WE and IE. The write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. RSTW must be performed for internal circuit initialization before write operation. WE must be low before and after the reset cycle (tLWE + tWAE + tFWD). Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles while WE and IE are high. Settings of WE and IE to the operation mode of Write address pointer and Data input. WE IE H H H L L X Internal Write address pointer Incremented Halted Data input (Latency 4) Input Not input X indicates "don't care" Read Operation Cycle The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles while RE and OE are high. RE must be low before and after the reset cycle (tLRE + tRAE + tFWD). Settings of RE and OE to the operation mode of read address pointer and Data output. RE OE H H H L L H L L Internal Read address pointer Incremented Halted Data output (Latency 4) Output High impedance Output High impedance Power-up and Initialization To assure proper operation of this Memory, place an interval of at least 200 µs after Vcc has stabilized to a value within the range of recommended operating conditions after power-up prior to the operation start. After this 200 µs stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of 150 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. 10/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 New Data Read Access In order to read out “new data,” i.e., to read out data that has been written in a follow-up manner, read reset must be input after write address 150 and the difference between the read address and the write address must be 350 or more but 1,114,111 or less. Old Data Read Access In order to read out “old data,” i.e., to read out data that was written prior to the write operation being carried out, the difference between the read address and the write address must be 0 or more but 30 or less. If the difference between the read address and the write address is between 31 and 349 or 1,114,112 or more, it is unpredictable whether the new data is output or whether the old data is output. In this case, however, the write data will be written normally. 11/20 IE WE DI 0-23 WAD RSTW SWCK Dn-2 tLWE Dn-1 tWSWL tWSWH Dn tWANS WA1 tWANH tRSTWH WA0 tRSTWS WA2 tWAE W19 WA20 tFWD tWAE (=21clk):Period of Address input from Write Reset. After write reset, WE should be remained high for 2 cycles after driving WE high first. Dn-3 tDS tDH tSWC Write Cycle Timing (Write Reset) TIMING DIAGRAM tWL D0 D1 0 cycle 1 cycle FEDS81V26000-02 OKI Semiconductor MS81V26000 12/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 Write Cycle Timing (Write Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle SWCK tWENH tWWEL tWENS tWWEH WE tWDSH DI 0-23 D0 D1 D2 tWDSS D3 D5 D4 D6 D7 tWEL RSTW “L” “H” IE Write Cycle Timing (Input Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle SWCK tIENH tWIEL tIENS tWIEH IE tIDSH DI 0-23 D0 D1 D2 tIDSS D3 D4 D5 D10 D11 tIEL RSTW WE “L” “H” 13/20 OE RE DO 0-23 RAD RSTR SRCK tLRE Qn-2 Qn-1 tWSRL tWSRH Qn tRANS RA1 tRANH tRSTRH RA0 tRSTRS RA2 tRAE RA19 RA20 tRAE (=21clk): Period of Address input from Read Reset. After read reset, RE should be remained high for 2 cycles after driving RE high first. “H” Qn-3 tSRC Read Cycle Timing (Read Reset) tFRD tRL tAC Q0 0 cycle 1 cycle Q1 FEDS81V26000-02 OKI Semiconductor MS81V26000 14/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 Read Cycle Timing (Read Enable) 1 cycle 2 cycle 3 cycle 4 cycle 6 cycle 7 cycle 5 cycle SRCK tRENH tWREL tRENS tWREH RE tRDSH DO 0-23 Q0 Q1 Q2 tAC tRDSS Q4 Q3 Q5 Q6 Q7 tREL RSTR “L” OE “H” Read Cycle Timing (Output Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle SRCK tOENH tWOEL tWOEH tOENS OE tAC tODSH DO 0-23 Q0 Q1 Q2 tODSS Q3 Q4 tDDCK Q5 tDECK Q10 Q11 tOEL RSTR “L” RE “H” 15/20 tWAE + tFWD tWL A1 2 tLRE Xn n tRAE + tFRD tRL tAC 0 Address difference is 350 or more and 1,114,111 or less. 148 149 150 151 152 Read Reset should be input after write address 150. A0 1 The setting address for reading and that for writing are the same. “H” “H” Xn-3 Xn-2 Xn-1 Xn tLWE 0 A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 OKI Semiconductor OE DO 0-23 RE RSTR SRCK IE DI 0-23 WE RSTW SWCK n Read / Write Cycle Timing (New Data Read) FEDS81V26000-02 MS81V26000 16/20 tWAE + tFWD tWL tLRE n Xn A0 1 A2 3 A3 4 A4 tRAE + tFRD tRL Address difference is 30 or less. A1 2 The setting address for reading and that for writing are the same. “H” “H” Bn-3 Bn-2 Bn-1 Bn tLWE 0 0 B0 1 B1 2 B2 3 B3 4 B4 OKI Semiconductor OE DO 0-23 RE RSTR SRCK IE DI 0-23 WE RSTW SWCK n Read / Write Cycle Timing (Old Data Read) FEDS81V26000-02 MS81V26000 17/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 PACKAGE DIMENSIONS (Unit: mm) TQFP100-P-1414-0.50-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.55 TYP. 4/Oct. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 REVISION HISTORY Document No. Date Page Previous Current Edition Edition Description FEDS81V26000-01 May 14, 2004 Final edition 1 FEDS81V26000-01 Dec 15, 2004 20 20 P17 DI0-23 XnÆBn 19/20 FEDS81V26000-02 OKI Semiconductor MS81V26000 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd. 20/20