OKI MSM51V17800F

FEDD51V17800F-01
1Semiconductor
MSM51V17800F
This version: January. 2001
Previous version : 
2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM51V17800F is a 2,097,152-word × 8-bit dynamic RAM fabricated in Oki’s silicon-gate
CMOS technology. The MSM51V17800F achieves high integration, high-speed operation, and lowpower consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MSM51V17800F is available in a 28-pin plastic SOJ or 28-pin plastic TSOP.
FEATURES
∙ 2,097,152-word × 8-bit configuration
∙ Single 3.3V power supply, ±0.3V tolerance
∙ Input : LVTTL compatible, low input capacitance
∙ Output : LVTTL compatible, 3-state
∙ Refresh : 2048 cycles/32ms
∙ Fast page mode, read modify write capability
∙ CAS before RAS refresh, hidden refresh, RAS-only refresh capability
∙ Packages
(SOJ28-P-400-1.27)
28-pin 400mil plastic SOJ
(Product : MSM51V17800F-xxJS)
(TSOPII28-P-400-1.27-K)
28-pin 400mil plastic TSOP
(Product : MSM51V17800F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Family
MSM51V17800F
tRAC
tAA
tCAC
tOEA
Cycle Time
(Min.)
50ns
60ns
70ns
25ns
30ns
35ns
13ns
15ns
20ns
13ns
15ns
20ns
90ns
110ns
130ns
Power Dissipation
Operating
(Max.)
360mW
324mW
288mW
Standby
(Max.)
1.8mW
1/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
PIN CONFIGURATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
RAS 7
NC 8
A10R 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin Plastic SOJ
Pin Name
VSS
DQ8
DQ7
DQ6
DQ5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
RAS 7
NC 8
A10R 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ8
DQ7
DQ6
DQ5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
28-Pin Plastic TSOP
(K Type)
Function
A0–A9, A10R
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1–DQ8
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (3.3V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must
be provided to every VSS pin.
2/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
BLOCK DIAGRAM
Timing
Generator
RAS
WE
OE
I/O
Controller
CAS
8
Output
Buffers
8
DQ1 – DQ8
10
10
Internal
Address
Counter
A0 – A9
10
A10R
Column
Address
Buffers
1
Row
Address
Buffers
Refresh
Control Clock
11
Row
Decoders
Word
Drivers
Column Decoders
Sense Amplifiers
8
8
I/O
Selector
Input
Buffers
8
8
Memory
Cells
VCC
On Chip
VBB Generator
On Chip
IVCC Generator
VSS
3/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage VCC Supply relative to VSS
VT
–0.5 to 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
*: Ta = 25°C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
3.0
3.3
3.6
V
VSS
0
0
0
V
VIH
2.0

VCC + 0.3*1
V
VIL
− 0.3

0.8
V
*2
Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
*2. The input voltage is VSS − 1.0V when the pulse width is less than 20ns (the pulse width respect to the
point at which VSS is applied).
PIN CAPACITANCE
(Vcc = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min.
Max.
Unit
CIN1
—
5
pF
(RAS, CAS, WE, OE)
CIN2
—
7
pF
Output Capacitance (DQ1 – DQ8)
CI/O
—
7
pF
Input Capacitance (A0 – A9, A10R)
Input Capacitance
4/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min.
Max.
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
0
0.4
V
All other pins not
under test = 0V
− 10
10
− 10
10
− 10
10
µA
DQ disable
− 10
10
− 10
10
− 10
10
µA

100

90

80
mA
RAS, CAS = VIH

2

2

2
mA
RAS, CAS
≥ VCC − 0.2V

0.5

0.5

0.5
µA

100

90

80
mA
1,2

5

5

5
mA
1

100

90

80
mA
1,2

75

70

65
mA
1,3
Output High Voltage
VOH
IOH = −2.0mA
Output Low Voltage
VOL
IOL = 2.0mA
0V ≤ VI ≤ VCC + 0.3V;
Input Leakage
Current
ILI
Output Leakage
Current
ILO
Average Power
Supply Current
ICC1
(Operating)
Power Supply
Current
ICC2
(Standby)
Average Power
Supply Current
0V ≤ VO ≤ VCC
RAS, CAS cycling,
tRC = Min.
CAS = VIH,
tRC = Min.
Power Supply
Current
RAS = VIH,
ICC5
(Standby)
(CAS before RAS
Refresh)
Average Power
Supply Current
(Fast Page Mode)
1,2
1
RAS cycling,
ICC3
(RAS-only Refresh)
Average Power
Supply Current
MSM51V17800 MSM51V17800 MSM51V17800
F-50
F-60
F-70
Unit Note
CAS = VIL,
DQ = enable
ICC6
RAS = cycling,
CAS before RAS
RAS = VIL,
ICC7
CAS cycling,
tPC = Min.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
5/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
AC CHARACTERISTICS (1/2)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3
Parameter
Symbol
MSM51V17800
F-50
MSM51V17800
F-60
MSM51V17800
F-70
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
90

110

130

ns
tRWC
131

155

185

ns
tPC
35

40

45

ns
Fast Page Mode Read Modify Write
tPRWC
Cycle Time
76

85

100

ns
Access Time from RAS
tRAC

50

60

70
ns
4, 5, 6
Access Time from CAS
tCAC

13

15

20
ns
4, 5
Access Time from Column Address
tAA

25

30

35
ns
4, 6
Access Time from CAS Precharge
tCPA

30

35

40
ns
4, 12
Access Time from OE
tOEA

13

15

20
ns
4
Output Low Impedance Time from
CAS
tCLZ
0

0

0

ns
4
CAS to Data Output Buffer Turnoff Delay Time
tOFF
0
13
0
15
0
20
ns
7
OE to Data Output Buffer Turn-off
Delay Time
tOEZ
0
13
0
15
0
20
ns
7
Transition Time
tT
3
50
3
50
3
50
ns
3
Refresh Period
tREF

32

32

32
ms
RAS Precharge Time
tRP
30

40

50

ns
RAS Pulse Width
tRAS
50
10,000
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode) tRASP
50
100,000
60
100,000
70
100,000 ns
RAS Hold Time
tRSH
13

15

20

ns
RAS Hold Time referenced to OE
tROH
13

15

20

ns
CAS Precharge Time
(Fast Page Mode)
tCP
7

10

10

ns
CAS Pulse Width
tCAS
13
10,000
15
10,000
20
10,000
ns
CAS Hold Time
tCSH
50

60

70

ns
CAS to RAS Precharge Time
tCRP
5

5

5

ns
RAS Hold Time from CAS Precharge tRHCP
30

35

40

ns
RAS to CAS Delay Time
tRCD
17
37
20
45
20
50
ns
5
RAS to Column Address Delay Time
tRAD
12
25
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0

0

0

ns
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
6/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
AC CHARACTERISTICS (2/2)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3
Parameter
Symbol
MSM51V17800
F-50
MSM51V17800
F-60
MSM51V17800
F-70
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Note
Row Address Hold Time
tRAH
7

10

10

ns
Column Address Set-up Time
tASC
0

0

0

ns
Column Address Hold Time
tCAH
7

10

15

ns
Column Address to RAS Lead Time
tRAL
25

30

35

ns
Read Command Set-up Time
tRCS
0

0

0

ns
Read Command Hold Time
tRCH
0

0

0

ns
8
Read Command Hold Time
referenced to RAS
tRRH
0

0

0

ns
8
Write Command Set-up Time
tWCS
0

0

0

ns
9
Write Command Hold Time
tWCH
7

10

15

ns
Write Command Pulse Width
tWP
7

10

10

ns
OE Command Hold Time
tOEH
13

15

20

ns
Write Command to RAS Lead Time
tRWL
13

15

20

ns
Write Command to CAS Lead Time
tCWL
13

15

20

ns
Data-in Set-up Time
tDS
0

0

0

ns
10
Data-in Hold Time
tDH
7

10

15

ns
10
OE to Data-in Delay Time
tOED
13

15

20

ns
CAS to WE Delay Time
tCWD
36

40

50

ns
9
Column Address to WE Delay Time
tAWD
48

55

65

ns
9
RAS to WE Delay Time
tRWD
73

85

100

ns
9
tCPWD
53

60

70

ns
9
CAS Active Delay Time from RAS
Precharge
tRPC
5

5

5

ns
RAS to CAS Set-up Time
(CAS before RAS)
tCSR
10

10

10

ns
RAS to CAS Hold Time
(CAS before RAS)
tCHR
10

10

10

ns
WE to RAS Precharge Time
(CAS before RAS)
tWRP
10

10

10

ns
WE Hold Time from RAS
(CAS before RAS)
tWRH
10

10

10

ns
RAS to WE Set-up Time
tWTS
10

10

10

ns
RAS to WE Hold Time
tWTH
10

10

10

ns
CAS Precharge WE Delay Time
7/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 5ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)
are measured between VIH and VIL.
4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 1 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,
then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,
then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and
are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD
(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
8/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
TIMING CHART
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRAD
VIL
WE
OE
VIH
VIL
tCRP
tRSH
tCAS
VIH
tRAL
tASR
Address
tRCD
tRAH
tASC
Row
tCAH
Column
tRRH
tRCS
VIH
tAA
VIL
tOEA
VIH
VIL
tCAC
tRAC
DQ
tRCH
tROH
tOFF
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
Write Cycle (Early Write)
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
OE
DQ
VIH
VIL
VIH
tCRP
tRSH
tCAS
tRAH
tASC
Row
tCAH
Column
tCWL
tWCS
tWP
tWCH
VIL
tRWL
VIH
VIL
VIH
VIL
tDS
tDH
Valid Data-in
Open
“H” or “L”
9/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
Read Modify Write Cycle
tRWC
RAS
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
VIH
VIH
VIL
tCRP
tRSH
tCAS
tRAD
VIL
tASR
Address
tRCD
tRAH
Row
tASC
tCWL
tRWL
tCAH
Colum
tRCS
tCWD
tWP
tRWD
WE
OE
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
tDH
Valid
Data-in
“H” or “L”
10/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
Fast Page Mode Read Cycle
tRASP
RAS
VIH
VIL
tRCD
tCRP
CAS
tCP
VIH
VIL
tRAH tASC
Row
Column
tCAH
tRCH
tCRP
tCAH
Column
tRCS
tRCH
tRCS
tRCH
VIH
VIL
tAA
tAA
tAA
tOEA
VIH
VIL
tCPA
tOFF
tOEZ
tRAC
tCAC
DQ
tASC
Column
tOEA
OE
tRSH
tCAS
tRAL
tASC
tCAH
tRCS
WE
tCP
tCAS
tRAD
tCSH
VIL
VIH
tRHCP
tCAS
tASR
Address
tRP
tPC
tCLZ
VOH
tCPA
tOFF
tCAC
tOFF
tCAC
tOEZ
tOEZ t
CLZ
tCLZ
Valid
Data-out
Valid
Data-out
VOL
tRRH
tOEA
Valid
Data-out
“H” or “L”
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
CAS
VIH
VIL
tCRP
tCAS
tRAH tASC
Row
tCSH
tCAH
tASC
Column
tCRP
tASC
tRAL
tCAH
Column
tRWL
tWCS
VIH
tWCH
tWP
tCWL
tWCS
tWCH
tWP
tCWL
tWCS
tWP
tWCH
VIL
tDS
DQ
tCAH
Column
tCWL
WE
tRSH
tCAS
tRAD
VIL
VIL
tCP
tCAS
tASR
Address
tCP
tRCD
VIH
VIH
tRHPC
tPC
VIH
VIL
tDH
Valid *
Data-in
tDS
tDH
Valid *
Data-in
tDS
tDH
Valid *
Data-in
Note: OE = “H” or “L”
“H” or “L”
11/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
CAS
tCSH
VIH
VIL
tRCD
VIL
tCAH
tCWL
tASC
Row
tCAH
tASC
tRAL
tCWL
Column
tRCS
tPWD
tCWD
Column
tRCS
tCPWD
tCWL
tCPWD
tCWD
tCWD
tAWD
tAWD
tRWL
VIH
tAWD
VIL
tWP
tAA
VIH
tCAC
tAA
Out
tCLZ
tCAC
tDS
tOED
tOEZ
tCAC
tDS
Out
In
tDH
tOEA
tOED
tOEZ
tOEZ
VI/OH
VI/OL
tCPA
tOEA
tOED
VIL
tROH
tDH
tAA
tDS
tWP
tWP
tCPA
tDH
tOEA
DQ
tCRP
tCAS
tASC
Column
tRAC
OE
tCP
tCAS
tCAH
VIL
VIH
tRP
tRSH
tRAD
tRCS
WE
tCP
tCAS
VIH
tRAH
tASR
Address
tPRWC
In
Out
In
tCLZ
tCLZ
Note: In = Valid Data-in, Out = Valid Data-out
“H” or “L”
RAS-only
Refresh Cycle
RAS
tRC
RAS
tRAS
VIH
tRP
VIL
tCRP
CAS
Address
DQ
tRPC
VIH
VIL
VIH
VIL
VOH
VOL
tASR tRAH
Row
tOFF
Open
Note: WE, OE = “H” or “L”
“H” or “L”
12/15
FEDD51V17800F-01
1Semiconductor
MSM51V17800F
CAS before RAS Refresh Cycle
tRP
RAS
CAS
WE
tRC
tRAS
VIH
tRPC
tCP
VIL
tRP
tCSR
tRPC
tCHR
VIH
VIL
tWRP
tWRH
tWRP
VIH
VIL
tCEZ
DQ
VOH
Open
VOL
Note: OE, Address = “H” or “L”
“H” or “L”
Hidden Refresh Read Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRAS
tRCD
tRSH
VIH
VIH
VIL
tRAH
tASC
Row
tCAH
Column
tCAC
VIH
VIL
DQ
tRAL
tREZ
VIL
VOL
tWRP tWRH
tCEZ
tOEA
VIH
VOH
tRRH
tAA
tROH
OE
tRP
tRAD
VIL
tRCS
WE
tRP
tCHR
tASR
Address
tRC
tRAS
tRAC
tOEZ
tCLZ
Open
Valid Data-out
“H” or “L”
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FEDD51V17800F-01
1Semiconductor
MSM51V17800F
Hidden Refresh Write Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
WE
tRCD
DQ
tRSH
tRP
tRP
VIH
tRAD
VIL
VIH
VIL
tRAH
tASC
Row
tCAH
Column
tRAL
tRWL
tWP
VIH
VIL
tWCS
OE
tRAS
tCHR
tASR
Address
tRC
tRAS
tWCH
tWRP
tWRH
VIH
VIL
VIH
tDS
tDH
Valid Data-in
VIL
“H” or “L”
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FEDD51V17800F-01
1Semiconductor
MSM51V17800F
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
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