E2E1035-27-Y2 ¡ Semiconductor MSM6636B ¡ Semiconductor This version:MSM6636B Jan. 1998 Previous version: Nov. 1996 SAE-J1850 Multiplex Communication Protocol Conformity Transmission Controller for Automotive LAN GENERAL DESCRIPTION The MSM6636B is a transmission controller for automotive LAN based on data communication protocol SAE-J1850. This device can realize a data bus topology bus LAN system with a PWM bit encoding method (41.6 kbps). In addition to a protocol control circuit, MSM6636B has an enclosed quartz oscillation circuit, host CPU interface (parallel interface), a transmit/receive buffer, and a bus receiver circuit that decreases the burden on the host CPU. FEATURES • Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued August 12, 1991) • Non-destructive collision and priority control using CSMA/CD • Internal transmit buffer (1 frame) and receive buffer (2 frames) • Modulating/demodulating: PWM (Pulse Width Modulation) • Transmission speed: 41.6 kbps • Multi-address setting with physical addressing: 1 type / functional addressing: 15 types • Address filter function by multi-addressing (broadcasting possible) • Automatic retransmission function by arbitration loss and non ACK • Three types of in-frame response support: q Single-byte response from a single node w Multi-byte response from a single node (with CRC code) e Single-byte response from multiple nodes (ID response as ACK) • Error detection by cyclic redundancy check (CRC) • Various communication error detections • Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function • Host CPU interface is accessed in parallel • Sleep function Low current consumption mode by oscillation stop (IDS Max < 50µA) SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus • Package: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6636BGS-K) 1/13 ¡ Semiconductor MSM6636B BLOCK DIAGRAM Buffer Register CPU Parallel Interface Receive Register Receive Buffer Address Register Clock Generator S-P Converter CRC Checker PWM Decoder Degital Filter Bus Receiver Receive Controller Transmission Register Transmission Controller CRC Generator P-S Converter LAN Bus Input Address Filter Status Register Response Register x'tal LAN Controller PWM Encoder LAN Bus Output MSM6636B 2/13 ¡ Semiconductor MSM6636B PIN CONFIGURATION (TOP VIEW) WR RD ALE INT RES AVDD BO– BI– BI+ BO+ AGND DGND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DVDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CS OSC0 OSC1 24-Pin Plastic SOP PIN DESCRIPTION Pin Symbol Type Description 1 WR I Data write enable input pin 2 RD I Data read enable input pin 3 ALE I Address latch input pin 4 INT O Interrupt output pin Reset input pin 5 RES I 6 AVDD — Analog power supply voltage 7 BO– O LAN—BUS output – 8 BI– I LAN—BUS input – 9 BI+ I LAN—BUS input + 10 BO+ O LAN—BUS output + 11 AGND — Analog ground pin 12 DGND — Digital ground pin 13 OSC1 O Crystal (or ceramic resonator) oscillation output 14 OSC0 I Crystal (or ceramic resonator) oscillaiton input 15 CS I Chip select input pin 16-23 AD0-7 I/O Address input/data input-output pin 24 DVDD — Digital power supply voltage 3/13 ¡ Semiconductor MSM6636B ABSOLUTE MAXIMUM RATINGS DGND=AGND=0V Symbol Condition Rating Unit DVDD, AVDD — –0.3 to +7.0 V Input Voltage VI AVDD=DVDD –0.3 to DVDD+0.3 V Output Voltage VO AVDD=DVDD –0.3 to DVDD+0.3 V PD(SOP)*1 Ta=25°C 780 mW TSTG — –55 to +150 °C Parameter Power Supply Voltage Power Dissipation Storage Temperature *1 24-pin SOP package power dissipation Power Dissipation Curve Power dissipation PD(SOP) [mW] < 24-pin SOP package> 1000 780 500 –40 25 125 150 Ambient temperature Ta (°C) 4/13 ¡ Semiconductor MSM6636B RECOMMENDED OPERATING CONDITIONS DGND=AGND=0V Parameter Symbol Condition Range Unit Power Supply Voltage DVDD, AVDD AVDD=DVDD 4.5 to 5.5 V Operating Frequency fOSC DVDD=AVDD=5V±10% 2 to 16 MHz Ambient Temperature Ta — –40 to +85 °C ELECTRICAL CHARACTERISTICS DC Characteristics Parameter "H" Input Voltage Symbol VIH1 DVDD=AVDD=5V±10%, DGND=AGND=0V, Ta=–40 to +85°C Applied pin (see below Condition Unit Min. Typ. Max. for A-E) — A DVDD ¥ 0.8 — DVDD+0.3 V "L" Input Voltage VIL1 — A DGND–0.3 — DVDD ¥ 0.2 V "H" Input Voltage VIH2 — E DVDD ¥ 0.7 — DVDD+1.0 V "L" Input Voltage VIL2 — E DGND–1.0 — DGND ¥ 0.3 V "H" Input Voltage VIH3 — B 2.4 — V "L" Input Voltage VIL3 — B –0.3 — 0.8 V Receiver Hysteresis Width VH — E 100 — 400 mV "H" Input Current IIH1 VI=VDD B — — +1 mA "L" Input Current IIL1 VI=0V B — — –1 mA "H" Input Current IIH2 VI=VDD RES — — +1 mA "L" Input Current IIL2 VI=0V RES — — –100 mA "H" Input Current IIH3 VI=VDD BI (+) — — +100 mA "L" Input Current IIL3 VI=0V BI (–) — — –100 mA VOH1 IO=–400µA C, AD0–7 DVDD–0.4 — — V "L" Output Voltage VOL1 IO=+3.2mA C, AD0–7 — — DGND+0.4 V "H" Output Voltage VOH2 IO=–4.0mA D DVDD–0.4 — — V "L" Output Voltage VOL2 IO=+4.0mA D — — DGND+0.4 V GND Offset Voltage VOFF — — — — ±1 V Current Consumption 1 IDS During sleep — — *1 50 mA — — — 10 mA "H" Output Voltage Current Consumption 2 IDD f=16MHz, no load DVDD+0.3 A: RES, CS B: ALE, WR, RD, AD0-7 C: INT D: BO–, BO+ E: BI–, BI+ *1 Typ.=0.2mA when VDD=5V, f=16 MHz, Ta=25°C 5/13 ¡ Semiconductor MSM6636B AC Chacteristics • PWM bit timing DVDD=AVDD=5V±10%, Ta=–40 to +85°C, In setting 41.6 kbps Parameter Transmit Symbol Bit Length "1" Dominant Width "0" Dominant Width "SOF" Dominant Width "SOF, BRK" Length "BRK" Dominant Width "EOD" + Bit Length "EOF" + Bit Length "EOF + IFS" " + Bit Length "0" Passive Width TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 Receive min typ max min max 23.64 6.90 14.87 30.54 47.28 38.42 47.28 70.92 94.56 8.86 24.00 7.00 15.00 31.00 48.00 39.00 48.00 72.00 96.00 9.00 24.36 7.11 15.23 31.47 48.72 39.59 48.72 — — 9.14 21.00 5.00 13.00 29.00 45.00 37.00 43.00 69.00 86.00 4.00 28.00 12.00 20.00 36.00 52.00 44.00 51.00 76.00 — 15.00 Unit ms ms ms ms ms ms ms ms ms ms Note: The sending timing in the above table does not include the delay of the bus drivers. Dominant "1" Passive TP2 Dominant "0 " Passive TP3 TP1 TP10 Dominant " SOF " Passive TP4 TP5 Dominant " EOD " Passive LAST BIT EOD TP7 " EOF " " IFS " Dominant Passive LAST BIT EOF IFS TP8 TP9 Dominant " BRK " Passive TP6 TP5 6/13 ¡ Semiconductor MSM6636B • CPU parallel interface timing DVDD=AVDD=5V±10%, Ta=–40 to +85°C Parameter Symbol Measuring condition Min. Max. ALE Pulse Width tAW 65 — Address Setup Time tAS 65 — Address Hold Time tAH 5 — CS Setup Time tCSS 50 — RD Setup Time tRDS 20 — Continuous Read Cycle Time tRDCY 160 — RD Output Enable Delay Time tRD — 70 — 50 75 — RD Output Floating Delay Time tRDH RD Pulse Width tRDW RD Hold Time at Read tRCSH 0 — WR Setup Time tWRS 100 — Continuous Write Cycle Time tWRCY 160 — WR Pulse Width tWRW 75 — Data Setup Time tDS 100 — Data Hold Time tDH 40 — tWCSH 50 — CS Hold Time at Write CL=50pF Unit ns 7/13 ¡ Semiconductor MSM6636B Parallel Interface Timing tAW ALE tRDS tAS AD0-7 tAH Address Data Output tRD tCSS tRDH CS tRDW tRCSH RD Read Timing ALE AD0-7 tWRS Address Data Input tDS tDH CS tWRW tWCSH WR Write Timing 8/13 ¡ Semiconductor MSM6636B Timing When Automatic Address Increment is Used ALE AD0-7 tRDS Address Data Output tRD tRDCY CS Data Output Data Output tRDH tRDW RD Read Timing ALE AD0-7 tWRS Address Data Input tDS CS Data Input Data Input tDH tWRCY tWRW WR Write Timing 9/13 ¡ Semiconductor MSM6636B • Wakeup input signal DVDD=AVDD=5V±10%, Ta=–40 to +85°C Symbol Min. Typ. Max. Unit LAN bus Passive Æ Dominant Change Pulse Width Parameter tWD 7 — — ms RXD Terminal Input Pulse Width tWR 400 — — ns Bus Receiver Stable Time *1 tRS 1 — — ms *1 The stable time of the bus receiver is from just after wakeup to the restart of message transmission and reception. However, the clock oscillation source should use an external clock. (A clock is input even in the sleep status.) tWD tWD tWD BI+ BI– RXD tWR Note: The time chart shows the wakeup input signals from each sleep status. 10/13 ¡ Semiconductor MSM6636B • Fault tolerant function operation conditions DVDD=AVDD=5V±10%, Ta=–40 to +85°C, In setting 41.6 kbps Parameter Symbol Min. Typ. Max. Unit LAN bus (+) GND Short Circuit Detection Pulse Width tPG 5 — — ms LAN bus (+) VDD Short Circuit Detection Pulse Width tPV 48 — — ms LAN bus (–) GND Short Circuit Detection Pulse Width tNG 48 — — ms LAN bus (–) VDD Short Circuit Detection Pulse Width tNV 5 — — ms BUS(+) BUS(–) tPG tPV tNV tNG BUS(+) BUS(–) • Reset input pulse width DVDD=AVDD=5V±10%, Ta=–40 to +85°C Parameter Reset Input Pulse Width Symbol Min. Typ. Max. Unit tRES 0.1 — — ms RES tRES Note: The oscillation stable time after power ON is determined by the crystal used and the parasitic capacitance generated by connection. Make tRES greater than or equal to the oscillation stable time. In the table above, the reset input pulse width indicates the minimum pulse width when oscillation is stable after power is turned on. 11/13 ¡ Semiconductor MSM6636B APPLICATION CIRCUIT Host CPU and J1850 Line Bus Connection Example Unit A Host CPU MSM6636B RS DVDD AVDD AD0-7 ALE ALE BO (+) WR RD WR BI (+) PXX CS RD INT CLKOUT RES AD0-7 INT OSC0 RB RR C *1 BI (–) BO (–) OPEN OSC1 RES DGND AGND RR ZD RB RS ZD Unit B RP . . . RD Bus + Bus – An optimum system can be constructed by selecting an optimum host CPU and combining it with the MSM6636B. *1 Insert a capacitor between the power supply and GND to prevent supply noise. It is recommended to connect a small-capacitance bypass capacitor and a large-capacitance filter capacitor serially. The typical capacitors are as follows: 0.01 to 0.22 mF : Ceramic capacitor 10 to 100 mF : Tantalum capacitor 12/13 ¡ Semiconductor MSM6636B PACKAGE DIMENSIONS (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/13