E2U0038-28-81 ¡ Semiconductor MSM7620 ¡ Semiconductor This version: Aug. 1998 MSM7620 Previous version: Nov. 1996 Echo Canceler GENERAL DESCRIPTION The MSM7620 is an improved version of the MSM7520 with the same basic configuration. The MSM7620 includes following improvements: a modified through mode, timing control of the control pin input, and a thinner package. The MSM7620 also provides a pin-for-pin replacement with the MSM7520. The MSM7620 is a low-power CMOS IC device for canceling echo (in an acoustic system or telephone line) generated in a speech path. Echo is canceled (in digital signal processing) by estimating the echo path and generating a pseudo-echo signal. Used as an acoustic echo canceler, the MSM7620 cancels the acoustic echo between the loud speaker and the microphone which occurs during hands free communication, such as on a car phone or a conference system phone. Used as a line echo canceler, the device cancels the line echo impedance mismatching in a hybrid. In addition, a quality conversation is made possible by controlling the level and preventing howling with a howling detector, double talk detector, attenuation function and a gain control function, and by controlling the low level noise with a center clipping function. The MSM7620 I/O interface supports m-law PCM. The use of a single chip CODEC, such as the MSM7543, allows the configuration an economic and efficient echo canceler to be configured. Note: If the object is to cancel line echo, the use of the MSM7602 is recommended, for the MSM7602 is provided with a howling detect control pin. In addition, the MSM7602, while having characteristics equivalent to the MSM7620, is packaged small. FEATURES • Handles both acoustic echoes and telephone line echoes. • Cancelable echo delay time: MSM7620-001 ................. For a single chip: 23 ms (max.) MSM7620-011 ................. For a cascade connection (can also be used for a single chip) Master chip: 23 ms (max.) Slave chip: 31 ms (max.) Cancelable up to 213 ms (one master plus six slaves) For a single chip: 23 ms (max.) • Echo attenuation : 30 dB (typ.) • Clock frequency : 18 MHz (36 MHz cannot be used) External input and internal oscillator circuit are provided. • Power supply voltage : 5 V (4.5 V to 5.5 V) • Power consumption : 150 mW (typ.) When powered down: 20 mW (typ.) • Package options: 32-pin plastic SSOP (SSOP32-P-640-0.80-K) (Product name : MSM7620-001GS-K) 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name : MSM7620-011GS-BK) 1/28 ¡ Semiconductor MSM7620 BLOCK DIAGRAM MSM7620-001 (Single chip only) RIN S/P Howling Detector Non-linear/ Linear ATT Double Talk Detector Linear/ Non-linear Gain Power Calculator P/S ROUT Adaptive FIR Filter (AFF) – SOUT P/S RST PWDWN Clock Generator X1/CLKIN Center Clip Linear/ Non-linear + ATT + Non-linear/ S/P Linear WDT , X2 SCKO Mode Selector I/O Controller IRLD SYNCO NLP HCL ADP ATT GC SIN INT VDD VSS SCK SYNC MSM7620-011 (Cascade connection or Single chip) RIN S/P Howling Detector Non-Linear /Linear ATT Double Talk Detector Linear/ Non-linear Gain Power Calculator P/S ROUT PD15 * Parallel I/O Port PD 0 * Parallel I/O Controller OF1 * OF2 * SF1 * SF2 * Adaptive FIR Filter (AFF) – SOUT P/S *RST *PWDWN Linear/ Non-linear Clock Generator X1/CLKIN * X2 SCKO Center Clip ATT + + Non-linear/ Mode Selector I/O Controller SYNCO NLP HCL ADP ATT GC MS IRLD * S/P Linear * INT SIN WDT VDD * VSS * SCK SYNC * * If the MSM7620-011 is used in the slave mode, only the diagonally hatched blocks and the pins marked with * are used. 2/28 ¡ Semiconductor MSM7620 PIN CONFIGURATION (TOP VIEW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 32-Pin Plastic SSOP Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 * 9 SIN 17 * 25 SCKO 2 NLP 10 RIN 18 * 26 * 3 HCL 11 SCK 19 * 27 RST 4 ADP 12 SYNC 20 X1/CLKIN 28 WDT 5 VSS 13 SOUT 21 X2 29 GC 6 ATT 14 ROUT 22 * 30 * 7 INT 15 * 23 PWDWN 31 * 8 IRLD 16 VSS 24 SYNCO 32 VDD *: No connect pin Note: Pin 26 of the MSM7520 is CKSEL, while that of the MSM7620 is in open state. It is possible to replace the MSM7520 with the MSM7620. 3/28 ¡ Semiconductor MSM7620 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-Pin Plastic SSOP Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 NLP 17 * 33 PD12 49 * 2 HCL 18 * 34 PD13 50 * 3 ADP 19 PD0 35 X1/CLKIN 51 PD14 4 MS 20 PD1 36 X2 52 PD15 5 ATT 21 PD2 37 * 53 * 6 INT 22 PD3 38 PWDWN 54 SF2 7 * 23 PD4 39 * 55 OF1 8 IRLD 24 PD5 40 SYNCO 56 * 9 * 25 PD6 41 SCKO 57 * 10 SIN 26 PD7 42 * 58 * 11 RIN 27 PD8 43 * 59 SF1 12 SCK 28 PD9 44 RST 60 OF2 13 SYNC 29 PD10 45 WDT 61 * 14 SOUT 30 PD11 46 GC 62 VDD 15 ROUT 31 * 47 VDD 63 * 16 VSS 32 * 48 VDD 64 * *: No connect pin Note: Pins 43, 53, and 61 of the MSM7520 are CKSEL, VDD, and TST2 respectively. While these pins of the MSM7620 are in open state, it is possible to replace the MSM7520 with the MSM7620. 4/28 ¡ Semiconductor MSM7620 PIN DESCRIPTIONS (1/5) Pin 32-pin 64-pin SSOP 2 QFP 1 Symbol Type NLP I Description The control pin for the center clipping function. This forces the SOUT output to a minimum value (FF) when the SOUT signal is below -54 dBm0. Effective for reducing low-level noise. • Single Chip or Master Chip in a Cascade Connection "H": Center clip ON "L": Center clip OFF • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 3 2 HCL I The through mode control. When this pin is in the through mode, RIN and SIN data are output to ROUT and SOUT. At the same time, the coefficient of the adaptive FIR filter is cleared. • Single Chip or Master Chip in a Cascade Connection "H": Through mode "L": Normal mode (echo canceler operates) • Slave Chip in a Cascade Connection Same as master This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 4 3 ADP I AFF coefficient control pin. This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. This pin is used when holding the AFF coefficient which has been once converged. • Single Chip or Master Chip in a Cascade Connection "H": Coefficient fix mode "L": Normal mode (coefficient update) • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. — 4 MS I Selection of the Master Chip and slave chip when used in a cascade connection. "L": Single chip or master chip "H": Slave chip 5/28 ¡ Semiconductor MSM7620 (2/5) Pin 32-pin 64-pin SSOP QFP 6 5 Symbol Type Description ATT I Control for the ATT function that prevents howling by attenuators (ATT) for the RIN input and SOUT output. If there is input only to RIN, then the ATT for the SOUT output is activated. If there is no input to SIN, or if there is input to both SIN and RIN, the ATT for the RIN input is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. • Single Chip or Master Chip in a Cascade Connection "H": ATT OFF "L": ATT ON "L" is recommended for echo cancellation. • Slave Chip in a Cascade Connection • Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 7 6 INT I Interrupt signal which starts 1 cycle (8 kHz) of the signal processing. Signal processing starts when H-to-L transition is detected. • Single Chip or Master Chip in a Cascade Connection Connect the IRLD pin. • Slave Chip in a Cascade Connection Connect the IRLD pin of the master chip. INT input is invalid for 100 ms after reset due to initialization. Refer to the control pin connection example. 8 8 IRLD O Load detection signal when the SIN and RIN serial input data is loaded in the internal registers. • Single Chip Connect to the INT pin. • Master Chip in a Cascade Connection Connect to the INT pin of the master chip and all the slave chips. • Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. 9 10 SIN I Transmit serial data. Input the m-law PCM signal synchronized to SYNC and SCK. Data is read in at the fall of SCK. 6/28 ¡ Semiconductor MSM7620 (3/5) Pin 32-pin 64-pin Symbol Type SSOP QFP 10 11 RIN I 11 12 SCK I Description Receive serial data. Input the m-law PCM signal synchronized to SYNC and SCK. Data is read in at the fall of SCK. Clock pin for transmit/receive serial data. This pin uses the external SCK or the SCKO. Input the PCM CODEC transmit/receive clock (64 to 2048 kHz). 12 13 SYNC I Sync signal for transmit/receive serial data. This pin uses the external SYNC or SYNCO. Input the PCM CODEC transmit/receive sync signal (8 kHz). 13 14 SOUT O Transmit serial data. This pin outputs the m-law PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state while there is no data output. 14 15 ROUT O Receive serial data. This pin outputs the m-law PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state while there is no data output. — 19 PD0 I/O Bidirectional bus for parallel data transfer between the Master Chip and Slave Chip when used in a cascade connection. — 30 PD11 The PD15 pin corresponds to MSB. — 33 PD12 This pin is in a high impedance state while there is no data output. Data — 34 PD13 is loaded in at the falling edge of SFx. — 51 PD14 — 52 PD15 20 35 X1/CLKIN I External input for the basic clock or for the crystal oscillator. Input the basic clock (18 MHz). Refer to the internal clock generator circuit example. 21 36 X2 O Crystal oscilator. Used to configure the oscillation circuit. Refer to the internal clock generator circuit example. When inputting the basic clock externally, insert a 5 pF capacitor with excellent high frequency characteristics between X2 and GND. 23 38 PWDWN I Power-down mode control. "L": Power-down mode "H": Normal operation mode During power-down, all input pins are disabled and output pins are in the following sates : High impedance : SOUT, ROUT, PD0 to 15 "L": SYNCO, SCKO "H": OF1, OF2 Holds the last state : WDT, IRLD Not affected: X2, MCKO Reset after power-down is released. 7/28 ¡ Semiconductor MSM7620 (4/5) Pin 32-pin 64-pin SSOP QFP 24 40 Symbol Type SYNCO O Description 8 kHz sync signal for the PCM CODEC. Connect this pin to the SYNC pin and the PCM CODEC transmit/receive sync pin. Leave it open if using an external SYNC. 25 41 SCKO O Transmit clock signal (200 kHz) for the PCM CODEC. Connect this pin to the SCK pin and the PCM CODEC transmit/receive clock pin. Not affected by reset. Outputs "0" during power-down. Leave it open if using an external SCK. 27 44 RST I Reset signal. "L": Reset mode "H": Normal operation mode During initialization, input signals, except for PWDWN are disabled for 100 ms after reset (after RST is returned from "L" to "H"). Input the basic clock during the reset. Output pins during reset are in the following sates : High impedance: SOUT, ROUT, PD0 to 15 "L": WDT "H": OF1, OF2 Not affected: X2, SYNCO, SCKO, IRLD, MCKO 28 45 WDT O Test pin. Leave this pin open. 29 46 GC I Input signal for the gain controller when RIN input is controlled and the RIN input level is controlled and howling is prevented. The gain controller adjusts the RIN input level when it is –20 dBm0 or above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to –20 dBm0 in the attenuation range from 0 to 8.5 dB. RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB. • Single Chip or Master Chip in a Cascade Connection "H": Gain control ON "L": Gain control OFF "H" is recommended for echo cancellation. • Slave Chip in a Cascade Connection Fixed at "L" This pin is loaded in synchronization with the falling edge of the INT signal or the rising edge of RST. 8/28 ¡ Semiconductor MSM7620 (5/5) Pin 32-pin 64-pin SSOP QFP — 54 Symbol Type SF2 I Description Parallel data transfer flag. • Single Chip Fixed at "H" • Master Chip in a Cascade Connection Fixed at "H" • Slave Chip in a Cascade Connection Connect OF2 of the master chip to the first stage slave chip. Connect OF1 of the previous stage slave chip to the second and later stage slave chips. Refer to the control pin connection example. — 55 OF1 O Parallel data transfer flag. • Single Chip Leave this pin open. • Master Chip in a Cascade Connection Connect to the SF1 of all slaves. • Slave chip in a Cascade Connection Connect to the SF2 of the next stage slave chip. Connect the last stage slave chip to the SF1 of the master chip. Refer to the control pin connection example. — 59 SF1 I Parallel data transfer flag. • Single Chip Connect OF2. • Master Chip in a Cascade Connection Connect OF1 of the last stage slave chip. • Slave Chip in a Cascade Connection Connect OF1 of master chip for all slave chips. Refer to the control pin connection example. — 60 OF2 O Parallel data output flag. • Single Chip Connect to SF1. • Master Chip in a Cascade Connection Connect to SF2 of the first stage slave chip. • Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. 9/28 ¡ Semiconductor MSM7620 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Power Dissipation Storage Temperature Condition Rating Unit –0.3 to +7 V Ta = 25°C –0.3 to VDD + 0.3 V 1 W — –55 to +150 °C PD TSTG RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 4.5 5 5.5 V Power Supply Voltage VSS — — 0 — V Input High Voltage VIH Input Low Voltage VIL — 0 — 0.8 V Operating Temperature Ta — –40 +25 +85 °C Condition Min. Typ. Max. Unit 4.2 — VDD V Pins other than X1 2.4 — VDD V X1 pin 3.5 — VDD V ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (Ta = –40°C to +85°C) Symbol Output High Voltage VOH Output Low Voltage VOL IOL = 1.6 mA 0 — 0.4 V High Level Input Current IIH VIH = VDD — 0.1 10 mA –100 –50 –10 mA –10 –0.1 — mA — 0.1 10 mA –100 –50 +10 mA –10 –0.1 — mA — 30 40 mA — 4 5 mA — 6 8 mA Low Level Input Current IIL IOH = 40 mA VIL = SF1, SF2 VSS to VDD with pull-up Input other than the above High Level Output Current Low Level Output Current IOZH IOZL VOH = VDD VOL = PD15 to PD0 VSS to VDD with pull-up Input other than the above Power Supply Current (Operating) IDDO When extarnal input is used Power Supply Current(Stand-by) IDDS PWDWN="L" Input Capacitance Output Load Capacitance — as basic clock When oscillation circuit is used as basic clock CI — — — 15 pF CLOAD — — — 20 pF 10/28 ¡ Semiconductor MSM7620 Echo Canceler Characteristics (Refer to Characteristics Diagram) Parameter Symbol Condition Min. Typ. Max. Unit — 30 — dB — — 23 ms — — 31 ms RIN = –10 dBm0 (5 kHz band white noise) Echo Attenuation LRES E. R. L. (echo return loss) = 6 dB TD = 20 ms ATT, GC, NLP: OFF Cancelable Echo Delay Time for a Single Chip or a Master Chip in a TD Cascade Cancelable Echo Delay Time for a Slave Chip in a Cascade RIN = –10 dBm0 (5 kHz band white noise) E.R.L. = 6 dB TDS ATT, GC, NLP: OFF 11/28 ¡ Semiconductor MSM7620 AC Characteristics (Ta = –40°C to +85°C) Symbol fC Condition Min. Typ. Max. Unit — 17.5 18.0 18.5 MHz Clock Cycle Time tMCK — 54.1 55.56 57.1 ns Clock Duty Ratio tDMC — 40 50 60 % Clock "H" Level Pulse Width tMCH — 23.5 — — ns Clock "L" Level Pulse Width tMCL — 23.5 — — ns Clock Rise Time tr — — — 5 ns Clock Fall Time tf — — — 5 ns Parameter Clock Frequency tDCM — — — 100 ns Internal Sync Clock Frequency fCO fc = 18 MHz — 200 — kHz Internal Sync Clock Output Cycle Time tCO fc = 18 MHz — 5 — ms Internal Sync Clock Duty Ratio tDCO fc = 18 MHz — 50 — % Internal Sync Signal Output Delay Time tDCC fc = 18 MHz — — 5 ns Internal Sync Signal Period tCYO fc = 18 MHz — 125 — ms Internal Sync Signal Output Width tWSO fc = 18 MHz — tCO — ms Sync Clock Output Time Transmit/receive Operation Clock Frequency fSCK — 64 — 2048 kHz Transmit/receive Sync Clock Cycle Time tSCK — — 15.6 ms Transmit/receive Sync Clock Duty Ratio tDSC — 0.488 40 50 60 % Transmit/receive Sync Signal Period tCYC — 123 125 — ms Sync Timing Sync Signal Width tXS — 45 — — ns tSX — 45 — — ns tWSY — tSCK — tCYC–tSCK ms — — ns Receive Signal Setup Time tDS — 45 Receive Data Hold Time tDH — 45 — — ns Receive Data Input Time tID — — 7tSCK — ms IRLD Signal Output Delay Time tDIC — — — 138 ns IRLD Signal Output Width tWIR — — tSCK — ms tSD — — — 90 tXD — — — 90 Serial Output Delay Time ns 12/28 ¡ Semiconductor MSM7620 AC Characteristics (Continued) (Ta = –40°C to +85°C) Symbol Condition Min. Typ. Max. Unit Reset Signal Input Width Parameter tWR — 1 — — ms Reset Start Time tDRS — 5 — — ns Reset End Time tDRE — — — 52 ns Processing Operation Start Time tDIT — 100 — — ms Power Down Start Time tDPS — — — 111 ns Power Down End Time tDPE — — — 15 ns Control Pin Setup Time (INT) tDTS — 20 — — ns Control Pin Hold Time (INT) tDTH — 120 — — ns Control Pin Setup Time (RST) tDSR — 20 — — ns Control Pin Hold Time (RST) tDHR — 10 — — ns Parallel Data Output Signal Width tWPD — — 2tMCK — ns Flag Signal Output Time tDF — — tMCK — ns Flag Signal Output Width tWFO — — tMCK/2 — ns Flag Signal Input Width tWFI OFz connected to SFx — tWFO — ns Data Read Setup Time tFS — — 20 — ns Data Read Hold Time tFH — — 10 — ns 13/28 ¡ Semiconductor MSM7620 TIMING DIAGRAM Clock Timing fc. tMCK tDMC tMCH tMCL tr tf X1/CLKIN tDCM SCKO fco. tCO tDCO SCKO tDCC tDCC tCYO SYNCO tWSO Serial Input Timing fsck. tSCK tDSC SCK tSX tXS tCYC SYNC tWSY tDH tDS SIN RIN MSB 7 6 5 4 3 tID 2 MSB 7 LSB 0 1 tDIC tDIC IRLD tWIR 14/28 ¡ Semiconductor MSM7620 Serial Output Timing fsck. tSCK tDSC SCK tSX tXS tCYC SYNC ,, ,, tWSY tXD tSD tXD SOUT ROUT High-Z tXD MSB 7 6 5 4 3 2 1 LSB 0 High-Z MSB 7 Operation Timing After Reset tWR *Reset timing can be asynchronous RST tDIT tDRS tDRE Reset Internal operation Initialization Processing Start Note: INT is invalid in the diagonally shaded interval. Power Down Timing PWDWN *tDPS Internal Operation tDPE Power Down Processing Start *Input MCK in the tDPS interval. 15/28 ¡ Semiconductor MSM7620 Control Pin Load-in Timing *tCYC INT(IRLD) tDTH tDTS *Refer to the Serial Input Timing NLP, HCL, ATT, ADP, GC tWR RST tDSR tDHR NLP, HCL, ATT, ADP, GC Parallel Output Timing tWPD PD15 – High-Z High-Z Output Data PD 0 tDF tWFO OF1 OF2 Parallel Input Timing tWFI SF1 SF2 tFS tFH PD15 – Input Data PD 0 16/28 ¡ Semiconductor MSM7620 HOW TO USE THE MSM7620 The MSM7620 cancels the echo which returns to SIN using the RIN signal. Connect the base signal to the R-side and the echo generated signal to the S-side. Connection Methods According to Echos Example 1: Canceling acoustic echo (to handle acoustic echo from line input) CODEC MSM7620 CODEC ROUT SIN H m-law – + SOUT + Canceling line echo (to handle line echo from microphone input) CODEC MSM7620 RIN Microphone Input CODEC ROUT AFF m-law – SOUT Example 3: Line input AFF m-law Acoustic echo Example 2: RIN + H m-law + SIN Line echo Canceling line echo in a cascade connection (to handle line echo from microphone input) CODEC MSM7620 RIN Microphone input CODEC ROUT Master AFF m-law SOUT – + m-law + H H SIN PD0 - 15 Line echo Slave AFF 17/28 ¡ Semiconductor MSM7620 Example 4: Canceling of both acoustic echo and line echo (to handle both acoustic echo from line input and line echo from microphone input) CODEC Acoustic echo MSM7620 MSM7620 ROUT RIN SOUT AFF m-law SIN + + + SOUT RIN Line input m-law H + – – CODEC SIN AFF ROUT Line echo Microphone input For acoustic echo For line echo 18/28 ¡ Semiconductor MSM7620 Control Pin Connection Example Two-stage Cascade Connection Master + (slave ¥ 1) Single Chip Connection Master chip – * PD 0 MS PD15 MS NLP NLP NLP – NLP Slave chip – MS * * PD15 NLP +5 V PD 0 HCL PD 0 HCL HCL HCL HCL ADP ADP ADP ADP ADP ATT ATT ATT ATT ATT GC GC GC GC GC PWDWN PWDWN PWDWN PWDWN RST PWDWN RST +5 V RST PD15 RST RST INT IRLD INT IRLD INT IRLD SF1 * * OF1 SF1 OF1 SF1 OF1 SF2 * * OF2 SF2 OF2 SF2 OF2 +5 V Asterisk * mark indicates a pin only for the MSM7620-011. Four-stage Cascade Connection Master + (slave ¥ 3) Master chip +5 V Slave chip 1 +5 V Slave chip 2 +5 V Slave chip 3 MS PD15 MS PD15 MS PD15 MS NLP NLP – NLP – NLP – NLP – PD 0 HCL PD 0 HCL PD 0 HCL PD 0 HCL HCL ADP ADP ADP ADP ADP ATT ATT ATT ATT ATT GC GC GC GC GC PWDWN PWDWN PWDWN PWDWN RST RST RST PWDWN RST +5 V PD15 RST INT IRLD INT IRLD INT IRLD INT IRLD SF1 OF1 SF1 OF1 SF1 OF1 SF1 OF1 SF2 OF2 SF2 OF2 SF2 OF2 SF2 OF2 19/28 ¡ Semiconductor MSM7620 Clock Circuit Example Internal clock generator circuit MSM7620 X1/CLKIN X2 XTAL : 18 MHz R : 1 MW C1 : 27 pF C2 : 27 pF R XTAL C1 C2 GND GND External clock input circuit MSM7602 X1/CLKIN 18 MHz X2 5pF GND 20/28 ¡ Semiconductor MSM7620 ECHO CANCELER CHARACTERISTICS DIAGRAM RIN input level vs. echo attenuation 40 40 30 30 Echo attenuation [dB] Echo attenuation [dB] ERL vs. echo attenuation 20 10 0 40 30 20 10 0 20 10 0 –50 –40 –30 –20 –10 –10 ERL. [dB] 0 RIN input level [dBm] 0 dBm = 2.2 dBm0 Measurement Conditions RIN input: 5 kHz band white noise Echo delay time TD = 20 ms ERL = 6 dB ATT, GC, NLP = OFF Measurement Conditions RIN input = –10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) Echo delay time TD = 20 ms ATT, GC, NLP = OFF Echo delay time vs. echo attenuation Echo attenuation [dB] 30 20 10 0 1 0 2 50 3 100 4 5 150 6 7chip 200 Echo delay time [ms] Measurement Conditions RIN input = –10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) ERL = 6 dB ATT, GC, NLP = OFF The second through seventh chips are connected in a cascade. 21/28 ¡ Semiconductor MSM7620 Measurement System Block Diagram White noise generator RIN input L. P. F. 5 kHz MSM7543 A PCM m-law CODEC Level meter A PCM MSM7543 RIN ROUT MSM7620 SOUT SIN PCM A m-law CODEC PCM A TD Delay Echo delay time ATT ERL (echo return loss) 22/28 6 ROUT Speaker output 21 12 14 15 11 11 RSYNC 14 XSYNC 12 10 23 PWDWN 27 RST VFRO PCMIN GSX AIN– BCLOCK 8 R3 1 SG 3 AOUT– 5 PWI 24 SGC R13 C3 + C2 7 PDN TMC 19 8 V DD C9 16 AG DG 9 28 SIN SOUT ROUT RIN SCK NLP SYNC INT IRLD WDT 24 SYNCO 25 SCKO EXT. SCK EXT. SYNC RST PWDWN ADP ATT GC VDD 20 X1 21 X2 VSS VSS 32-Pin SSOP CLK HCL R12 For cancellation of line echo 13 13 10 10 2 2 3 3 4 4 6 6 29 29 32 C4 5 16 ++ SIN SOUT ROUT RIN SCK NLP HCL ADP ATT GC MSM7620-001GS-K 9 PCMOUT MSM7620-001GS-K 22 R1 13 AIN+ R2 For cancellation of acoustic echo R6 SYNC MSM7543GS-VK R11 9 13 14 12 11 15 12 11 RSYNC 14 XSYNC INT 7 IRLD 8 PWDWN 23 RST 27 WDT 28 24 SYNCO 25 SCKO 32 VDD C8 5 VSS 16 VSS 20 X1 21 X2 32-Pin SSOP R10 PCMOUT AIN+ PCMIN VFRO BCLOCK GSX Circuit input C5 RIN 23 6 SOUT Circuit output 21 R8 AIN– 22 R7 R9 10 19 PDN TMC SG 1 3 AOUT– PWI 5 24 SGC VDD 9 DG 16 C10 R8 > 20 kW R9 > 20 kW R10 = 2.2 kW R11 = 10 kW R12 = 10 kW R13 = 0-22 W R14 = 0-22 W C6 = 10 mF C7 = 0.1 mF C8 = 10 mF C9 = 1.0 mF C10 = 1.0 mF R14 + C6 MSM7620 23/28 R1 > 50 kW R2 > 20 kW R3 > 20 kW R4 = 2.2 kW R5 = 10 kW R6 = 10 kW R7 > 50 kW C1 = 0.1 mF C2 = 10 mF C3 = 0.1 mF C4 = 10 mF C5 = 0.1 mF AG C7 8 ¡ Semiconductor 23 R5 APPLICATION CIRCUIT R4 Bidirectional Connection Example MSM7543GS-VK Mike input C1 SIN C2 + C9 16 AG 8V DD 24 SGC 1 SG 3 AOUT– 5 PWI 22 AIN– 13 12 15 11 14 C4 DG 9 10 19 TMC PDM XSYNC RSYNC BCLOCK PCMIN PCMOUT + R5 Master NLP HCL ADP MS ATT GC 16 VSS 36 X2 47 VDD 48 VDD 62 VDD WDT SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD 64-Pin QFP 41 SCKO 40 SYNCO 35 X1 1 2 3 4 5 46 44 RST 38 PWDWN 10 SIN 15 ROUT 12 SCK 13 SYNC MSM7620-011GS-BK RST PWDWN R3 R12 C3 R1 R2 23 AIN + 6 VFRO 21 GSX MSM7543GS-VK R4 45 14 11 52 51 34 33 30 29 28 27 26 25 24 23 22 21 20 19 60 54 55 59 6 8 45 14 11 52 51 34 33 30 29 28 27 26 25 24 23 22 21 20 19 60 54 55 59 6 8 WDT 1 2 3 4 5 46 VSS 16 36 X2 47 VDD 48 VDD 62 VDD 41 SCKO 40 SYNCO 35 X1 NLP HCL ADP MS ATT GC 44 RST 38 PWDWN 10 SIN 15 ROUT 12 SCK 13 SYNC 64-Pin QFP SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD Slave MSM7620-011GS-BK CLK ROUT SIN C1 XSYNC RSYNC + C8 9 DG 22 24 16 R1 > 50 kW R2 > 20 kW R3 > 20 kW R4 = 2.2 kW R5 = 10 kW R6 > 50 kW C1 = 0.1 mF C2 = 10 mF C3 = 0.1 mF C4 = 10 mF C5 = 0.1 mF AG VDD 8 SGC PWI 1 3 AOUT– 5 SG AIN– PCMIN BCLOCK AIN + VFRO PCMOUT 23 6 GSX 21 MSM7543GS-VK 10 PDM 19 TMC 13 12 15 11 14 R10 R9 C10 R6 C6 R7 > 20 kW R8 > 20 kW R9 = 2.2 kW R10 = 10 kW R11 = 0-22 W R12 = 0-22 W C6 = 10 mF C7 = 0.1 mF C8 = 10 mF C9 = 1.0 mF C10 = 1.0 mF + C7 R12 R8 R7 C5 RIN SOUT ¡ Semiconductor MSM7620 Cascade Connection Example 24/28 ¡ Semiconductor MSM7620 NOTES ON USE 1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be amplified, the echo can not be eliminated. Refer to the characteristics diagram for ERL vs. echo attenuation quantity. 2. Set the level of the analog input so that the PCM CODEC does not overflow. 3. The recommended input level is –10 to –20 dBm0. Refer to the characteristics diagram for the RIN input level vs. echo attenuation quantity. 4. Applying the tone signal to this echo canceler will decrease echo attenuation. If the tone signal is input to the SIN pin during the time that a signal is input to the RIN pin, this echo cancceler operates faultily. A signal must be input to either the RIN pin or the SIN pin. The ADP or HCL pin must be driven at "H" if the tone signal is input to the SIN pin during the time that a signal is input to the RIN pin. 5. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset when possible. 6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock simultaneouly with power ON. If powering down immediately after power ON, be sure first input 10 or more clocks of the basic clock. 7. After powering ON, be sure to reset. 8. After the power down pin is changed to a "1" from a "0", be sure to reset. 9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 dB. 25/28 ¡ Semiconductor MSM7620 EXPLANATION OF TERMS Attenuating Function : This function prevents howling and controls the noise level with an attenuator for the RIN input and SOUT output. Refer to the explanation of pins (ATT pin). Echo Attenuation : If there is talking (input only to RIN) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. Echo attenuation = (SOUT level during through mode operation) – (SOUT level during echo canceler operation) [dB] Echo Delay Time : This is the time from when the signal is output from ROUT until it returns to SIN as an echo or other similar device. Acoustic Echo : When using a hands free phone, and so on, the signal output from the speaker echoes and is input again to the microphone. The return signal is referred to as acoustic echo. Telephone Line Echo : This is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. Gain Control Function : This function prevents howling and controls the sound level by with a gain controller for the RIN input. Refer to the explanation of pins (GC pin). Center Clipping Function : This function forces the SOUT output to a minimum value when the signal is below –57 dBm0. Refer to the explanation of pins (NLP pin). Double Talk Detection : Double talk refers to a state in which the SIN and RIN signals are input simultaneously. In a double talk state, a signal outside the echo signal which is to be canceled can be input to the SIN input, resulting in misoperation. The double talk detector prevents such misoperations of the canceler. Howling Detection : This is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands free talking. Howling not only interferes with talking, but can also cause misoperation of the echo canceler. The howling detector prevents such misoperation and prevents howling. Echo Return Loss (ERL) : When the signal output from ROUT returns to SIN as an echo, ERL refers to how much loss there is in the signal level during ROUT. ERL = (ROUT level) – (SIN level of the ROUT signal which returns as an echo) [dB] If ERL is positive (ROUT > SIN), the system is an attenuator system. If ERL is negative (ROUT < SIN), the system is an amplifier system. 26/28 ¡ Semiconductor MSM7620 PACKAGE DIMENSIONS (Unit : mm) SSOP32-P-640-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.83 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/28 ¡ Semiconductor MSM7620 (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 28/28