UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 HIGH-SPEED PWM CONTROLLER FEATURES D Improved Versions of the UC3823/UC3825 D D D D DESCRIPTION The UC3823A and UC3823B and the UC3825A and UC3825B family of PWM controllers are improved versions of the standard UC3823 and UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 μA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification. In addition each output is capable of 2-A peak currents during transitions. PWMs Compatible with Voltage-Mode or Current-Mode Control Methods Practical Operation at Switching Frequencies to 1 MHz 50-ns Propagation Delay to Output High-Current Dual Totem Pole Outputs (2-A Peak) Trimmed Oscillator Discharge Current D D Low 100-μA Startup Current D Pulse-by-Pulse Current Limiting Comparator D Latched Overcurrent Comparator With Full Cycle Restart BLOCK DIAGRAM CLK/LEB 4 13 VC (60%) RT 5 CT 6 R RAMP 7 EAOUT 3 NI 11 OUTA * OSC T SD PWM LATCH 1.25 V PWM COMPARATOR 14 OUTB 12 PGND 2 E/A 9 mA INV 1 SOFT−START COMPLETE SS 8 CURRENT LIMIT 1.0 V OVER CURRENT ILIM 9 1.2 V RESTART DELAY 0.2 V VCC 15 GND 10 RESTART DELAY LATCH 5V ”B” 16V/10V ”A” 9.2V/8.4V SD S R R 250 mA FAULT LATCH UVLO VREF 5.1 V ON/OFF * On the UC1823A version, toggles Q and Q are always low. 4V VREF GOOD INTERNAL BIAS 16 5.1 VREF UDG−02091 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004 −2008, Texas Instruments Incorporated UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications. Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for detailed technical and applications information. ORDERING INFORMATION UVLO MAXIMUM DUTY CYCLE TA −40°C 40°C to 85°C −0°C 0°C to 70°C (1) 9.2 V / 8.4 V 16 V / 10 V SOIC−16(1) (DW) PDIP−16 (N) PLCC−20(1) (Q) SOIC−16 (DW) PDIP−16 (N) PLCC−20(1) (Q) < 100% UC2823ADW UC2823AN UC2823AQ UC2823BDW UC2823BN − < 50% UC2825ADW UC2825AN UC2825AQ UC2825BDW UC2825BN − < 100% UC3823ADW UC3823AN UC3823AQ UC3823BDW UC3823BN − < 50% UC3825ADW UC3825AN UC3825AQ UC3825BDW UC3825BN UC3825BQ The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000 devices per reel for the Q package and 2000 devices per reel for the DW package. UVLO 9.2 V / 8.4 V MAXIMUM DUTY CYCLE TA −55°C 55°C to 125°C CDIP−16 (J) LCCC−20 (L) < 100% UC1823AJ, UC1823AJ883B, UC1823AJQMLV UC1823AL, UC1823AL883B < 50% UC1825AJ, UC1825AJ883B, UC1825AJQMLV UC1825AL, UC1825AL883B, UC1825ALQMLV PIN ASSIGNMENTS Q OR L PACKAGES (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VREF VCC OUTB VC PGND OUTA GND ILIM EAOUT CLK/LEB NC RT CT 4 3 2 1 20 19 18 5 6 17 16 7 8 15 14 9 10 11 12 13 RAMP SS NC ILIM GND INV NI EAOUT CLK/LEB RT CT RAMP SS NI INV NC VREF VCC DW, J, OR N PACKAGES (TOP VIEW) NC = no connection 2 OUTB VC NC PGND OUTA UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 TERMINAL FUNCTIONS NAME CLK/LEB TERMINAL NO. J or DW Q or L 4 5 I/O DESCRIPTION O Output of the internal oscillator Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. Output of the error amplifier for compensation Analog ground return pin Input to the current limit comparator Inverting input to the error amplifier Non-inverting input to the error amplifier High current totem pole output A of the on-chip drive stage. High current totem pole output B of the on-chip drive stage. Ground return pin for the output driver stage Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. Timing resistor connection pin for oscillator frequency programming Soft-start input pin which also doubles as the maximum duty cycle clamp. Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. CT 6 8 I EAOUT GND ILIM INV NI OUTA OUTB PGND 3 10 9 1 2 11 14 12 4 13 12 2 3 14 18 15 O − I I I O O − RAMP 7 9 I RT SS 5 8 7 10 I I VC 13 17 − VCC 15 19 − Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths VREF 16 20 O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT VIN Supply voltage, VC, VCC 22 V IO Source or sink current, DC OUTA, OUTB 0.5 A IO Source or sink current, pulse (0.5 μs) OUTA, OUTB 2.2 A INV, NI, RAMP −0.3 V to 7 V ILIM, SS −0.3 V to 6 V Analog inputs Power ground PGND ±0.2 V Outputs OUTA, OUTB limits ICLK Clock output current CLK/LEB IO(EA) Error amplifier output current EAOUT 5 mA ISS Soft-start sink current SS 20 mA IOSC Oscillator charging current RT −5 mA TJ Operating virtual junction temperature range −55°C to 150°C Tstg Storage temperature −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds tSTG Storage temperature Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds (1) PGND −0.3 V to VC +0.3 V −5 mA −55C°C to 150°C −65°C to 150°C 300°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS TA = −55°C to 125°C for the UC1823A/UC1825A, TA = −40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 5.1 5.15 V REFERENCE, VREF VO Ouput voltage range TJ = 25°C, Line regulation 12 V ≤ VCC ≤ 20 V 2 15 Load regulation 1 mA ≤ IO ≤ 10 mA 5 20 Total output variation Line, load, temperature Temperature stability(1) T(min) < TA < T(max) 0.2 Output noise voltage(1) 10 Hz < f < 10 kHz 50 Long term stability(1) Short circuit current IO = 1 mA TJ = 125°C, 5.03 1000 hours mV 5.17 V 0.4 mV/°C μVRMS 5 25 mV 30 60 90 mA TJ = 25°C 375 400 425 kHz RT = 6.6 kΩ, CT = 220 pF, TA = 25°C 0.9 1 1.1 MHz VREF = 0 V OSCILLATOR fOSC Initial accuracy(1) Total variation(1) Voltage stability Temperature stability(1) Line, temperature 350 450 kHz RT = 6.6 kΩ, CT = 220 pF, 0.85 1.15 MHz 12 V < VCC < 20 V T(min) < TA < T(max) High-level output voltage, clock 1% +/− 5% 3.7 4 Low-level output voltage, clock IOSC 0 0.2 Ramp peak 2.6 2.8 3 Ramp valley 0.7 1 1.25 Ramp valley-to-peak 1.6 1.8 2 9 10 11 mA mV Oscillator discharge current RT = OPEN, VCT = 2 V V ERROR AMPLIFIER Input offset voltage 2 10 Input bias current 0.6 3 Input offset current 0.1 1 Open loop gain 1 V < VO < 4 V 60 CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110 IO(sink) Output sink current VEAOUT = 1 V IO(src) Output source current VEAOUT = 4 V High-level output voltage IEAOUT = −0.5 mA Low-level output voltage IEAOUT = −1 mA Gain bandwidth product f = 200 kHz Slew (1) 4 rate(1) Ensured by design. Not production tested. 1 μA A 95 dB 2.5 mA −1.3 −0.5 4.5 4.7 5 0 0.5 1 6 12 Mhz 6 9 V/μs V UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS TA = −55°C to 125°C for the UC1823A/UC1825A, TA = −40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted) PWM COMPARATOR IBIAS Bias current, RAMP VRAMP = 0 V −1 Minimum duty cycle −8 μA 0% Maximum duty cycle 85% tLEB Leading edge blanking time RLEB = 2 kΩ, CLEB = 470 pF RLEB Leading edge blanking resistance VCLK/LEB = 3 V VZDC Zero dc threshold voltage, EAOUT VRAMP = 0 V tDELAY Delay-to-output time(1) VEAOUT = 2.1 V, VILIM = 0 V to 2 V step 300 375 450 ns 8.5 10.0 11.5 kΩ 1.10 1.25 1.4 V 50 80 ns 20 μA CURRENT LIMIT / START SEQUENCE / FAULT ISS Soft-start charge current VSS Full soft-start threshold voltage IDSCH Restart discharge current ISS Restart threshold voltage IBIAS ILIM bias current ICL Current limit threshold voltage Overcurrent threshold voltage Delay-to-output time, ILIM(1) td VSS= 2.5 V 8 14 4.3 5 100 250 350 μA 0.3 0.5 V 15 μA 0.95 1 1.05 1.14 1.2 1.26 50 80 IOUT = 20 mA 0.25 0.4 IOUT = 200 mA 1.2 2.2 IOUT = 20 mA 1.9 2.9 2 3 CL = 1 nF 20 45 UC2823B, UC2825B, UC3825B, UC3825B 16 17 9.6 VSS= 2.5 V VILIM = 0 V to 2 V step VILIM = 0 V to 2 V step V V ns OUTPUT Low level output saturation voltage Low-level High level output saturation voltage High-level tr, tf Rise/fall time(1) IOUT = 200 mA V ns UNDERVOLTAGE LOCKOUT (UVLO) Start threshold voltage UC1823A, UC1825A, UC2823A, UC2825A UC3825A, UC3825A 8.4 9.2 Stop threshold voltage UC2823B, UC2825B, UC3825B, UC3825B 9 10 OVLO hysteresis UC1823A, UC1825A, UC2823A, UC2825A UC3825A, UC3825A 0.4 0.8 1.2 UC2823B, UC2825B, UC3825B, UC3825B 5 6 7 100 300 μA 28 36 mA V SUPPLY CURRENT Isu Startup current ICC Input current (1) VC = VCC = VTH(start) − 0.5 V Ensured by design. Not production tested. 5 UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 APPLICATION INFORMATION The oscillator of the UC3823A, UC3823B, UC3825A, and UC3825B is a saw tooth. The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based on the desired frequency (RT) and DMAX. The design equations are: RT + 3V (10 mA) ǒ1 * DMAXǓ CT + ǒ1.6 ǒR T D MAXǓ fǓ (1) Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended. UDG−95102 Figure 1. Oscillator OSCILLATOR FREQUENCY vs TIMING RESISTANCE 10 M MAXIMUM DUTY CYCLE vs TIMING RESISTANCE 100 DMAX − Maximum Duty Cycle − % f − Frequency − Hz 95 1M 100 k 10 k 1k 10 k RT − Timing Resistance − W Figure 2 6 90 85 80 75 70 100 k 1k 10 k RT − Timing Resistance − W Figure 3 100 k UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 LEADING EDGE BLANKING The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%. To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM comparator, current limit comparator, or the overcurrent comparator. Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not require any filtering as result of leading edge blanking. To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy, an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%. The design equation is: t LEB + 0.5 ǒR ø 10 kWǓ C (2) Values of R less than 2 kΩ should not be used. Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this reason, some noise filtering may be required on the ILIM pin. UDG−95105 Figure 4. Leading Edge Blanking Operational Waveforms 7 UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 UVLO, SOFT-START AND FAULT MANAGEMENT Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output follows until closed loop regulation takes over. Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged by a 250-μA current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At this point the fault latch resets and the chip executes a soft-start. Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions. UDG−95106 Figure 5. Soft-Start and Fault Waveforms ACTIVE LOW OUTPUTS DURING UVLO The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate. UDG−95108 Figure 6. Output Voltage vs Output Current 8 UDG−95106 Figure 7. Output V and I During UVLO UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 CONTROL METHODS Current Mode Voltage Mode UDG−95110 UDG−95109 . Figure 8. Control Methods SYNCHRONIZATION The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming synchronizing signal. UDG−95111 Figure 9. General Oscillator Synchronization UDG−95113 Figure 10. Two Unit Interface UDG−95112 Figure 11. Operational Waveforms 9 UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 HIGH CURRENT OUTPUTS Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak current into a capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground (PGND) pins help decouple the device’s analog circuitry from the high-power gate drive noise. The use of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT USE standard silicon diodes. Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B devices. These can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each output for a combined peak current of 4 A. UDG−95114 Figure 12. Power MOSFET Drive Circuit GROUND PLANES Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND. Nothing else should be connected to power ground. VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be bypassed to the signal ground plane. 10 UC1823A, UC2823A, UC2823B, UC3823A, UC3823B, UC1825A, UC2825A, UC2825B, UC3825A, UC3825B www.ti.com SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010 UDG−95115 Figure 13. Ground Planes Diagram OPEN LOOP TEST CIRCUIT This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any wideband circuit, careful grounding and bypass procedures should be followed. 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