UC1851 UC2851 UC3851 Programmable, Off-Line, PWM Controller FEATURES DESCRIPTION • All Control, Driving, Monitoring, and Protection Functions Included • Low-Current Off Line Start Circuit • Voltage Feed Forward or Current Mode Control • High Current Totem Pole Output The UC1851 family of PWM controllers are optimized for offline primary side control. These devices include a high current totem pole output stage and a toggle flip-flop for absolute 50% duty cycle limiting. In all other respects this line of controllers is pin for pin compatible with the UC1841 series. Inclusion of all major housekeeping functions in these high performance controllers makes them ideal for use in cost sensitive applications. • 50% Absolute Max Duty Cycle • PWM Latch for Single Pulse Per Period • Pulse-by-Pulse Current Limiting plus Shutdown for Over-Current Fault • No Start-Up or Shutdown Transients • Slow Turn-On Both Initially and After Fault Shutdown • Shutdown Upon Over or Under Voltage Sensing • Latch Off or Continuous Retry After Fault • 1% Reference Accuracy • 500kHz Operation • 18 Pin DIL or 20 Pin PLCC Package BLOCK DIAGRAM 10/94 Important features of these controllers include low current start-up, linear feed-forward for constant volt-second operation, and compatibility with both voltage or current mode control. In addition, these devices include a programmable start threshold, as well as programmable over-voltage, under-voltage, and over current fault thresholds. The fault latch on these devices can be configured for automatic restart, or latched off response to a fault. These devices are packaged in 18-pin plastic or ceramic dualin-line packages, or for surface mount applications, a 20 Pin PLCC. The UC1851 is characterized for -55°C to +125°C operation while the UC2851 and UC3851 are designed for -40°C to +85°C and 0°C to +70°C, respectively. UC1851 UC2851 UC3851 ABSOLUTE MAXIMUM RATINGS (Note 1) Comparator Inputs (Pins 1–7, 9–11, 16). . . . . . . . . . . . . . Internally clamped at 12V Power Dissipation at TA = 25°C (Note 3). . . . . . . . . . . 1000mW Power Dissipation at TC = 25°C (Note 3). . . . . . . . . . . 2000mW Operating Junction Temperature . . . . . . . . . . . -55°C to +150°C Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Note 1:All voltages are with respect to ground, Pin 13. Currents are positive-into, negative-out of the specified terminal Note 2:All pin numbers are referenced to DIL-18 package. Note 3:Consult Packaging Section of Databook for thermal limitations and considerations of package. Supply Voltage, +VIN (Pin 15) Voltage Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V Current Driven, 100mA maximum . . . . . . . . . . . Self-limiting PWM Output Voltage (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40V PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA PWM Output Peak Energy Discharge . . . . . . . . . . . . 20µJoules Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V CONNECTION DIAGRAMS DIL-18, SOIC-18 (TOP VIEW) J or N, DW Package PACKAGE PIN FUNCTIONS FUNCTION PIN PLCC-20, LCC-20 (TOP VIEW) Q, L PACKAGE COMP START/UV OV SENSE STOP RESET CUR THRESH CUR SENSE SLOW START RT/CT RAMP VIN SENSE PWM OUT GROUND DRIVE BIAS +VIN SUPPLY 5.0V REF INV. INPUT N.I. INPUT 1 2 3 4 5 7 8 9 10 11 12 13 14 15 17 18 19 20 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1851, -40°C to +85°C for the UC2851, and 0°C to 70°C for the UC3851; VIN = 20V, RT = 20kΩ, CT = .001 mfd, RR = 10kΩ, CR = .001mfd. Current Limit Threshold = 200mV, TA = TJ. PARAMETER Power Inputs Start-Up Current Operating Current Supply OV Clamp Reference Section Reference Voltage Line Regulation Load Regulation Total Ref Variation Short Circuit Current Oscillator Nominal Frequency Voltage Stability Total Ref Variation Maximum Frequency TEST CONDITIONS VIN = 30V, Pin 2 = 2.5V VIN = 30V, Pin 2 = 3.5V VIN = 20mA UC1851 / UC2851 MIN TYP MAX 33 TJ = 25°C VIN = 8 to 30V IL = 0 to 10mA Over Operating Temperature Range VREF = 0, TJ = 25°C 4.95 TJ = 25°C VIN = 8 to 30V Over Operating Temperature Range 47 RT = 2kΩ, CT = 330pF 2 4.5 15 39 6 21 45 5.0 10 10 5.05 15 20 4.9 5.1 -100 4.85 -80 50 53 45 0.5 1 55 4.9 45 500 MIN 33 43 500 UC3851 TYP MAX UNITS 4.5 15 39 6 21 45 mA mA V 5.0 10 10 5.1 20 30 V mV mV -80 5.15 -100 V mA 50 55 kHz 0.5 1 57 % kHz kHz UC1851 UC2851 UC3851 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the PARAMETER Ramp Generator Ramp Current, Minimum Ramp Current, Maximum Ramp Valley Ramp Peak Error Amplifier Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain Output Swing (Max Output ≤ Ramp Peak - 100mV) CMRR PSRR Short Circuit Current Gain Bandwidth (Note 1) Slew Rate (Note 1) PWM Section Continuous Duty Cycle Range (other than zero) (Note 1) Output High Level Rise Time (Note 1) Fall Time (Note 1) Output Saturation Comparator Delay (Note 1) UC1851, -40°C to +85°C for the UC2851, and 0°C to 70°C for the UC3851; VIN = 20V, RT = 20kΩ, CT = .001 mfd, RR = 10kΩ, CR = .001mfd. Current Limit Threshold = 200mV, TA = TJ. TEST CONDITIONS UC1851 / UC2851 UC3851 UNITS MIN TYP MAX MIN TYP MAX ISENSE = −10µA ISENSE = 1.0mA -0.9 0.3 3.9 Clamping Level VCM = 5.0V -11 -14 -.95 0.4 4.2 0.6 4.5 0.5 0.5 ∆VO = 1 to 3V Minimum Total Range 60 VCM = 1.5 to 5.5V VIN = 8 to 30V VCOMP = 0V TJ = 25°C, AVOL = 0dB TJ = 25°C, AVCL = 0dB 70 70 Minimum Total Continuous Range Ramp Peak < 4.2V ISOURCE = 20mA ISOURCE = 200mA TJ = 25°C, CL = 1nF TJ = 25°C, CL = 1nF IOUT = 20mA IOUT = 200mA 2 1 18 17 Pin 8 to Pin 12, TJ = 25°C, RL = 1kΩ Sequencing Functions Comparator Thresholds Pins 2, 3, 5 Input Bias Current Pins 3, 5 = 0V Input Leakage Pins 3, 5 = 10V Start/UV Hysteresis Current Pin 2 = 2.5V Ext. Stop Threshold Pin 4 Error Latch Activate Current Pin 4 = 0V, Pin 3 > 3V Driver Bias Saturation Voltage, IB = -50mA VIN-VOH Driver Bias Leakage VB = 0V Slow-Start Saturation IS = 10mA Slow-Start Leakage VS = 4.5V Current Control Current Limit Offset Current Shutdown Offset Input Bias Current Pin 7 = 0V Common Mode Range (Note 1) Current Limit Delay (Note 1) TJ = 25°C, Pin 7 to 12, RL = 1k Note 1:Guaranteed by design. Not 100% tested in production. 3 2.8 170 0.8 370 5 2 0.5 66 0.3 -10 1 18.5 18.5 50 50 0.2 1.7 300 150 150 0.4 2.2 500 3.0 -1.0 0.1 200 1.6 -120 2 3.2 -4.0 2.0 220 2.4 -200 3 -0.1 0.2 0.1 -10 0.5 2.0 0 400 -2 5 430 -5 3.0 400 -0.4 200 µA -.95 0.4 4.2 0.6 4.5 mA V V 10 5 0.5 mV µA µA dB 3.5 V -10 dB dB mA MHz V/µs 46 % 18.5 18.5 50 50 0.2 1.7 300 150 150 0.4 2.2 500 V V ns ns V V ns 3.0 -1.0 0.1 200 1.6 -120 2 3.2 -4.0 2.0 230 2.4 -200 3 V µA µA µA V µA V -0.1 0.2 0.1 -10 0.5 2.0 µA V µA 0 400 -2 10 440 -5 3.0 400 mV mV µA V ns 66 0.3 70 70 46 -14 2 1 60 3.5 80 80 -4 2 0.8 -0.9 0.3 3.9 -11 80 80 -4 2 0.8 2 18 17 2.8 170 0.8 360 -0.4 200 UC1851 UC2851 UC3851 FUNCTIONAL DESCRIPTION PWM CONTROL 1. Oscillator 2. Ramp Generator: 3. Error Amplifier 4. Reference Generator: 5. PWM Comparator: 6. PWM Latch: 7. PWM Output Switch: Generates a fixed-frequency internal clock from an external RT and CT. KC Frequency = where KC is a first-order correction factor ≈ 0.3 log (CT x 1012). RTCT dV sense voltage = . Develops linear ramp with slope defined externally by dT RRCR CR is normally selected ≤ CT and its value will have some effect upon valley duty cycle. Limiting the minimum value for ISENSE into pin 11 will establish a maximum duty cycle clamp. CR terminal can be used as an input port for current mode control. Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance; unity-gain stable. The output is held low by the slow start voltage at turn on in order to minimize overshoot. Precision 5.0V for internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of ±2%. 40V clamp zener for chip OV protection, 100mA maximum current. Generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. Terminates the PWM output pulse when set by inputs from either the PWM comparator, the pulse-by-pulse comparator, or the error latch. Resets with each internal clock pulse. Totem pole output stage capable of sourcing and sinking 1 amp peak current. The active "on" state is high. SEQUENCING FUNCTIONS 1. Start/UV Sense: With an increasing voltage, this comparator generates a turn-on signal and releases the slow start clamp at a start threshold. With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200µA hysteresis current. 2. Drive Switch: Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input voltage reaches start threshold. 3. Driver Bias: Supplies drive to external circuitry upon start-up. 4. Slow Start: Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RSCS for slow increase of output pulse width. Can also be used as an alternate maximum duty cycle clamp with an external voltage divider. PROTECTION FUNCTIONS 1. Error Latch: When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are: a. OV > 3.2V (Typically 3V) b. Stop > 2.4V (Typically 1.6V) c. Current Sense 400mV over threshold. (Typical). Error Latch resets when slow start voltage falls to 0.4V if Reset Pin < 2.8V. With Pin 5 > 3.2V, Error Latch will remain set. 2. Current Limiting: Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error Latch. 3. External Stop: A voltage over 2.4 will set the Error Latch and hold the output off. A voltage less than 0.8V will defeat the error latch and prevent shutdown. A capacitor here will slow the action of the error latch for transient protection by providing a Typical Delay of 13ms/µF. 4 UC1851 UC2851 UC3851 Start/UV Hysteresis Current Output Saturation Characteristics Oscillator Frequency PWM Output Minimum Pulse Width Error Amplifier Open-Loop Gain and Phase Shutdown Timing 5 UC1851 UC2851 UC3851 OPEN-LOOP CIRCUIT Nominal Frequency = 1 RTCT = 50kHz R1 + R2 + R3 Start Voltage = 3 +0.2R1 = 12V R2 + R3 R1 + R2 + R3 UV Fault Voltage = 3 = 8V R2 + R3 R1 + R2 + R3 OV Fault Voltage = 3 = 32V R3 Current Limit = 200mV Current Fault Voltage = 600mV Duty Cycle Clamp = 50% @VIN = 15V, Duty Cycle = 48% @VIN = 30V, Duty Cycle = 24% High Peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 13 in a single ground point. Programmable Soft Start and Restart Delay Circuit UC1851 Power MOSFET Drive Interface For further application information see UC1840/UC1841 Data Sheets UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 6 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9558601MVA OBSOLETE CDIP J 18 TBD Call TI Call TI UC1851J OBSOLETE CDIP J 18 TBD Call TI Call TI UC1851J883B OBSOLETE CDIP J 18 TBD Call TI Call TI UC2851DW ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2851DWG4 ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2851N ACTIVE PDIP N 18 20 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC2851NG4 ACTIVE PDIP N 18 20 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3851DW ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3851DWG4 ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3851DWTR ACTIVE SOIC DW 18 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3851DWTRG4 ACTIVE SOIC DW 18 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3851N ACTIVE PDIP N 18 20 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3851NG4 ACTIVE PDIP N 18 20 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device UC3851DWTR Package Package Pins Type Drawing SOIC DW 18 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.9 12.0 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC3851DWTR SOIC DW 18 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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