TI UCC28720

UCC28720
www.ti.com
SLUSBE8 – MAY 2013
Constant-Voltage, Constant-Current Controller With Primary-Side Regulation
Check for Samples: UCC28720
FEATURES
APPLICATIONS
•
•
•
1
< 10-mW No-Load Power
Primary-Side Regulation (PSR) Eliminates
Opto-Coupler
±5% Voltage and Current Regulation Across
Line and Load
700-V Start-Up Switch
80-kHz Maximum Switching Frequency
Enables High-Power Density Charger Designs
Quasi-Resonant Valley-Switching Operation
for Highest Overall Efficiency
Wide VDD Range Allows Small Bias Capacitor
Dynamic BJT Drive
Overvoltage, Low-Line, and Overcurrent
Protection Functions
Programmable Cable Compensation
SOIC-7 Package
•
•
•
•
•
•
•
•
•
+
SIMPLIFIED APPLICATION
–
VAC
VOUT
UCC28720
VAUX
VDD
HV
DRV
VS
CBC
CS
GND
UDG-13090
•
•
USB-Compliant Adapters and Chargers for
Consumer Electronics
– Smart phones
– Tablet computers
– Cameras
Standby Supply for TV and Desktop
White Goods
DESCRIPTION
The UCC28720 flyback power supply controller
provides isolated-output Constant-Voltage (CV) and
Constant-Current (CC) output regulation without the
use of an optical coupler. The devices process
information from the primary power switch and an
auxiliary flyback winding for precise control of output
voltage and current.
An internal 700-V start-up switch, dynamicallycontrolled operating states and a tailored modulation
profile support ultra-low standby power without
sacrificing start-up time or output transient response.
Control algorithms in the UCC28720 allow operating
efficiencies to meet or exceed applicable standards.
The output drive interfaces to a bipolar transistor
power switch. Discontinuous conduction mode (DCM)
with valley switching reduces switching losses.
Modulation of switching frequency and primary
current peak amplitude (FM and AM) keeps the
conversion efficiency high across the entire load and
line ranges.
The controller has a maximum switching frequency of
80 kHz and always maintains control of the peakprimary current in the transformer. Protection features
help keep primary and secondary component
stresses in check. The UCC28720 allows
compensation for voltage drop in the cable to be
programmed with an external resistor.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. PRODUCT INFORMATION (1)
(1)
(2)
(2)
PACKAGE
PINS
ORDERABLE
DEVICES
SOIC (D)
7
UCC28720D
See Orderable Addendum for specific device ordering information.
For other fixed cable compensation options, please consult the factory.
ABSOLUTE MAXIMUM RATINGS (1)
MIN
MAX
Start-up pin voltage, HV
VHV
700
Bias supply voltage, VDD
VVDD
38
Continuous base current sink
IDRV
50
Continuous base current source
IDRV
Self- limiting
Peak current, VS
IVS
Base drive voltage at DRV
VDRV
Self- limiting
−0.75
7
−0.5
5
Operating junction temperature range
TJ
−55
150
Storage temperature
TSTG
−65
150
VS
Lead temperature 0.6 mm from case for 10 seconds
ESD rating
(1)
2
V
mA
−1.2
−0.5
CS, CBC
Voltage range
UNIT
V
°C
260
Human-body model (HBM)
Charged-device model (CDM)
2000
500
V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functional operation of
the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. All voltages are with respect
to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the operating ambient temperature
ranges unless otherwise noted.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
VDD
Bias supply operating voltage
CVDD
VDD bypass capacitor
9
35
V
1.0
10
µF
RCBC
Cable-compensation resistance
10
kΩ
IVS
VS pin current
−1
mA
TJ
Operating junction temperature
−40
125
°C
THERMAL INFORMATION
UCC28720
THERMAL METRIC (1)
D
UNITS
7 PINS
θJA
Junction-to-ambient thermal resistance (2)
141.5
θJCtop
Junction-to-case (top) thermal resistance (3)
73.8
θJB
Junction-to-board thermal resistance (4)
89.0
ψJT
Junction-to-top characterization parameter (5)
23.5
ψJB
Junction-to-board characterization parameter (6)
88.2
(1)
(2)
(3)
(4)
(5)
(6)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
3
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C, TA = TJ
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-VOLTAGE START UP
IHV
Start-up current out of VDD
VHV = 100 V, VVDD = 0 V, start state
225
500
IHVLKG
Leakage current at HV
VHV = 400 V, run state, TJ = 25 ºC
100
0.01
0.25
2.00
2.65
150
µA
BIAS SUPPLY INPUT
IRUN
Supply current, run
IDRV = 0, run state
IWAIT
Supply current, wait
IDRV = 0, wait state
95
ISTART
Supply current, start
IDRV = 0, VVDD = 18 V, start state, IHV = 0
18
30
IFAULT
Supply current, fault
IDRV = 0, fault state
95
150
mA
µA
UNDERVOLTAGE LOCKOUT
VVDD(on)
VDD turn-on threshold
VVDD low to high
19
21
23
VVDD(off)
VDD turn-off threshold
VVDD high to low
7.35
7.7
8.15
VVSR
Regulating level
Measured at no-load condition, TJ = 25°C (1)
4.01
4.05
4.09
V
VVSNC
Negative clamp level
IVS = -300 µA, volts below ground
190
250
325
mV
IVSB
Input bias current
VVS = 4 V
-0.25
0
0.25
µA
V
VS INPUT
CS INPUT
VCST(max) Max CS threshold voltage
VVS = 3.7 V
735
780
815
VCST(min)
Min CS threshold voltage
VVS = 4.35 V
175
190
215
KAM
AM control ratio
VCST(max) / VCST(min)
3.6
4.0
4.4
VCCR
Constant current regulating level
CC regulation constant
317
330
344
mV
KLC
Line compensation current ratio
IVSLS = -300 µA, IVSLS / current out of CS pin
24.0
25.0
28.6
A/A
TCSLEB
Leading-edge blanking time
DRV output duration, V CS = 1 V
230
290
355
ns
IDRS(max)
Maximum DRV source current
VDRV = 2 V, VVDD = 9 V, VVS = 3.85 V
32
37
41
IDRS(min)
Minimum DRV source current
VDRV = 2 V, VVDD = 9 V, VVS = 4.30 V
16
19
22
RDRVLS
DRV low-side drive resistance
IDRV = 10 mA
VDRCL
DRV clamp voltage
VVDD = 35 V
RDRVSS
DRV pull-down in start state
mV
V/V
DRIVER
mA
Ω
1
2.4
5.9
7
V
20
25
kΩ
TIMING
fSW(max)
Maximum switching frequency
VVS = 3.7 V
74
80
87
kHz
fSW(min)
Minimum switching frequency
VVS = 4.35 V
580
650
740
Hz
tZTO
Zero-crossing timeout delay
2.5
3.1
3.6
µs
(1)
4
The regulating level and over voltage at VS decreases with temperature by 0.8 mV/˚C. This compensation is included to reduce the
power supply output voltage variance over temperature.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C, TA = TJ
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PROTECTION
VOVP
Over-voltage threshold
At VS input, TJ = 25°C (2)
4.51
4.60
4.73
VOCP
Over-current threshold
At CS input
1.4
1.5
1.6
IVSL(run)
VS line-sense run current
Current out of VS pin increasing
190
225
275
IVSL(stop)
VS line-sense stop current
Current out of VS pin decreasing
70
80
100
KVSL
VS line sense ratio
IVSL(run) / IVSL(stop)
2.45
2.80
3.05
TJ(stop)
Thermal shut-down temperature
Internal junction temperature
165
V
µA
A/A
°C
CABLE COMPENSATION
VCBC(max)
Cable compensation maximum
voltage
Voltage at CBC at full load
2.9
3.1
3.5
VCVS(min)
Minimum compensation at VS
VCBC = open, change in VS regulating level at full
load
-55
-15
25
VCBC = 0 V, change in VS regulating level at full
load
275
320
380
VCVS(max) Maximum compensation at VS
(2)
V
mV
The regulating level and over voltage at VS decreases with temperature by 0.8 mV/˚C. This compensation is included to reduce the
power supply output voltage variance over temperature.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
5
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
IHV
HV
OC FAULT
OV FAULT
TSD/SD FAULT
LINE FAULT
POWER
& FAULT
MANAGEMENT
UVLO
21 V / 8 V
VDD
VDD
5V
GND
4.05 V + VCVS
+
VS
SAMPLER
35 mA
CONTROL
LAW
E/A
DRV
VCST
+
20 kΩ
OV FAULT
VOVP
VALLEY
SWITCHING
14 V
1 / fSW
S
Q
R
Q
+
SECONDARY
TIMING
DETECT
CURRENT
REGULATION
CS
VCST
LEB
IVSLS
LINE
SENSE
IVSLS
10 kΩ
IVSLS / KLC
+
LINE
FAULT
2.2 V / 0.80 V
OC FAULT
+
1.5 V
VCVS = ICBC x 3 kΩ
CABLE
COMPENSATION
0 V-VCVS(max)
+
ICBC
28 kΩ
CBC
UDG-13094
6
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
SOIC (D) PACKAGE
7 PINS
(TOP VIEW)
UCC28720
SOIC-7 (D)
VDD 1
7
HV
CBC 3
6
DRV
GND 4
5
CS
VS 2
(TOP VIEW)
PIN FUNCTIONS
NAME
NUMBER
I/O
DESCRIPTION
CBC
3
I
Cable compensation is a programming pin for compensation of cable voltage drop. Cable
compensation is programmed with a resistor to GND.
CS
5
I
Current sense input connects to a ground-referenced current-sense resistor in series with the power
switch. The resulting voltage is used to monitor and control the peak primary current. A series resistor
can be added to this pin to compensate the peak switch current levels as the AC-mains input varies.
DRV
6
O
Drive is an output used to drive the base of an external high voltage NPN transistor.
GND
4
—
The ground pin is both the reference pin for the controller and the low-side return for the drive output.
Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and
avoid any common trace length with analog signal return paths.
HV
7
I
The high-voltage pin connects directly to the rectified bulk voltage and provides charge to the VDD
capacitor for start-up of the power supply.
NTC
—
I
NTC an interface to an external negative temperature coefficient resistor for remote temperature
sensing. Pulling this pin low shuts down PWM action.
VDD
1
I
VDD is the bias supply input pin to the controller. A carefully-placed bypass capacitor to GND is
required on this pin.
I
Voltage sense is an input used to provide voltage and timing feedback to the controller. This pin is
connected to a voltage divider between an auxiliary winding and GND. The value of the upper resistor
of this divider is used to program the AC-mains run and stop thresholds and line compensation at the
CS pin.
VS
2
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
7
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
Detailed Pin Description
VDD (Device Bias Voltage Supply): The VDD pin is connected to a bypass capacitor to ground. The VDD turnon UVLO threshold is 21 V and turn-off UVLO threshold is 8.1 V, with an available operating range up to 35 V on
VDD. The USB charging specification requires the output current to operate in constant-current mode from 5 V to
a minimum of 2 V; this is easily achieved with a nominal VDD of approximately 25 V. The additional VDD
headroom up to 35 V allows for VDD to rise due to the leakage energy delivered to the VDD capacitor in highload conditions.
GND (Ground): There is a single ground reference external to the device for the base drive current and analog
signal reference. Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on
the VS and CS signal pins.
HV (High Voltage Startup): The HV pin is connected directly to the bulk capacitor to provide startup current to
the VDD capacitor. The typical startup current is ~300 µA which provides fast charging of the VDD capacitor. The
internal HV start-up device is active until VDD exceeds the turn-on UVLO threshold at which time the HV start-up
device is turned off. In the off state the leakage current is very low to minimize standby losses of the controller.
When VDD falls below the UVLO turn-off threshold the HV start-up device is turned on.
VS (Voltage-Sense): The VS pin is connected to a resistor divider from the auxiliary winding to ground. The
output-voltage feedback information is sampled at the end of the transformer secondary current demagnetization
time to provide an accurate representation of the output voltage. Timing information to achieve valley-switching
and to control the duty cycle of the secondary transformer current is determined by the waveform on the VS pin.
Avoid placing a filter capacitor on this input which would interfere with accurate sensing of this waveform.
The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. During the transistor on-time the VS pin is
clamped to approximately 250 mV below GND and the current out of the VS pin is sensed. For the AC-input
run/stop function, the run threshold on VS is 225 µA and the stop threshold is 80 µA. The values for the auxilliary
voltage divider upper-resistor RS1 and lower-resistor RS2 can be determined by the equations below.
where
•
•
•
RS2 =
NPA is the transformer primary-to-auxiliary turns ratio,
VIN(run) is the AC RMS voltage to enable turn-on of the controller (run),
IVSL(run) is the run-threshold for the current pulled out of the VS pin during the switch on-time. (see
ELECTRICAL CHARACTERISTICS)
(1)
RS1 ´ VVSR
NAS ´ (VOCV + VF ) - VVSR
where
•
•
•
•
•
VOCV is the converter regulated output voltage,
VF is the output rectifier forward drop at near-zero current,
NAS is the transformer auxiliary to secondary turns ratio,
RS1 is the VS divider high-side resistance,
VVSR is the CV regulating level at the VS input (see ELECTRICAL CHARACTERISTICS).
(2)
DRV (Base Drive): The DRV pin is connected to the NPN transistor base pin. The driver provides a base drive
signal limited to 7 V. The turn-on characteristic of the driver is a 15 mA to 35-mA current source that is scaled
with the current sense threshold dictated by the operating point in the control scheme. When the minimum
current sense threshold is being used, the base drive current is also at its minimum value. As the current sense
threshold is increased to the maximum, the base drive current scales linearly with it to its maximum of 35 mA
typical. The turn-off current is determined by the low-side driver RDS(on)
8
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
CS (Current Sense): The current-sense pin is connected through a series resistor (RLC) to the current-sense
resistor (RCS). The current-sense threshold is 0.78 V for IPP(max) and 0.195 V for IPP(min). The series resistor RLC
provides the function of feed-forward line compensation to eliminate change in IPP due to change in di/dt and the
propagation delay of the internal comparator and NPN transistor turn-off time. There is an internal leading-edge
blanking time of approximately 300 ns to eliminate sensitivity to the turn-on current spike. It should not be
necessary to place a bypass capacitor on the CS pin. The value of RCS is determined by the target output current
in Constant Current (CC) regulation. The values of RCS and RLC can be determined by the equations below. The
term ηXFMR is intended to account for the energy stored in the transformer but not delivered to the secondary.
This includes transformer resistance and core loss, bias power, and primary-to-secondary leakage ratio.
Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%,
and bias power to output power ratio of 1.5%. The ηXFMR value is approximately: 1 - 0.05 - 0.035 - 0.015 = 0.9.
V
´ NPS
RCS = CCR
´ hXFMR
2IOCC
where
•
•
•
•
RLC =
VCCR is a current regulation constant (see ELECTRICAL CHARACTERISTICS),
NPS is the transformer primary-to-secondary turns ratio (a ratio of 13 to 15 is recommended for 5-V output),
IOCC is the target output current in constant-current regulation,
ηXFMR is the transformer efficiency.
(3)
KLC ´ RS1 ´ RCS ´ tD ´ NPA
LP
where
•
•
•
•
•
•
RS1 is the VS pin high-side resistor value,
RCS is the current-sense resistor value,
t D is the current-sense delay including NPN transistor turn-off delay, add ~50 ns to transistor delay,
NPA is the transformer primary-to-auxiliary turns ratio,
LP is the transformer primary inductance,
KLC is a current-scaling constant (see ELECTRICAL CHARACTERISTICS).
(4)
CBC (Cable Compensation): The cable compensation pin is connected to a resistor to ground to program the
amount of output voltage compensation to offset cable resistance. The cable compensation block provides a 0-V
to 3-V voltage level on the CBC pin corresponding to IOCC(max) output current. Connecting a resistance from CBC
to GND programs a current that is summed into the VS feedback divider, increasing the regulation voltage as
IOUT increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum cable
compensation of a 5-V output to 400 mV when CBC is shorted to ground. The CBC resistance value can be
determined by the equation below.
where
•
•
•
•
•
VOCV is the regulated output voltage,
VF is the diode forward voltage in V,
VOCBC is the target cable compensation voltage at the output terminals,
VCBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see
ELECTRICAL CHARACTERISTICS),
VVSR is the CV regulating level at the VS input (see ELECTRICAL CHARACTERISTICS).
(5)
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
9
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
TYPICAL CHARACTERISTICS
VDD = 25 V, unless otherwise noted.
10
10.000
IRUN, VDD = 25V
1
IVDD - Operating current - mA
IVDD- Bias supply current - mA
VDD off
Run state
0.1
0.01
VDD on
0.001
Startup state
0.0001
1.000
IWAIT, VDD = 25V
0.100
ISTART, VDD = 18V
0.010
0.00001
0
10
20
30
40
VVDD - Input voltage - V
0.001
C001
-50
-25
0
25
50
75
100
TJ - Temperature - ƒC
Figure 1. Bias Supply Current vs. VDD Voltage
250
IVS - VS pin current threshold - µA
VVSR - VS Regulating Voltage - V
4.15
4.1
4.05
4
3.95
Start
200
150
100
50
Stop
0
3.9
±50
±25
0
25
50
75
100
-50
125
TJ - Junction Temperature - °C
VVS = 3.7V
600.0
500.0
400.0
VVS = 4.35V
200.0
100.0
0.0
-50
-25
0
25
50
75
TJ - Junction temperature - ƒC
100
125
VCCR - Constant current regulating level - mV
800.0
300.0
0
25
50
75
100
TJ - Junction temperature - ƒC
125
C004
Figure 4. VS Pin Start and Stop Thresholds vs. Junction
Temperature
900.0
700.0
-25
C003
Figure 3. VS Pin Regulation Voltage vs. Junction
Temperature
VCST(min) - Min current sense threshold- mV
C002
Figure 2. Operating Current vs. Junction Temperature
4.2
340.0
335.0
330.0
325.0
320.0
-50
-25
0
25
50
75
TJ- Junction temperature - ƒC
C005
Figure 5. Current Sense Threshold vs. Temperature
10
125
100
125
C006
Figure 6. Constant Current Regulation Level vs. Junction
Temperature
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
TYPICAL CHARACTERISTICS (continued)
VDD = 25 V, unless otherwise noted.
fSW(max) - Maximum switching freq. - kHz
fSW(min) - Min. switching freq. - Hz
700
690
680
670
660
650
640
630
620
610
600
-50
-25
0
25
50
75
100
TJ - Junction temperature - ƒC
85.00
84.00
83.00
82.00
81.00
80.00
79.00
78.00
77.00
76.00
75.00
-50
125
25
50
75
100
125
C012
Figure 8. Maximum Switching Frequency vs. Junction
Temperature
1.60
35.00
RDRVLS - Driver low side resistance -
40.00
IDRS - Driver source current - mA
0
TJ - Junction temperature - ƒC
Figure 7. Minimum Switching Frequency vs. Junction
Temperature
VVS = 3.7V
30.00
25.00
20.00
VVS = 4.35V
15.00
VDRV=2V, VVDD = 9V
10.00
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
-50
-25
0
25
50
75
100
TJ - Junction temperature - ƒC
125
-50
4.66
4.64
4.62
4.6
4.58
4.56
4.54
-25
0
25
50
75
TJ - Junction temperature - ƒC
100
125
25
50
75
100
125
C009
Figure 10. Driver Pull Down Resistance vs. Junction
Temperature
227.00
226.00
225.00
224.00
223.00
222.00
221.00
220.00
219.00
-50
-25
0
25
50
75
100
TJ - Junction temperature - ƒC
C010
Figure 11. Over Voltage Protection Threshold vs. Junction
Temperature
0
TJ - Junction temperature - ƒC
IHV - High voltage charging current - µA
4.68
-50
-25
C008
Figure 9. Driver Output Source Current vs. Junction
Temperature
VOVP - Over voltage protection threshold - V
-25
C007
125
C011
Figure 12. HV Charging Current vs. Junction Temperature
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
11
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The UCC28720 is a flyback power supply controller which provides accurate voltage and constant current
regulation with primary-side feedback, eliminating the need for opto-coupler feedback circuits. The controller
operates in discontinuous conduction mode with valley-switching to minimize switching losses. The modulation
scheme is a combination of frequency and primary peak current modulation to provide high conversion efficiency
across the load range. The control law provides a wide-dynamic operating range of output power which allows
the power designer to achieve the <10-mW stand-by power requirement.
During low-power operating ranges the device has power management features to reduce the device operating
current at operating frequencies below 28 kHz. Accurate voltage and constant current regulation, fast dynamic
response, and fault protection are achieved with primary-side control. A complete charger solution can be
realized with a straightforward design process, low cost and low component count.
Primary-Side Voltage Regulation
Figure 13 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown.
The power train operation is the same as any DCM flyback circuit but accurate output voltage and current
sensing is the key to primary-side control.
Bulk Voltage
Secondary
Winding
Primary Winding
VOUT
Cout Rload
Timing
Aux
Winding
RS1
VS
Discriminator
and Sampler
VCL
RS2
Zero Crossings
Control
Law
GD
DRV
-
Minimum
Period
And Peak
Primary
Current
CS
RCS
UDG -13093
Figure 13. Simplified Flyback Convertor
(with the main voltage regulation blocks)
12
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer
energy to the secondary. As shown in Figure 14 it is clear there is a down slope representing a decreasing total
rectifier VF and resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an
accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably
recognizes the leakage inductance reset and ringing and ingores it, continuously samples the auxiliary voltage
during the down slope after the ringing is diminished, and captures the error signal at the time the secondary
winding reaches zero current. The internal reference on VS is 4.05 V. Temperature compensation on the VS
reference voltage of -0.8-mV/°C offsets the change in the output rectifier forward voltage with temperature. The
resistor divider is selected as outlined in the VS pin description.
Figure 14. Auxiliary Winding Voltage
The UCC28720 includes a VS signal sampler that uses discrimination methods to ensure an accurate sample of
the output voltage from the auxiliary winding. There are some conditions that must be met on the auxiliary
winding signal to ensure reliable operation. These conditions are the reset time of the leakage inductance and
the duration of any subsequent leakage inductance ring. Refer to Figure 15 below for a detailed illustration of
waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the
leakage inductance reset pedestal, tLK_RESET in Figure 15. Because this can mimic the waveform of the
secondary current decay, followed by a sharp downslope, it is important to keep the leakage reset time less than
600 ns for IPRI minimum, and less than 2.2 µs for IPRI maximum. The second detail is the amplitude of ringing on
the VAUX waveform following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately
100 mVp-p at least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive
ringing, it usually occurs during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on
VS scales up when measured at the auxiliary winding by RS1 and RS2, and is equal to 100 mV x (RS1 + RS2) / RS2
when measured directly at the auxilliary winding.
tLK_RESET
tSMPL
VS ring(p-p)
tDM
UDG-12202
Figure 15. Auxiliary Waveform Details
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
13
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode
as illustrated in Figure 16 below. The internal operating frequency limits of the device are 80 kHz, fSW(max) and 65
Hz, fSW(min). The transformer primary inductance and primary peak current chosen sets the maximum operating
frequency of the converter. The output preload resistor and efficiency at low power determines the converter
minimum operating frequency. There is no stability compensation required for the UCC28720.
Control Law Profile in Constant Voltage(CV) Mode
80 kHz
fSW(max)
I PP (peak primary current)
fSW (1 / MINP)
I PP(max )
I PP
fSW
28 kHz
FM
AM
I PP(max ) / 4.0
FM
f SW(min)
3.3 kHz
0.75 V 1.3 V
2.2 V
3.55 V
Control Voltage , E/A Output - VCL
5V
UDG-13095
Figure 16. Frequency and Amplitude Modulation Modes
(during voltage regulation)
14
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
Primary-Side Current Regulation
Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary
average current. The control law dictates that as power is increased in CV regulation and approaching CC
regulation the primary-peak current is at IPP(max). Referring to Figure 17 below, the primary-peak current, turns
ratio, secondary demagnetization time (tDM), and switching period (tSW) determine the secondary average output
current. Ignoring leakage inductance effects, the average output current is given by Equation 6. When the
average output current reaches the regulation reference in the current control block, the controller operates in
frequency modulation mode to control the output current at any output voltage at or below the voltage regulation
target as long as the auxiliary winding can keep VDD above the UVLO turn-off threshold.
IPP
IS × NS/NP
tON
tDM
tSW
UDG-12203
Figure 17. Transformer Currents
I
N
t
IOUT = PP ´ P ´ DM
2 NS tSW
(6)
VOCV
5.25
5
Output Voltage (V)
4.75
4
±5%
3
2
1
Output Current
IOCC
UDG-12201
Figure 18. Typical Target Output V-I Characteristic
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
15
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
Valley Switching
The UCC28720 utilizes valley switching to reduce switching losses in the transistor, to reduce induced-EMI, and
to minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all load
conditions unless the collector voltage (VC) ringing has subsided.
Referring to Figure 19 below, the UCC28720 operates in a valley-skipping mode in most load conditions to
maintain an accurate voltage or current regulation point and still switch on the lowest available VC.
VC
VDRV
UDG-13091
Figure 19. Valley-Skipping Mode
Start-Up Operation
The internal high-voltage start-up switch connected to the bulk capacitor voltage (VBLK) through the HV pin
charges the VDD capacitor. During start up there is typically 300 µA available to charge the VDD capacitor.
When VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the converter starts switching
and the start-up switch is turned off. The initial three cycles are limited to IPP(min). After the initial three cycles at
minimum IPP(min), the controller responds to the condition dictated by the control law. The converter will remain in
discontinuous mode during charging of the output capacitor(s), maintaining a constant output current until the
output voltage is in regulation.
16
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
Fault Protection
The UCC28720 provides comprehensive fault protection. Protection functions include:
• Output over-voltage fault
• Input under-voltage fault
• Internal over-temperature fault
• Primary over-current fault
• CS pin fault
• VS pin fault
A UVLO reset and restart sequence applies for all fault protection events.
The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on
VS exceeds 115% of the nominal VOUT, the device stops switching and the internal current consumption is IFAULT
which discharges the VDD capacitor to the UVLO turn-off threshold. After that, the device returns to the start
state and a start-up sequence ensues.
The UCC28720 always operates with cycle-by-cycle primary peak current control. The normal operating range of
the CS pin is 0.78 V to 0.195 V. There is additional protection if the CS pin reaches 1.5 V. This results in a UVLO
reset and restart sequence.
The line input run and stop thresholds are determined by current information at the VS pin during the transistor
on-time. While the VS pin is clamped close to GND during the transistor on-time, the current through RS1 is
monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds
allows clean start-up and shut-down of the power supply with the line voltage. The run current threshold is 225
µA and the stop current threshold is 80 µA.
The internal over-temperature protection threshold is 165°C. If the junction temperature reaches this threshold
the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
17
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
DESIGN PROCEDURE
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28720 controller. Refer to the Figure 20 for component names and network locations. The design procedure
equations use terms that are defined below.
VBLK
+
CB1
+ VF -
CB2
RPL
Ns
Np
COUT
VOUT
–
VAC
UCC28720
SOIC-7
VAUX + VFA HV
VDD
Na
CDD
RS1
DRV
VS
CS
RLC
CBC
RS2
RCS
R CBC
GND
UDG-13091
Figure 20. Design Procedure Application Example
Definition of Terms
Capacitance Terms in Farads
• CBULK: total input capacitance of CB1 and CB2.
• CDD: minimum required capacitance on the VDD pin.
• COUT: minimum output capacitance required.
Duty Cycle Terms
• DMAGCC: secondary diode conduction duty cycle in CC, 0.425.
• DMAX: transistor on-time duty cycle.
Frequency Terms in Hertz
• fLINE: minimum line frequency.
• fMAX: target full-load maximum switching frequency of the converter.
• fMIN: minimum switching frequency of the converter, add 15% margin over the fSW(min) limit of the device.
• fSW(min): minimum switching frequency (see ELECTRICAL CHARACTERISTICS).
Current Terms in Amperes
• IOCC: converter output constant-current target.
• IPP(max): maximum transformer primary current.
• ISTART: start-up bias supply current (see ELECTRICAL CHARACTERISTICS).
• ITRAN : required positive load-step current.
• IVSL(run): VS pin run current (see ELECTRICAL CHARACTERISTICS).
• IDRS: Driver source current (see ELECTRICAL CHARACTERISTICS).
18
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
Current and Voltage Scaling Terms
• KAM: maximum-to-minimum peak primary current ratio (see ELECTRICAL CHARACTERISTICS).
• KLC: current-scaling constant (see ELECTRICAL CHARACTERISTICS).
Transformer Terms
• LP: transformer primary inductance.
• NAS: transformer auxiliary-to-secondary turns ratio.
• NPA: transformer primary-to-auxiliary turns ratio.
• NPS: transformer primary-to-secondary turns ratio.
Power Terms in Watts
• PIN: converter maximum input power.
• POUT: full-load output power of the converter.
• PRSTR: VDD start-up resistor power dissipation.
• PSB: total stand-by power.
• PSB_CONV: PSB minus start-up resistor and snubber losses.
Resistance Terms in Ω
• RCS: primary current programming resistance.
• RESR: total ESR of the output capacitor(s).
• RPL: preload resistance on the output of the converter.
• RS1: high-side VS pin resistance.
• RS2: low-side VS pin resistance.
Timing Terms in Seconds
• tD: current-sense delay including transistor turn-off delay; add 50 ns to transistor delay.
• tDMAG(min): minimum secondary rectifier conduction time.
• tON(min): minimum transistor on time.
• tR: resonant frequency during the DCM (discontinuous conduction mode) time.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
19
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
Voltage Terms in Volts
• VBLK: highest bulk capacitor voltage for stand-by power measurement.
• VBULK(min): minimum voltage on CB1 and CB2 at full power.
• VOCBC: target cable compensation voltage at the output terminals.
• VCBC(max): maximum voltage at the CBC pin at the maximum converter output current (see ELECTRICAL
CHARACTERISTICS).
• VCCR: constant-current regulating voltage (see ELECTRICAL CHARACTERISTICS).
• VCST(max): CS pin maximum current-sense threshold (see ELECTRICAL CHARACTERISTICS).
• VCST(min): CS pin minimum current-sense threshold (see ELECTRICAL CHARACTERISTICS).
• VDD(off): UVLO turn-off voltage (see ELECTRICAL CHARACTERISTICS).
• VDD(on): UVLO turn-on voltage (see ELECTRICAL CHARACTERISTICS).
• VOΔ: output voltage drop allowed during the load-step transient.
• VCPK: peak transistor collector to emitter voltage at high line.
• VF: secondary rectifier forward voltage drop at near-zero current.
• VFA: auxiliary rectifier forward voltage drop.
• VLK: estimated leakage inductance energy reset voltage.
• VOCV: regulated output voltage of the converter.
• VOCC: target lowest converter output voltage in constant-current regulation.
• VREV: peak reverse voltage on the secondary rectifier.
• VRIPPLE: output peak-to-peak ripple voltage at full-load.
• VVSR: CV regulating level at the VS input (see ELECTRICAL CHARACTERISTICS).
AC Voltage Terms in VRMS
• VIN(max): maximum input voltage to the converter.
• VIN(min): minimum input voltage to the converter.
• VIN(run): converter input start-up (run) voltage.
Efficiency Terms
• ηSB: estimated efficiency of the converter at no-load condition, not including start-up resistance or bias losses.
For a 5-V USB charger application, 60% to 65% is a good initial estimate.
• η: converter overall efficiency.
• ηXFMR: transformer primary-to-secondary power transfer efficiency.
20
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
Stand-by Power Estimate
Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on
target converter maximum switching frequency and output power rating.
The following equation estimates the stand-by power of the converter.
(7)
For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on
25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in
the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias
power estimated at 2.5 mW.
(8)
The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement,
typically 325 VDC.
For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by
power loss.
PSB = PSB _ CONV + 2.5 mW
(9)
Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum
Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target.
(10)
The below equation provides an accurate solution for input capacitance based on a target minimum bulk
capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the
target capacitance.
(11)
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
21
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.
Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on
target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have
an estimate from previous designs. For the transition mode operation limit, the period required from the end of
secondary current conduction to the first valley of the VCE voltage is ½ of the DCM resonant period, or 1 µs
assuming 500-kHz resonant frequency. DMAX can be determined using the equation below.
æt
ö
DMAX = 1 - ç R ´ fMAX ÷ - DMAGCC
è 2
ø
(12)
Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation
below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It
is set internally by the UCC28720 at 0.425. The total voltage on the secondary winding needs to be determined;
which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V
USB charger applications, a turns ratio range of 13 to 15 is typically used.
(13)
Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following
parameters.
The UCC28720 constant-current regulation is achieved by maintaining a maximum DMAG duty cycle of 0.425 at
the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage
determine the current sense resistor for a target constant current.
Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term
is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias
power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An
overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding
loss, and 1.5% bias power.
V
´ NPS
RCS = CCR
´ hXFMR
2IOCC
(14)
The primary transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency and output and transformer power losses are
included in the equation below. Initially determine transformer primary current.
Primary current is simply the maximum current sense threshold divided by the current sense resistance.
(15)
(16)
The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target
operating output voltage in constant-current regulation and the VDD UVLO of the UCC28720. There is additional
energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be
used in many designs.
(17)
22
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
UCC28720
www.ti.com
SLUSBE8 – MAY 2013
Transformer Parameter Verification
The transformer turns ratio selected affects the transistor VC and secondary rectifier reverse voltage so these
should be reviewed. The UCC28720 does require a minimum on time of the transistor (tON) and minimum DMAG
time (tDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of fMAX, LP and RCS
affects the minimum tON and tDMAG.
The secondary rectifier and transistor voltage stress can be determined by the equations below.
(18)
For the transistor VC voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.
(
)
VCPK = VIN (max) ´ 2 + (VOCV + VF + VOCBC )´ NPS + VLK
(19)
Equation 20 and Equation 21 are used to determine if the minimum tON target of 300 ns and minimum tDMAG
target of 1.2 µs is achieved.
IPP(max ) ´ VCST(min )
LP
tON(min ) =
´
VCST(max )
VIN max ´ 2
(
tDMAG(min ) =
)
(20)
tON ´ VIN(max ) ´ 2
NPS ´ (VOCV + VF )
(21)
Output Capacitance
The output capacitance value is typically determined by the transient response requirement from no-load. For
example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a
load-step transient of 0 mA to 500 mA . The equation below assumes that the switching frequency can be at the
UCC28720 minimum of fSW(min).
(22)
Another consideration of the output capacitor(s) is the ripple voltage requirement which is reviewed based on
secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation
below.
(23)
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
23
UCC28720
SLUSBE8 – MAY 2013
www.ti.com
VDD Capacitance, CDD
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain
the voltage to the UCC28720. The total output current available to the load and to charge the output capacitors is
the constant-current regulation target. The equation below assumes the output current of the flyback is available
to charge the output capacitance until the minimum output voltage is achieved. There is 1 V of margin added to
VDD in the calculation.
(I
RUN
CDD =
COUT ´ VOCC
IO
(VDD(on ) - VDD(off ) )- 1 V
+ L DRS(max) ´ (1 - D magcc ) ))´
(24)
VS Resistor Divider, Line Compensation, and Cable Compensation
The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side
divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1
is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating
threshold.
(25)
The low-side VS pin resistor is selected based on desired VO regulation voltage.
(26)
The UCC28720 can maintain tight constant-current regulation over input line by utilizing the line compensation
feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected base
drive and transistor turn-off delay. Assume a 50-ns internal delay in the UCC28720.
K ´ RS1 ´ RCS ´ tD ´ NPA
RLC = LC
LP
(27)
The UCC28720 has adjustable cable drop compensation. The resistance for the desired compensation level at
the output terminals can be determined using Equation 28.
(28)
24
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: UCC28720
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
UCC28720D
ACTIVE
SOIC
D
7
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
U28720
UCC28720DR
ACTIVE
SOIC
D
7
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
U28720
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28720DR
Package Package Pins
Type Drawing
SOIC
D
7
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28720DR
SOIC
D
7
2500
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated