SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FEATURES D High Accuracy, Better Than 1% CurrentShare D D D D D D D D D DESCRIPTION The UCC39002 is an advanced, high performance and low cost loadshare controller that provides all necessary functions to parallel multiple independent power supplies or dc-to-dc modules. Targeted for high reliability applications in server, workstation, telecom and other distributed power systems, the controller is suitable for N+1 redundant systems or high current applications where off-the-shelf power supplies need to be paralleled. Error at Full Load High-Side or Low-Side (GND Reference) Current-Sense Capability Ultra-Low Offset Current Sense Amplifier Single Wire Load Share Bus Full Scale Adjustability Intel SSI LoadShare Specification Compliant Disconnect from Load Share Bus at Stand-By Load Share Bus Protection Against Shorts to GND or to the Supply Rail 8-Pin MSOP Package Minimizes Space Lead-Free Assembly The BiCMOS UCC39002 is based on the automatic master/slave architecture of the UC3902 and UC3907 load share controllers. It provides better than 1% current share error between modules at full load by using a very low offset post-package-trimmed current-sense amplifier and a high-gain negative feedback loop. And with the amplifier’s common mode range of 0-V to the supply rail, the current sense resistor, RSHUNT, can be placed in either the GND return path or in the positive output rail of the power supply. SYSTEM CONFIGURATIONS D Modules With Remote Sense Capability D Modules With Adjust Input D Modules With Both Remote Sense and Adjust D Input In Conjunction With the Internal Feedback E/A of OEM Power Supply Units TYPICAL LOW-SIDE CURRENT SENSING APPLICATION V+ RADJ CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 S− LOAD SYSTEM+− POWER SUPPLY WITH REMOTE SENSE CS− SYSTEM+ UCC39002 1 LS BUS S+ RSHUNT V− ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) Copyright 2007, Texas Instruments Incorporated 1 www.ti.com o SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESCRIPTION (continued) The functionality of the UCC29002/1 differs slightly compared to the UCC39002. The UCC39002 will force the maximum adjustment range at start up to quickly engage load sharing; the UCC29002/1 ADJ amplifier will operate in a linear mode during start up, resulting in a more gradual load sharing at turn on. During transient conditions while adding or removing power supplies, the UCC39002 protects the system by keeping the load share bus disconnected from the remaining supplies. By disabling the adjust function in case a short of the load share bus occurs to either GND or the supply rail, it also provides protection for the system against erroneous output voltage adjustment. The UCC39002 also meets Intel’s SSI (Server System Infrastructure) loadshare specifications of a single-line load share bus and scalable load share voltage for any level of output currents. The UCC39002 family is offered in 8-pin MSOP (DGK), SOIC (D), and PDIP (P) packages. absolute maximum ratings over operating free-air temperature (unless otherwise noted)}w Supply voltage, current limited (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V Supply voltage, voltage source (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V Input voltage, current sense amplifier (VCS+, VCS−) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V Current sense amplifier output voltage (VCSO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD Load share bus voltage (VLS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD Supply current (IDD + IZENER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Adjust pin input voltage (VADJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEAO +1 V < VADJ ≤ VDD Adjust pin sink current (IADJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mA Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead Temperature, Tsol (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. § All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. PDIP (P) PACKAGE (TOP VIEW) SOIC (D) OR MSOP (DGK) PACKAGE (TOP VIEW) CS− CS+ VDD GND 1 8 2 7 3 6 4 5 CS− CS+ VDD GND CSO LS EAO ADJ 1 8 2 7 3 6 4 5 CSO LS EAO ADJ AVAILABLE OPTIONS PACKAGED DEVICES TA = TJ −40°C to 105°C 0°C to 70°C SOIC−8 (D)† MSOP−8 (DGK)† PDIP−8 (P) UCC29002D UCC29002DGK UCC29002P UCC29002D/1 UCC29002DGK/1 NA UCC39002D UCC39002DGK UCC39002P † The D and DGK packages are available taped and reeled. Add R suffix to device type (e.g. UCC39002DR) to order quantities of 2,500 devices per reel. 2 www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 electrical characteristics VDD = 12 V, 0°C < TA < 70°C for the UCC39002, −40°C < TA < 105°C for the UCC29002 and UCC29002/1, TA = TJ (unless otherwise noted) general PARAMETER TEST CONDITIONS Supply current LS with no load, VDD clamp voltage IDD = 6 mA MIN TYP ADJ = 5 V MAX UNITS 2.5 3.5 13.50 14.25 15.00 mA V UNITS undervoltage lockout MIN TYP MAX Start-up voltage(1) PARAMETER TEST CONDITIONS 4.175 4.375 4.575 Hysteresis 0.200 0.375 0.550 MIN TYP MAX UNITS 100 µV V current sense amplifier PARAMETER TEST CONDITIONS TA = 25_C VIC = 0.5 V or 11.5 V, VCSO = 5 V Over-temperature variation −100 VIO Input offset voltage AV CMRR Gain 75 90 Common mode rejection ratio 75 90 IBIAS Input bias current (CS+, CS−) VOH High-level output voltage (CSO) VOL Low-level output voltage (CSO) IOH IOL High-level output current (CSO) GBW Low-level output current (CSO) Gain bandwidth product(2) ±10 −0.6 0.1 V ≤ ([CS+] − [CS−]) ≤ 0.4 V, IOUT_CSO = 0 mA −0.4 V ≤ ([CS+] − [CS−]) ≤ 0.1 V, IOUT_CSO = 0 mA VCSO = 10 V µV/_C dB 0.6 10.7 11.0 11.8 0.00 0.10 0.15 −1 −1.5 1 1.5 µA V VCSO = 1 V mA 2 MHz load share driver (LS) PARAMETER VRANGE TEST CONDITIONS MIN Input voltage range TYP MAX 0 VOUT Output voltage VCSO = 1 V VCSO = 10 V VOL VOH Low-level output voltage VCSO = 0 V, IOUT ISC Output current 0.5 V ≤ VLS ≤ 10 V Short circuit current VSHTDN Driver shutdown threshold VLS = 0 V, VCS− − VCS+ IOUT_LS = 0 mA High-level output voltage(2) UNITS 10 0.995 1 1.005 9.995 10 10.005 0.00 0.10 0.15 V VDD−1.7 −1 −1.5 VCSO = 10 V −10 −20 0.3 0.5 mA 0.7 V load share bus protection PARAMETER IADJ (1) (2) Adjust amplifier current TEST CONDITIONS VCSO = 2 V, VEAO = 2 V, VCSO = 2 V, VEAO = 2 V, VLS = VDD , VADJ = 5 V VLS = 0 V, VADJ = 5 V MIN TYP MAX 0 5 10 0 5 10 UNITS A µA Enables the load share bus at start-up. Ensured by design. Not production tested. www.ti.com 3 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 electrical characteristics VDD = 12 V, 0°C < TA < 70°C for the UCC39002, −40°C < TA < 105°C for the UCC29002 and UCC29002/1, TA = TJ (unless otherwise noted) (continued) error amplifier PARAMETER TEST CONDITIONS VOH gM High-level output voltage IOH MIN TYP 3.50 Transconductance IOUT_EAO = 0 mA IEAO = ± 50 µA High-level output current VLS − VCSO = 0.4 V,REAO = 2.2 kΩ 0.70 MAX 3.65 3.80 14 0.85 UNITS V mS 1.00 mA MAX UNITS ADJ buffer PARAMETER TEST CONDITIONS Input offset voltage(2) VIO ISINK VADJ = 1.5 V, VADJ = 5.0 V, Sink current ISINK Sink current TA = 25_C 0_C ≤ TA ≤ 70_C −40_C ≤ TA ≤ 105_C (1) (2) VADJ = 5.0 V, LS = floating MIN VEAO = 0 V, VEAO= 0 V VEAO= 2.0 V TYP −60 mV 0 5 10 3.60 3.95 4.30 3.45 3.95 4.45 3.35 3.95 4.55 µA mA Enables the load share bus at start-up. Ensured by design. Not production tested. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION ADJ 5 O CS− 1 I Adjust amplifier output. This is the buffered output of the error amplifier block to adjust output voltage of the power supply being controlled. This pin must always be connected to a voltage equal to or greater than VEAO + 1 V. Current sense amplifier inverting input. CS+ 2 I Current sense amplifier non-inverting input. CSO 8 O Current sense amplifier output. EAO 6 O Output for load share error amplifier. (Transconductance error amplifier.) GND 4 − Ground. Reference ground and power ground for all device functions. Return the device to the low current sense− path of the converter. LS 7 I/O VDD 3 I 4 Load share bus. Output of the load share bus driver amplifier. Power supply providing bias to the device. Bypass with a good quality, low ESL 0.1-µF to 1-µF, maximum, capacitor as close to the VDD pin and GND as possible. www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 typical high-side current sensing application RSHUNT V+ RADJ S+ UCC39002 POWER SUPPLY WITH REMOTE SENSE 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 S− V− RSHUNT V+ RADJ S+ UCC39002 POWER SUPPLY WITH REMOTE SENSE 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 LOAD S− V− RSHUNT V+ RADJ S+ UCC39002 POWER SUPPLY WITH REMOTE SENSE 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 S− V− www.ti.com 5 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 functional block diagram Current Sense Amp CS− 1 8 CSO Disconnect Switch + + CS+ 2 VBIAS VDD Enable and Bias OK 7 LS Load Share Bus Receiver + 3 100 kΩ Error Amp + gM 13.5 V to 15 V GND Load Share Bus Driver 4 Fault Protection 6 EAO 3V Start Up and Adjust Logic 3V 5 ADJ Adjust Amp + 500 Ω UDG−02086 6 www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION differential current sense amplifier (CS+, CS−, CSO) The UCC39002 features a high-gain and high-precision amplifier to measure the voltage across a low-value current sense resistor. Since the amplifier is fully uncommitted, the current sense gain is user programmable. The extremely low input offset voltage of the UCC39002 current sense amplifier makes it suitable to measure current information across a low value sense resistor. Furthermore, the input common mode range includes ground and the positive supply rail of the UCC39002 (VDD). Accordingly, the current sense resistor can be placed in the ground return path or in the positive output rail of the power supply VO as long as VO ≤ VDD. The current sense amplifier is not unity gain stable and must have a minimum gain of three. load share bus driver amplifier (CSO) This is a unity-gain buffer amplifier to provide separation between the load share bus voltage and the output of the current sense amplifier. The circuit implements an ideal diode with virtually 0 V forward voltage drop by placing the diode inside the feedback loop of the amplifier. The diode function is used to automatically establish the role of the master module in the system. The UCC39002 which is assigned to be the master uses the load share bus driver amplifier to copy its output current information on to the load share bus. All slave units, with lower output current levels by definition, have this “ideal diode” reversed biased (VCSO < VLS). Consequently, the VCSO and VLS signals will be separated. That allows the error amplifier of the UCC39002 to compare its respective module’s output current to the master module’s output current and make the necessary corrections to achieve a balanced current distribution. Since the bus is always driven by a single load share bus driver amplifier, the number of modules (n) are limited by the output current capability of the amplifier according to: n+ 100 kW I OUT,MIN V LS,FULL_SCALE (1) where 100 kΩ is the input impedance of the LS pin as shown in the block diagram, IOUT,MIN is given in the data sheet and VLS,FULL_SCALE is the maximum voltage on the load share bus at full load. Note that the number of parallel units can be increased by reducing the full scale bus voltage, i.e. by reducing the current sense gain. load share bus receiver amplifier (LS) The load share bus receiver amplifier is a unity gain buffer monitoring the load share bus voltage. Its primary purpose is to ensure that the load share bus is not loaded by the internal impedances of the UCC39002. The LS pin is already internally compensated and has an internal 15-kHz filter. Adding external capacitance, including stray capacitance, should be avoided to maintain stability. www.ti.com 7 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION error amplifier (EAO) As pictured in the block diagram, the UCC39002 employs a transconductance also called gM type error amplifier. The gM amplifier was chosen because it requires only one pin, the output to be accessible for compensation. The purpose of the error amplifier is to compare the average, per module current level to the output current of the respective module controlled by the UCC39002. It is accommodated by connecting the buffered VLS voltage to its non−inverting input and the VCSO signal to its inverting input. If the average per module current, represented by the load share bus is higher than the module’s own output current, an error signal will be developed across the compensation components connected between the EAO pin and ground. The error signal is than used by the adjust amplifier to make the necessary output voltage adjustments to ensure equal output currents among the parallel operated power supplies. In case the UCC39002 assumes the role of the master load share controller in the system or it is used in conjunction with a stand alone power module, the measured current signal on VCSO is approximately equal to the VLS voltage. To avoid erroneous output voltage adjustment, the input of the error amplifier incorporates a typically 25 mV offset to ensure that the inverting input of the error amplifier is biased higher than the non−inverting input. Consequently, when the two signals are equal, there will be no adjustment made and the initial output voltage set point is maintained. adjust amplifier output (ADJ) A current proportional to the error voltage VEAO on pin 6 is sunk by the ADJ pin. This current flows through the adjust resistor RADJ and changes the output voltage of the module controlled by the UCC39002. The amplitude of the current is set by the 500-Ω internal resistor between ground and the emitter of the amplifier’s open collector output transistor according to Figure 1. The adjust current value is given as: I ADJ + V EAO 500 W (2) At the master module VEAO is 0 V, thus the adjust current must be zero as well. This ensures that the output voltage of the master module remains at its initial output voltage set point at all times. Furthermore, at insufficient bias level, during a fault or when the UCC39002 is disabled, the non-inverting input of the adjust amplifier is pulled to ground to prevent erroneous adjustment of the module’s output voltage by the load share controller. 8 www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION enable function (CS+, CS−) The two inputs of the current sense amplifier are also used for implementing an ENABLE function. During normal operation CS− = CS+ and the internal offset added between the CS− voltage and the inverting input of the enable comparator ensures that the UCC39002 is always enabled. By forcing the CS− pin approximately 0.5-V above the CS+ pin, the UCC39002 can be forced into a disable mode. While disabled, the UCC39002 disconnects itself from the load share bus and its adjust current is zero. CS+ 2 + ENABLE + 0.5 V CS− 1 UDG−02087 Figure 1. Enable Comparator fault protection Accidentally, the load share bus might be shorted to ground or to the positive bias voltage of the UCC39002. These events might result in erroneous output voltage adjustment. For that reason, the load share bus is continuously monitored by a window comparator as shown in Figure 2. VDD − 0.7 V + LS 7 FAULT + R CSO 8 2R UDG−02088 Figure 2. Fault Protection Comparators The FAULT signal is handled by the start up and adjust logic which pulls the non-inverting input of the adjust amplifier low when the FAULT signal is asserted. www.ti.com 9 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION start up and adjust logic The start up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states. Similarly, the driver amplifier of UCC39002 is disabled during these conditions. In the UCC39002/UCC29002, during start up, the load share driver amplifier is disabled by the disconnect switch and the adjust amplifier is forced to sink the maximum current through the adjust resistor. This operating mode ensures that the module controlled by the UCC39002 will be able to quickly engage in sharing the load current since its output will be adjusted to a sufficiently high voltage immediately at turn on. Both the load share driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of the average per module current level represented by the LS bus voltage. The UCC29002/1 does not have this logic at start up. In this way, the UCC29002/1 will not adjust the output of the module to its maximum adjustment range at turn on and engages load sharing at more moderate rate. In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the CS+ and CS− pins or when the bias voltage is below the minimum operating voltage. bias and bias OK circuit (VDD) The UCC39002 is built on a 15-V, high performance BiCMOS process. Accordingly the maximum voltage across the VDD and GND pins (pin 3 and 4 respectively) is limited to 15 V. The recommended maximum operating voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the bias voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor. The current into the VDD pin must be limited to 10 mA as listed in the absolute maximum ratings table. The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such, must be placed as close to the device pins (VDD and GND) as possible, using a good quality low ESL capacitor, including trace length. The device is optimized for a capacitor value of 0.1 µF to 1 µF. VBIAS (Internal Bias) VDD 3 14.2 V GND 4 4.375 V + Bias_OK UDG−02089 Figure 3. VDD Clamp and Bias Monitor 10 www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable function with a 4.375-V threshold. While VDD < 4.375 V the load share control functions are disabled. While this might be inconvenient for some low voltage applications it is necessary to ensure high accuracy. The load share accuracy is dependent on working with relatively large signal amplitudes on the load share bus. If the internal offsets, current sense error and ground potential difference between the UCC39002 controllers are comparable in amplitude to the load share bus voltage, they can cause significant current distribution error in the system. The maximum voltage on the load share bus is limited approximately 1.7-V below the bias voltage level (VDD) which would result in an unacceptably low load share bus amplitude therefore poor accuracy at low VDD levels. To circumvent this potential design problem, the UCC39002 won’t operate below the above mentioned 4.375-V bias voltage threshold. If the system does not have a suitable bias voltage available to power the UCC39002, it is recommended to use an inexpensive charge pump which can generate the bias voltage for all the UCC39002s in the load share system. The maximum VDD of the UCC39002 is 15 V. For higher-voltage applications, use the application solution as recommended in Figure 4. A Zener clamp on the VDD pin is provided internally so the device can be powered from higher voltage rails using a minimum number of external components. The CSA inputs must be adjusted so as to not exceed their absolute maximum voltage ratings. LOAD CURRENT DIRECTION VOUT+ R ADJ SNS+ RBIAS1 LOAD POWER SUPPLY OUTPUT SYSTEM GROUND UCC39002 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 LS BUS TO OTHER UCC39002 DEVICES CCOMP R BIAS2 C BIAS 4 GND ADJ 5 RCOMP POWER SUPPLY OUTPUT SNS− RSHUNT VOUT− Figure 4. High Voltage Application www.ti.com 11 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modules for load sharing. paralleling the power modules D D D D VOUT = nominal output voltage of the modules to be paralleled IOUT(max) = maximum output current of each module to be paralleled ∆VADJ = maximum output voltage adjustment range of the power modules to be paralleled N = number of modules NOTE: The power modules to be paralleled must be equipped with true remote sense or access to the feedback divider of the module’s error amplifier. A typical high side application for a single module is shown in Figure 5 and is repeated for each module to be paralleled. RSHUNT 0.005 Ω V+ P1 R15 274 Ω V− C13 1 nF TP11 POWER MODULE R16 16.2 kΩ R13 274 Ω RSENSE 200 Ω U1 UCC39002 1 CS− CSO 8 RADJUST R18 1 kΩ 2 CS+ Q1 LS 7 C12 V+ TP13 SB2 S+ TP12 REAO 475 Ω Load V− 3 VDD EAO 6 R19 47 kΩ R14 16.2 kΩ C11 0.47 µF 4 GND ADJ 5 CEAO 47 µF S1 S− UDG−02078 Load Share Bus Figure 5. Typical High-Side Application for Single Power Module In Figure 5, P1 represents the output voltage terminals of the module, S1 represents the remote sense terminals of the module, and a signal on the SB2 terminal will enable the disconnect feature of the device. The load share bus is the common bus between all of the paralleled load share controllers. VDD must be decoupled with a good quality ceramic capacitor returned directly to GND. 12 www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE measuring the modules’ loop Using the configuration in Figure 6, measure the unity gain crossover frequency of the power modules to be paralleled. A typical resultant bode plot is shown in Figure 7. + VIN + + VOUT DC−DC Module Load 50 Ω + SENSE XFRMR Source Out Channel A Channel B Network Analyzer UDG−02079 Figure 6. Unity Gain Crossover Frequency Measurement Connection Diagram 40 30 20 Gain − dB 10 0 −10 UNITY GAIN CROSSOVER FREQUENCY fCO = 40 Hz −20 −30 −40 1 10 100 1000 f − Frequency − Hz Figure 7. Power Module Bode Plot www.ti.com 13 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE the shunt resistor Selection of the shunt resistor is limited by its voltage drop at maximum module output current. This voltage drop should be much less than the voltage adjustment range of the module: I OUT(max) R SHUNT tt D V ADJ(max) (3) Other limitations for the sense resistor are the desired minimum power dissipation and available component ratings. the CSA gain The gain of the current sense amplifier is configured by the compensation components between Pin 1, CS−, and Pin 8, CSO, of the load share device. The voltage at the CSO pin is limited by the saturation voltage of the internal current sense amplifier and must be at least two volts less than VDD: V CSO(max) t VDD * 2 V (4) The maximum current sense amplifier gain is equal to: A CSA + V CSO ǒRSHUNT Ǔ I OUT(max) (5) Referring to Figure 5, the gain is equal to R16/R15 and a high-frequency pole, configured with C13, is used for noise filtering. This impedance is mirrored at the CS+ pin of the differential amplifier as shown. The current sense amplifier output voltage, VCSO, serves as the input to the unity gain LS bus driver. The module with the highest output voltage forward biases the internal diode at the output of the LS bus driver and determine the voltage on the load share bus, VLS. The other modules act as slaves and represent a load on the IVDD of the module due to the internal 100-kΩ resistor at the LS pin. This increase in supply current for the master module is equal to N(VLS/100 kΩ). 14 www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE determining RADJUST The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop across RADJUST due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be maintained at approximately 1 V above the voltage at the EAO pin. This is necessary in order to keep the transistor at the output of the internal adjust amplifier from saturating. To fulfill this requirement, RADJUST is first calculated using the following equation: R ADJUST w ƪ ǒDVADJ(max) * IOUT(max) V OUT * DV ADJ(max) * 1 V * Ǔ R SHUNT ǒ DV ADJ(max) R SENSE 500 W Ǔƫ 500 W (6) Where RSHUNT is the current sense resistor, and RSENSE is the internal resistance between VOUT+ and SENSE+ within the module. Also needed for consideration is the actual adjust pin current. The maximum sink current for the ADJ pin, IADJmax, is 6 mA as determined by the internal 500-Ω emitter resistor and 3-V clamp. The value of adjust resistor, RADJUST, is based upon the maximum adjustment range of the module, ∆VADJmax. This adjust resistor is determined using the following formula: R ADJUST w ƪDVADJ(max) * IOUT(max) I ADJ(max) * ƫ R SHUNT DV ADJ(max) R SENSE (7) By selecting a resistor that meets both of these minimum requirements, the ADJ pin will be at least 1 V greater than the EAO voltage and the adjust pin sink current will not exceed its 6 mA maximum. www.ti.com 15 SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE error amplifier compensation The total load-share loop unity-gain crossover frequency, fCO, should be set at least one decade below the measured crossover frequency of the paralleled modules previously measured, fCO(module). (See Figure 7) Compensation of the transconductance error amplifier is accomplished by placing the compensation resistor, REAO, and capacitor, CEAO, between EAO and GND. The values of these components is determined using equations (8) and (13). C EAO + ǒ gM 2p f CO Ǔǒ ǒŤ A CSAǓ ǒA VǓ ǒA ADJǓ A PWRǒf COǓ ŤǓ (8) Where: D D D D D D gM is the transconductance of the error amplifier, typically 14 mS, fCO is equal to the desired crossover frequency in Hz of the load share loop, typically fCO (module)/10, ACSA is the CSA gain, AV is the voltage gain, AADJ is the gain associated with the adjust amplifier, |APWR(fCO)| is the measured gain of the power module at the desired load share crossover frequency, fCO, converted to V/V from dB A CSA + R16 R15 AV + (9) R SHUNT V OUT , R LOAD + R LOAD I OUT(max) A ADJ + R ADJUST (10) R SENSE ǒRADJUST ) RSENSEǓ 500 W ǒ Ǔ ŤAPWR ǒfCOǓŤ + 10 G MODULEǒf COǓ 20 (11) (12) Where GMODULE(fco) is the measured value of the gain from Figure 7, at the desired crossover frequency. Once the CEAO capacitor is determined, REAO is selected to achieve the desired loop response: R EAO + 16 Ǹǒ Ǔ ǒ 2 gm ŤAPWR ǒfCOǓŤ 1 AV A CSA A ADJ * 1 2p ǒf COǓ ǒC EAOǓ Ǔ 2 (13) www.ti.com SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE references For further details, refer to the following document: D Reference Design, 48-VIN , 12-VOUT Loadshare System Using UCC39002 with Three DC/DC PH-100S4 Modules”, Texas Instruments Literature No. SLUA270 For a more complete description of general load sharing toics, refer to the following documents. D Application Note, The UC3902 Load Share Controller and Its Performance in Distributed Power Systems, TI Literature No. SLUA128 D Application Note, UC3907 Load Share IC Simplifies Parallel Power Supply Design, TI Literature No. SLUA147 www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC29002D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 29002 UCC29002D/1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 290021 UCC29002D/1G4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 290021 UCC29002DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 29002 UCC29002DGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 29002 UCC29002DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 29002 UCC29002DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 29002 UCC29002DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 105 29002 UCC29002DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 29002 UCC29002DR/1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 290021 UCC29002DR/1G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 290021 UCC29002DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 29002 UCC29002P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 UCC29002P UCC29002PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 UCC29002P UCC39002D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 39002 UCC39002DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 39002 UCC39002DGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) 0 to 70 39002 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC39002DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) 0 to 70 39002 UCC39002DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) 0 to 70 39002 UCC39002DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) 0 to 70 39002 UCC39002DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 39002 UCC39002DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 39002 UCC39002P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC39002P UCC39002PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC39002P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC29002DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC29002DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC29002DR/1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC39002DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC39002DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC29002DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 UCC29002DR SOIC D 8 2500 367.0 367.0 35.0 UCC29002DR/1 SOIC D 8 2500 367.0 367.0 35.0 UCC39002DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 UCC39002DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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