TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 Cap-Free, NMOS, 250-mA Low-Dropout Regulator with Reverse Current Protection Check for Samples: TPS73250-Q1 FEATURES APPLICATIONS • • • • • 1 • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B Stable With No Output Capacitor or Any Value or Type of Capacitor Input Voltage Range: 1.7 V to 5.5 V Ultralow Dropout Voltage: 40 mV Typ at 250 mA Excellent Load Transient Response, With or Without Optional Output Capacitor New NMOS Topology Provides Low Reverse Leakage Current Low Noise: 30 μVRMS Typ (10 kHz to 100 kHz) 0.5% Initial Accuracy 1% Overall Accuracy (Line, Load, and Temperature) Less Than 1-μA Max IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions – Fixed Outputs of 1.20 V to 5 V – Adjustable Outputs from 1.20 V to 5.5 V – Custom Outputs Available Post-Regulation for Switching Supplies Noise-Sensitive Circuitry such as VCOs Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors Optional Optional VIN IN VOUT OUT TPS73250-Q1 EN GND NR ON OFF Optional Typical Application Circuit for Fixed-Voltage Versions DESCRIPTION The TPS73250-Q1 family of low-dropout (LDO) voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR, and even allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. The TPS73250-Q1 uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1 μA and ideal for portable applications. The extremely low output noise (30 μVRMS with 0.1-μF CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. DRB PACKAGE 3mmx 3mm SON (TOP VIEW) OUT 1 DBV PACKAGE SOT23 (TOP VIEW) 8 IN N/C 2 7 N/C IN 1 NR/FB 3 6 N/C GND 2 EN 3 GND 4 5 EN 5 OUT 4 NR/FB DCQ PACKAGE SOT223 (TOP VIEW) TAB IS GND 6 1 IN 2 3 4 5 GND EN OUT NR/FB 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS73250-Q1 SLVSBH6 – JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE TA 40°C to 125°C (1) TYPE DESIGNATOR QUANTITY ORDERABLE PART NUMBER TOP-SIDE MARKING SOT223-6 DCQ Reel of 2500 TPS73250QDCQRQ1 73250Q SOT-23 DBV Reel of 3000 TPS73250QDBVRQ1 Preview VSON DRB Reel of 3000 TPS73250QDRBRQ1 Preview For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating junction temperature range unless otherwise noted. (1) VALUE UNIT –0.3 to 6 V VEN range –0.3 to 6 V VOUT range –0.3 to 5.5 V –0.3 to 6 V VIN range VNR, VFB range Peak output current Internally limited Output short-circuit duration Indefinite Continuous total power dissipation See Thermal Information Table Junction temperature range, TJ –55 to 150 Storage temperature range –65 to 150 °C 2 kV 750 V ESD ratings (1) 2 Human Body Model (HBM) AEC-Q100 Classification Level H2 Charged Device Model (CDM) AEC-Q100 Classification Level C3 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 THERMAL INFORMATION TPS73250-Q1 (3) THERMAL METRIC (1) (2) Junction-to-ambient thermal resistance (4) θJA (5) DRB DCQ DBV 8 PINS 6 PINS 5 PINS 47.8 70.4 180 64 θJCtop Junction-to-case (top) thermal resistance 83 70 θJB Junction-to-board thermal resistance (6) N/A N/A 35 ψJT Junction-to-top characterization parameter (7) 2.1 6.8 N/A ψJB Junction-to-board characterization parameter (8) 17.8 30.1 N/A θJCbot Junction-to-case (bottom) thermal resistance (9) 12.1 6.3 N/A (1) (2) (3) (4) (5) (6) (7) (8) (9) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. . iii. DBV: There is no exposed pad with the DBV package. (b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. . ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. . iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 3 TPS73250-Q1 SLVSBH6 – JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference MIN TA = 25°C 1.198 Output voltage range VOUT Accuracy (1) (2) VOUT Accuracy ΔVOUT%/ΔVIN Line regulation (1) TYP 1.7 Nominal TA = 25°C VIN, IOUT, and T VOUT + 0.5 V ≤ VIN ≤ 5.5 V; 10 mA ≤ IOUT ≤ 250 mA Nominal TA = 25°C VIN, IOUT, and T VOUT + 0.5 V ≤ VIN ≤ 5.5 V; 10 mA ≤ IOUT ≤ 250 mA UNIT 5.5 V 1.210 V VFB 5.5 – VDO V –0.5 0.5 –1 1.20 MAX ±0.5 –0.5 –1 VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V 1 % 0.5 ±0.5 1 0.01 1 mA ≤ IOUT ≤ 250 mA 0.002 10 mA ≤ IOUT ≤ 250 mA 0.0005 % %/V ΔVOUT%/ΔIOUT Load regulation VDO Dropout voltage (3) (VIN = VOUT (nom) – 0.1 V) IOUT = 250 mA ZO(DO) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO ICL Output current limit VOUT = 0.9 × VOUT(nom) ISC Short-circuit current VOUT = 0 V 300 IREV Reverse leakage current (4) (–IIN) VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT 0.1 10 IGND GND pin current IOUT = 10 mA (IQ) 400 550 IOUT = 250 mA 650 950 ISHDN Shutdown current (IGND) VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5, –40°C ≤ TA ≤ 100°C 0.02 1 µA IFB FB pin current 0.1 0.3 μA PSRR Power-supply rejection ratio (ripple rejection) f = 100 Hz, IOUT = 250 mA 58 f = 10 kHz, IOUT = 250 mA 37 VN Output noise voltage BW = 10 Hz – 100 kHz COUT = 10 μF, No CNR 27 × VOUT COUT = 10 μF, CNR = 0.01 μF 8.5 × VOUT tSTR Startup time VEN(HI) EN pin high (enabled) VEN(LO) EN pin low (shutdown) IEN(HI) EN pin current (enabled) TSD Thermal shutdown temperature TA Recommended operating temperature (1) (2) (3) (4) 4 40 %/mA 150 Ω 0.25 250 VOUT = 3 V, RL = 30 Ω COUT = 1 μF, CNR = 0.01 μF 425 mV 600 mA mA μA μA dB μVRMS μs 600 1.7 VIN 0 0.5 V 0.1 μA VEN = 5.5 V 0.02 Shutdown Temp increasing 160 Reset Temp decreasing 140 –40 V °C 125 °C Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater. Tolerance of external resistors not included in this specification. VDO is not measured for fixed output versions with VOUT(nom) < 1.8 V since minimum VIN = 1.7 V. Fixed-voltage versions only; refer to Applications section for more information. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 FUNCTIONAL BLOCK DIAGRAMS IN 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp Current Limit OUT 8kΩ GND R1 R1 + R2 = 80kΩ R2 NR Figure 1. Fixed Voltage Version IN Table 1. Standard 1% Resistor Values for Common Output Voltages VO 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp GND 8kΩ R2 1.2V Short Open 1.5V 23.2kΩ 95.3kΩ 1.8V 28.0kΩ 56.2kΩ 2.5V 39.2kΩ 36.5kΩ 2.8V 44.2kΩ 33.2kΩ 3.0V 46.4kΩ 30.9kΩ 3.3V 52.3kΩ 30.1kΩ NOTE: VOUT = (R1 + R2)/R2 × 1.204; R1R2 ≅ 19kΩ for best accuracy. OUT Current Limit R1 80kΩ R1 FB R2 Figure 2. Adjustable Voltage Version Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 5 TPS73250-Q1 SLVSBH6 – JUNE 2012 www.ti.com PIN CONFIGURATIONS IN 1 GND 2 EN 3 DRB PACKAGE 3mm x 3mm SON (TOP VIEW) DCQ PACKAGE SOT223 (TOP VIEW) DBV PACKAGE SOT23 (TOP VIEW) 5 6 OUT 4 TAB IS GND NR/FB 1 IN 2 3 4 OUT 1 8 IN N/C 2 7 N/C NR/FB 3 6 N/C GND 4 5 EN 5 GND EN OUT NR/FB PIN DESCRIPTIONS 6 NAME SOT23 (DBV) PIN NO. SOT223 (DCQ) PIN NO. 3×3 SON (DRB) PIN NO. IN 1 1 8 GND 2 3, 6 4, Pad EN 3 5 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section in Application Information for more details. EN can be connected to IN if not used. NR 4 4 3 Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 4 4 3 Adjustable voltage version only; this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 2 1 Output of the regulator. There are no output capacitor requirements for stability. DESCRIPTION Input supply Ground Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 TYPICAL CHARACTERISTICS For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. LOAD REGULATION LINE REGULATION 0.5 0.20 Referred to IOUT = 10mA −40_C +25_C +125_C Change in VOUT (%) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 Change in VOUT (%) 0.4 0.10 +25_ C +125_C 0.05 0 −0.05 −40_ C −0.10 −0.15 −0.4 −0.5 −0.20 0 50 100 150 200 0 250 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN − VOUT (V) IOUT (mA) Figure 3. Figure 4. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 100 100 TPS73225DBV 80 80 TPS73225DBV IOUT = 250mA 60 VDO (mV) VDO (mV) +125_ C +25_ C 40 60 40 20 20 −40_C 0 −50 0 0 50 100 150 200 250 −25 0 25 50 75 100 IOUT (mA) Temperature (_C) Figure 5. Figure 6. OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 30 125 18 IOUT = 10mA 16 25 I OUT = 10mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 0 −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/_ C) Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 7 TPS73250-Q1 SLVSBH6 – JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE 1000 800 900 700 IOUT = 250mA 800 600 600 I GND (µA) I GND (µA) 700 500 400 300 100 50 100 150 200 300 VIN = 5.5V VIN = 4V VIN = 2V 100 0 −50 0 0 400 200 VIN = 5.5V VIN = 4V VIN = 2V 200 500 250 −25 0 25 50 75 100 125 Temperature (_C) IOUT (mA) Figure 9. Figure 10. GROUND PIN CURRENT IN SHUTDOWN vs TEMPERATURE CURRENT LIMIT vs VOUT (FOLDBACK) 500 1 VENABLE = 0.5 V VIN = VOUT + 0.5 V 450 ICL Output Current (mA) IGND (µA) 400 0.1 350 300 ISC 250 200 150 100 50 0.01 -50 -25 0 25 50 75 100 TPS73233 0 -0.5 125 0 0.5 Temperature (°C) Figure 11. 2.0 2.5 3.0 3.5 CURRENT LIMIT vs TEMPERATURE 600 600 550 550 500 500 Current Limit (mA) Current Limit (mA) 1.5 Figure 12. CURRENT LIMIT vs VIN 450 400 350 300 450 400 350 300 250 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 250 −50 −25 VIN (V) 0 25 50 75 100 125 Temperature (_ C) Figure 13. 8 1.0 Output Voltage (V) Figure 14. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN - VOUT 40 90 IOUT = 100mA COUT = Any 80 35 30 IOUT = 1mA COUT = 10µF 60 50 IO = 100mA CO = 1µF IOUT = 1mA C OUT = Any 40 25 PSRR (dB) Ripple Rejection (dB) 70 IOUT = 1mA COUT = 1µF 20 15 30 20 IOUT = Any COUT = 0µF 10 VIN = VOUT + 1V 0 10 100 1k 10k Frequency = 10kHz COUT = 10mF VOUT = 2.5V IOUT = 100mA 10 I OUT = 100mA COUT = 10µF 5 0 100k 1M 0 10M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Frequency (Hz) VIN - VOUT (V) Figure 15. Figure 16. NOISE SPECTRAL DENSITY CNR = 0µF NOISE SPECTRAL DENSITY CNR = 0.01µF 1 1.8 2.0 1 eN (µV/√Hz) eN (µV/√Hz) C OUT = 1µF COUT = 0µF 0.1 COUT = 10µF COUT = 1µF 0.1 COUT = 0µF COUT = 10µF IOUT = 150mA IOUT = 150mA 0.01 0.01 10 100 1k 10k 100k 10 100 1k Frequency (Hz) Frequency (Hz) Figure 17. Figure 18. RMS NOISE VOLTAGE vs COUT 10k 100k RMS NOISE VOLTAGE vs CNR 60 140 50 120 VOUT = 5.0V VOUT = 5.0V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3V 20 20 CNR = 0.01µF 10Hz < Frequency < 100kHz 0.1 1 0 10 VOUT = 3.3V 60 40 VOUT = 1.5V 10 0 80 VOUT = 1.5V COUT = 0µF 10Hz < Frequency < 100kHz 1p COUT (µF) 10p 100p 1n 10n CNR (F) Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 9 TPS73250-Q1 SLVSBH6 – JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. TPS73233 LOAD TRANSIENT RESPONSE VIN = 3.8V TPS73233 LINE TRANSIENT RESPONSE COUT = 0µF 50mV/tick IOUT = 250mA VOUT COUT = 0µF 50mV/div COUT = 1µF 50mV/tick COUT = 10µF 50mV/tick VOUT VOUT VOUT C OUT = 100µF 50mV/div = 0.5V/µs dt 50mA/tick 4.5V 1V/div 10mA VIN I OUT 10µs/div 10µs/div Figure 21. Figure 22. TPS73233 TURN-ON RESPONSE TPS73233 TURN-OFF RESPONSE RL = 1kΩ COUT = 0µF RL = 20Ω COUT = 10µF VOUT R L = 20Ω C OUT = 1µF R L = 20Ω C OUT = 1µF 1V/div RL = 1kΩ COUT = 0µF RL = 20Ω COUT = 10µF VOUT 2V 2V VEN 1V/div 1V/div 0V 0V VEN 100µs/div 100µs/div Figure 23. Figure 24. TPS73233 POWER UP / POWER DOWN IENABLE vs TEMPERATURE 10 6 5 4 VIN VOUT IENABLE (nA) 3 Volts dVIN 5.5V 250mA 1V/div VOUT 2 1 1 0.1 0 −1 −2 50ms/div 0.01 −50 −25 0 25 50 75 100 125 Temperature (°C) Figure 25. 10 Figure 26. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 APPLICATION INFORMATION The TPS73250-Q1 belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS73250Q1 ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 27 shows the basic circuit connections for the fixed voltage models. Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN OUT VOUT TPS73250-Q1 EN GND OUTPUT NOISE A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS73250-Q1 and it generates approximately 32 µVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: V (R + R2 ) = 32 µVRMS ´ OUT VN = 32 µVRMS ´ 1 R2 VREF (1) Since the value of VREF is 1.2 V, this relationship reduces to: NR ǒmVV Ǔ ON OFF parallel, ringing may occur when the product of COUT and total ESR drops below 50 nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. RMS V N(mVRMS) + 27 Optional bypass capacitor to reduce output noise. V OUT(V) (2) for the case of no CNR. Figure 27. Typical Application Circuit for FixedVoltage Versions For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap reference output. This impedance helps compensate for leakages into the error amp terminals. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS73250-Q1 does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR capacitors are in An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10 Hz to 100 kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: ǒmVV Ǔ V N(mVRMS) + 8.5 RMS V OUT(V) (3) for CNR = 10 nF. This noise reduction effect is shown as RMS Noise Voltage vs CNR (Figure 20) in the Typical Characteristics section. Connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) will reduce output noise and improve load transient performance. The TPS73250-Q1 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250 μV of switching noise at ~4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 11 TPS73250-Q1 SLVSBH6 – JUNE 2012 www.ti.com BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. INTERNAL CURRENT LIMIT The TPS73250-Q1 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5 V. See Figure 12 in the Typical Characteristics section for a graph of IOUT vs VOUT. Note from Figure 12 that approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS73250-Q1 should be enabled first. ENABLE PIN AND SHUTDOWN The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V (max) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT (see Figure 23). When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot upon powerup. Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section. DROPOUT VOLTAGE For large step changes in load current, the TPS73250-Q1 requires a larger voltage drop from VIN to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN – VOUT above this line insure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worstcase conditions [full-scale instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS73250-Q1 can take a couple of hundred microseconds to return to the specified regulation accuracy. TRANSIENT RESPONSE The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1 μF) from the OUT pin to ground will reduce undershoot magnitude but increase its duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response. The TPS73250-Q1 does not have active pulldown when the output is overvoltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed voltage version) VOUT dV/dt = COUT ´ 80 kW P RLOAD (4) (Adjustable voltage version) VOUT dV/dt = COUT ´ 80 kW P (R1 + R2 ) P RLOAD (5) The TPS73250-Q1 uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 TPS73250-Q1 www.ti.com SLVSBH6 – JUNE 2012 REVERSE CURRENT The NMOS pass element of the TPS73250-Q1 provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80-kΩ internal resistor divider to ground (see Figure 1 and Figure 2). THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS73250-Q1 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS73250-Q1 into thermal shutdown will degrade device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Power Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): P D + (VIN * VOUT) I OUT (6) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. PACKAGE MOUNTING Solder pad footprint recommendations for the TPS73250-Q1 are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at www.ti.com. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS73250-Q1 13 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2012 PACKAGING INFORMATION Orderable Device TPS73250QDCQRQ1 Status (1) ACTIVE Package Type Package Drawing SOT-223 DCQ Pins Package Qty 6 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF TPS73250-Q1 : • Catalog: TPS73250 • Enhanced Product: TPS73250-EP NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2012 • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS73250QDCQRQ1 Package Package Pins Type Drawing SPQ SOT-223 2500 DCQ 6 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 7.05 B0 (mm) K0 (mm) P1 (mm) 7.45 1.88 8.0 W Pin1 (mm) Quadrant 12.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73250QDCQRQ1 SOT-223 DCQ 6 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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