ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 1-Mbps QUAD DIGITAL ISOLATORS Check for Samples: ISO7241A-EP FEATURES 1 • • • • • 4000-Vpeak Isolation, 560-Vpeak VIORM – UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1, IEC 60950-1 and CSA Approved 4-kV ESD Protection Operates With 3.3-V or 5-V Supplies Typical 25-Year Life at Rated Working Voltage (See Application Note (SLLA197 ) and Figure 10) High Electromagnetic Immunity (See Application Report (SLLA181)) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • ISO7241A (TOP VIEW) APPLICATIONS • • • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability VCC1 GND1 INA INB INC OUTD EN1 GND1 Industrial Fieldbus Computer Peripheral Interface Servo Control Interface Data Acquisition (1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB OUTC IND EN2 GND2 Additional temperature ranges available - contact factory DESCRIPTION See the Product Notification section. The ISO7241A is a quad-channel digital isolator with multiple channel configurations and output enable functions. This device has logic input and output buffers separated by TI’s silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, this device blocks high voltage, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. The ISO7241A has three channels the same direction and one channel in opposition. This device has TTL input thresholds and a noise-filter at the input that prevents transient pulses from being passed to the output of the device. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. (See ISO7240CF (SLLS869) or contact TI for a logic low failsafe option). The ISO7241A may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V, 5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used. This device is characterized for operation over the ambient temperature range of –55°C to 125°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated ISO7241A-EP SLLSE18 – JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel Filter OSC + PWM Pulse Width Demodulation Vref Carrier Detect EN IN Input + Filter Data MUX AC Detect Vref OUT Output Buffer AC Channel Table 1. Device Function Table (1) INPUT VCC (1) OUTPUT VCC (1) (2) 2 OUTPUT ENABLE (EN) OUTPUT (OUT) H H or Open H L H or Open L X L Z PU PU Open H or Open H PD PU X H or Open H PD PU X L Z PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level Table 2. ORDERING INFORMATION (1) PACKAGE (2) TA –55°C to 125°C INPUT (IN) DW Reel ORDERABLE PART NUMBER TOP-SIDE MARKING ISO7241AMDWREP ISO7241AM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT VCC Supply voltage (2), VCC1, VCC2 –0.5 to 6 V VI Voltage at IN, OUT, EN –0.5 to 6 V IO Output current ±15 mA Human Body Model JEDEC Standard 22, Test Method A114-C.01 ESD Electrostatic Field-Induced-Charged Device discharge Model TJ Maximum junction temperature Machine Model (1) (2) JEDEC Standard 22, Test Method C101 ±4 All pins ANSI/ESDS5.2-1996 kV ±1 ±200 V 170 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage (1), VCC1, VCC2 IOH High-level output current IOL Low-level output current tui 3.15 TYP MAX 5.5 4 UNIT V mA –4 mA Input pulse width 1 μs 1/tui Signaling rate 0 1000 kbps VIH High-level input voltage (IN) (EN on all devices) 2 VCC V VIL Low-level input voltage (IN) (EN on all devices) 0 0.8 V TJ Junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification (1) 150 1000 °C A/m For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP 3 ISO7241A-EP SLLSE18 – JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION , over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Quiescent ICC1 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent ICC2 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps 6.5 11 13 20 13 20 mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at 0 V, Single channel VCC – 0.8 IOH = –20 μA, See Figure 1 VCC – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) μA 0 IOH = –4 mA, See Figure 1 V IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 150 mV 10 IN from 0 V to VCC –10 25 V μA 2 pF 50 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level-to-high-impedance output tPZL Propagation delay, high-impedance-to-low-level output tfs Failsafe output delay time from input power loss (1) (2) 4 See Figure 1 MIN TYP 40 MAX 95 10 (2) 2 See Figure 1 See Figure 2 See Figure 3 2 ns ns ns 2 15 20 15 20 15 20 15 20 12 UNIT ns μs Also referred to as pulse skew. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 6.5 11 8 13 8 13 UNIT SUPPLY CURRENT Quiescent ICC1 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent ICC2 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at 0 V, Single channel VOH High-level output voltage IOH = –4 mA, See Figure 1 IOH = –20 μA, See Figure 1 VCC – 0.8 V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) μA 0 (5-V side) 150 mV 10 IN from 0 V to VCC –10 IN at VCC, VI = 0.4 sin (4E6πt) 25 V μA 2 pF 50 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level-to-high-impedance output tPZL Propagation delay, high-impedance-to-low-level output tfs Failsafe output delay time from input power loss (1) (2) See Figure 1 MIN TYP 40 MAX 100 11 (2) 3 See Figure 1 See Figure 2 See Figure 3 2 UNIT ns ns ns 2 15 20 15 20 15 20 15 20 18 ns μs Also known as pulse skew tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP 5 ISO7241A-EP SLLSE18 – JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Quiescent ICC1 Quiescent ICC2 4 7 4 7 13 20 13 20 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at VCC, Single channel VOH High-level output voltage IOH = –4 mA, See Figure 1 VCC – 0.8 IOH = –20 μA, See Figure 1 V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) μA 0 (5-V side) 150 mV 10 IN from 0 V to VCC –10 2 25 V μA pF 50 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 40 100 tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss (1) (2) 6 See Figure 1 11 (2) 2.5 See Figure 1 See Figure 2 See Figure 3 2 ns ns ns 2 12 UNIT ns μs Also known as pulse skew tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Quiescent ICC1 1 Mbps Quiescent ICC2 1 Mbps VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 4 7 4 7 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 8 13 8 13 mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at 0 V, single channel VCC – 0.4 IOH = –20 μA, See Figure 1 VCC – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) μA 0 IOH = –4 mA, See Figure 1 V IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 150 mV 10 IN from 0 V or VCC –10 25 V μA 2 pF 50 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level-to-high-impedance output tPZL Propagation delay, high-impedance-to-low-level output tfs Failsafe output delay time from input power loss (1) (2) See Figure 1 MIN TYP MAX 45 110 12 (2) UNIT ns 3.5 See Figure 1 See Figure 2 See Figure 3 2 ns 2 15 20 15 20 15 20 15 20 18 ns μs Also referred to as pulse skew. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP 7 ISO7241A-EP SLLSE18 – JANUARY 2010 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms Vcc Vcc ISOLATION BARRIER 0V RL = 1 kW ±1% IN Input Generator VI OUT EN Vcc/2 VI t PZL VO VO CL Vcc/2 0V t PLZ Vcc 0.5 V 50% NOTE B 50 W VOL 3V ISOLATION BARRIER NOTE A IN Input Generator VI Vcc OUT VO Vcc/2 VI Vcc/2 0V EN 50 W t PZH CL NOTE B RL = 1 kW ±1% VO VOH 50% 0.5 V t PHZ 0V NOTE A A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 PARAMETER MEASUREMENT INFORMATION (continued) VI 0V or VCC1 IN VCC1 ISOLATION BARRIER VCC1 2.7 V VI OUT VO 0V tfs VOH CL NOTE B VO 50% fs low VOL A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 S1 IN ISOLATION BARRIER C = 0.1 mF± 1% GND1 C = 0.1 mF± 1% OUT NOTE B Pass-fail criteria: Output must remain stable VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP 9 ISO7241A-EP SLLSE18 – JANUARY 2010 www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 8.34 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm 0.008 mm Minimum Internal Gap (Internal Clearance) Distance through the insulation RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance Input to output CI Input capacitance to ground >1012 Ω VI = 0.4 sin (4E6πt) 2 pF VI = 0.4 sin (4E6πt) 2 pF DEVICE I/O SCHEMATICS Enable VCC Output Input VCC VCC VCC VCC 1 MW 1 MW 500 W 8W 500 W IN EN VCC VCC OUT 13 W REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File Number: 40016131 File Number: 1698195 File Number: E181974 (1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Low-K Thermal Resistance (1) 168 High-K Thermal Resistance 96.1 UNIT θJA Junction-to-air θJB Junction-to-Board Thermal Resistance 61 °C/W θJC Junction-to-Case Thermal Resistance 48 °C/W PD (1) 10 Device Power Dissipation VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50% duty cycle square wave °C/W 220 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 TYPICAL CHARACTERISTIC CURVES INPUT VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE VCC1 FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE 1.4 3 5 V Vth+ 1.3 2.9 VCC1 - Failsafe Threshold - V Input Voltage Threshold - V 1.35 3.3 V Vth+ 1.25 1.2 Air Flow at 7 cf/m, Low_K Board 1.15 5 V Vth1.1 2.8 VCC at 5 V or 3.3 V, Load = 15 pF, Air Flow at 7/cf/m, Low-K Board 2.7 Vfs+ 2.6 2.5 Vfs- 2.4 2.3 2.2 1.05 1 -40 3.3 V Vth-25 -10 2.1 5 20 35 50 65 80 TA - Free-Air Temperature - °C 95 110 2 -40 125 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - °C Figure 5. Figure 6. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 50 VCC = 5 V Load = 15 pF, TA = 25°C Load = 15 pF, TA = 25°C 45 40 IO - Output Current - mA 40 IO - Output Current - mA -25 VCC = 3.3 V 30 20 35 VCC = 3.3 V 30 25 VCC = 5 V 20 15 10 10 5 0 0 0 2 4 VO - Output Voltage - V 6 0 Figure 7. 1 2 3 VO - Output Voltage - V 4 5 Figure 8. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP 11 ISO7241A-EP SLLSE18 – JANUARY 2010 www.ti.com APPLICATION INFORMATION 2 mm max. from VCC1 VCC1 2 mm max. from VCC2 VCC2 0.1 mF 0.1 mF 1 16 2 15 IN A 3 14 OUT A IN B 4 13 OUT B IN C 5 12 OUT C OUT D 6 11 IND 7 10 8 9 GND1 GND2 EN1 EN2 GND2 GND1 ISO7241A Figure 9. Typical Application Circuit LIFE EXPECTANCY vs. WORKING VOLTAGE WORKING LIFE -- YEARS 100 VIORM at 560-V 28 Years 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (VIORM) -- V Figure 10. Time-Dependant Dielectric Breakdown Testing Results 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP ISO7241A-EP www.ti.com SLLSE18 – JANUARY 2010 PRODUCT NOTIFICATION An ISO7241A anomaly occurs when a negative-going pulse below the specified 1-μs minimum bit width is input to the device. The output locks in a logic-low condition until the next rising edge occurs after a 1-μs period. Positive noise edges in pulses of less than the minimum specified 1 μs have no effect on the device, and are properly filtered. To prevent noise from interfering with ISO7241A performance, it is recommended that an appropriately sized capacitor be placed on each input of the device Figure 11. ISO7241A Anomaly Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): ISO7241A-EP 13 PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ISO7241AMDWREP ACTIVE SOIC DW 16 2000 TBD Call TI Call TI ISO7241AMDWREPG4 ACTIVE SOIC DW 16 2000 TBD Call TI Call TI V62/10606-01XE ACTIVE SOIC DW 16 2000 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF ISO7241A-EP : • Catalog: ISO7241A NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2012 • Catalog - TI's standard catalog product Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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