TI SN74AUP3G14

SN74AUP3G14
www.ti.com
SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
LOW-POWER TRIPLE SCHMITT-TRIGGER INVERTER
Check for Samples: SN74AUP3G14
FEATURES
1
•
2
•
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 μA Maximum)
Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Wide Operating VCC Range of 0.8 V to 3.6 V
DCU PACKAGE
(TOP VIEW)
1A
3Y
2A
GND
1
2
7
3
6
4
1A
3Y
2A
GND
1Y
3A
2Y
5
•
1
8
2
7
3
6
4
5
VCC
1Y
3A
2Y
YFP PACKAGE
(TOP VIEW)
RSE PACKAGE
(TOP VIEW)
DQE PACKAGE
(TOP VIEW)
VCC
8
•
•
•
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 4.3 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
VCC
1Y
8
1
3A
2
2Y
3
1A
7
4
1A
3Y
2A
GND
6
3Y
5
2A
A1
1 8
A2
B1
2 7
B2
C1
3 6
C2
D1
45
D2
VCC
1Y
3A
2Y
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
(µA)
100%
40%
60%
3.3-V
(A)
Logic
40%
Voltage (V)
80%
80%
60%
Switching Characteristics
at 25 MHz(A)
Dynamic-Power Consumption
(pF)
100%
3.3-V
(A)
Logic
20%
20%
AUP
AUP
0%
(A)
0%
AUP
Single, dual, and triple gates
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Input
0
5
(A)
Figure 1. AUP – The Lowest-Power Family
Output
10
15
20 25 30
Time (ns)
35
40
45
SN74AUP3Gxx data at CL = 15 pF.
Figure 2. Excellent Signal Integrity
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
SN74AUP3G14
SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
www.ti.com
The SN74AUP3G14 contains three inverters and performs the Boolean function Y = A. The device functions as
three independent inverters but, because of Schmitt action, it may have different input threshold levels for
positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
–40°C to 85°C
(1)
(2)
(3)
2
ORDERABLE
PART NUMBER
PACKAGE (2)
TA
TOP-SIDE
MARKING (3)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
Reel of 3000
SN74AUP3G14YFPR
___HF_
uQFN – DQE
Reel of 5000
SN74AUP3G14DQER
TX
QFN – RSE
Reel of 5000
SN74AUP3G14RSER
TX
SSOP – DCU
Reel of 3000
SN74AUP3G14DCUR
H14_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
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SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
Pin numbers shown are for the DCU and DQE package.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
4.6
UNIT
V
(2)
VI
Input voltage range
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state (2)
–0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
DCU package
220
DQE package
261
RSE package
253
YFP package
(1)
(2)
(3)
V
°C/W
132
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUP3G14
SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
MAX
0.8
3.6
V
Input voltage
0
3.6
V
Output voltage
0
VCC
V
VCC = 0.8 V
–20
μA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65
–1.9
VCC = 2.3 V
–3.1
VCC
Supply voltage
VI
VO
IOH
www.ti.com
High-level output current
VCC = 3 V
IOL
Low-level output current
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
(1)
4
Operating free-air temperature
mA
–4
VCC = 3 V
TA
UNIT
μA
mA
4
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
ΔVT
Hysteresis
(VT+ – VT–)
VOH
MIN
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
0.6
0.8 V
0.3
0.6
0.3
1.1 V
0.53
0.9
0.53
0.9
1.4 V
0.74
1.11
0.74
1.11
1.65 V
0.91
1.29
0.91
1.29
2.3 V
1.37
1.77
1.37
1.77
3V
1.88
2.29
1.88
2.29
0.8 V
0.1
0.6
0.1
0.6
1.1 V
0.26
0.65
0.26
0.65
1.4 V
0.39
0.75
0.39
0.75
1.65 V
0.47
0.84
0.47
0.84
2.3 V
0.69
1.04
0.69
1.04
3V
0.88
1.24
0.88
1.24
0.8 V
0.07
0.5
0.07
0.5
1.1 V
0.08
0.46
0.08
0.46
1.4 V
0.18
0.56
0.18
0.56
1.65 V
0.27
0.66
0.27
0.66
2.3 V
0.53
0.92
0.53
0.92
3V
0.79
1.31
0.79
1.31
IOH = –20 μA
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
IOH = –2.3 mA
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
VOL
TA = 25°C
1.9
1.85
2.72
2.67
2.6
2.55
0.8 V to 3.6 V
0.1
0.1
IOL = 1.1 mA
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
2.3 V
IOL = 3.1 mA
IOL = 2.7 mA
3V
IOL = 4 mA
V
V
V
V
IOL = 20 μA
IOL = 2.3 mA
UNIT
0.44
0.45
0 V to 3.6 V
0.1
V
0.5
μA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
μA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
μA
ICC
VI = GND or
(VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.5
0.9
μA
ΔICC
VI = VCC – 0.6 V (1),
IO = 0
3.3 V
40
50
μA
Ci
VI = VCC or GND
Co
VO = GND
II
(1)
A or B input VI = GND to 3.6 V
0V
1.5
3.6 V
1.5
0V
pF
3
pF
One input at VCC – 0.6 V, other input at VCC or GND
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SN74AUP3G14
SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
TYP
1.2 V ± 0.1 V
2.6
1.5 V ± 0.1 V
MAX
MIN
MAX
7.3
12.8
2.1
15.6
1.4
5.2
8.7
0.9
10.3
1.8 V ± 0.15 V
1
4.2
6.6
0.5
8.2
2.5 V ± 0.2 V
1
3
4.4
0.5
5.5
3.3 V ± 0.3 V
1
2.4
3.5
0.5
4.3
0.8 V
tpd
A or B
Y
TA = –40°C to 85°C
UNIT
18
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
TYP
0.8 V
A
Y
MAX
MIN
MAX
UNIT
18.4
1.2 V ± 0.1 V
tpd
TA = –40°C to 85°C
4.6
7.9
13.4
1.3
16.7
1.5 V ± 0.1 V
4
6
9.6
2.2
11.8
1.8 V ± 0.15 V
3.6
5
7.9
2.4
9.5
2.5 V ± 0.2 V
3.2
4
5.5
2.3
6.8
3.3 V ± 0.3 V
2.9
3.5
4.6
2.1
5.6
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
TYP
0.8 V
tpd
A or B
Y
TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
24
1.2 V ± 0.1 V
3.6
9.9
16.3
3.1
19.9
1.5 V ± 0.1 V
2.3
7.2
11.1
1.8
13.2
1.8 V ± 0.15 V
1.6
5.8
8.7
1.1
10.6
2.5 V ± 0.2 V
1
4.3
5.9
0.5
7.3
3.3 V ± 0.3 V
1
3.4
4.8
0.5
5.9
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
0.8 V
tpd
6
A or B
Y
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
32.8
1.2 V ± 0.1 V
4.9
13.1
20.9
4.4
25.5
1.5 V ± 0.1 V
3.4
9.5
14.2
2.9
16.9
1.8 V ± 0.15 V
2.5
7.7
11
2
13.5
2.5 V ± 0.2 V
1.8
5.7
7.6
1.3
9.4
3.3 V ± 0.3 V
1.5
4.7
6.2
1
7.5
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ns
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SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
4
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.1
3.3 V ± 0.3 V
4.3
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UNIT
pF
7
SN74AUP3G14
SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
Output
VCC/2
VM
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for
propagation delays tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
F.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 x V CC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 x V CC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 xV CC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + V ∆
VOL
tPHZ
VCC/2
VOH - V ∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPLH and tPHL are the same as tpd.
G.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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SN74AUP3G14
SCES764D – SEPTEMBER 2009 – REVISED AUGUST 2012
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REVISION HISTORY
Changes from Revision C (July 2010) to Revision D
•
10
Page
Deleted input transition rise or fall rate (Δt/Δv) paramater from Recommended Operation Conditons table ....................... 4
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN74AUP3G14DCUR
ACTIVE
US8
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H14R
SN74AUP3G14DQER
ACTIVE
X2SON
DQE
8
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TX
SN74AUP3G14RSER
ACTIVE
UQFN
RSE
8
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TX
SN74AUP3G14YFPR
ACTIVE
DSBGA
YFP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(HF2 ~ HFN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AUP3G14DCUR
US8
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74AUP3G14DQER
X2SON
DQE
8
5000
180.0
8.4
1.2
1.6
0.55
4.0
8.0
Q1
SN74AUP3G14RSER
UQFN
RSE
8
5000
180.0
8.4
1.6
1.6
0.66
4.0
8.0
Q2
SN74AUP3G14YFPR
DSBGA
YFP
8
3000
178.0
9.2
0.9
1.75
0.6
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP3G14DCUR
US8
DCU
8
3000
202.0
201.0
28.0
SN74AUP3G14DQER
X2SON
DQE
8
5000
202.0
201.0
28.0
SN74AUP3G14RSER
UQFN
RSE
8
5000
202.0
201.0
28.0
SN74AUP3G14YFPR
DSBGA
YFP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
D: Max = 1.59 mm, Min = 1.53 mm
E: Max = 0.79 mm, Min = 0.73 mm
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