Advance Information PE42672 DIE SP7T UltraCMOS™ 2.75 V Switch 100 – 3000 MHz, +68 dBM IIP3 Figure 1. Functional Diagram Features • Dedicated TX1 port for WCDMA, TX2 • WCDMA TX1 RX1 • GSM/EDGE TX2 RX2 GSM/EDGE TX3 RX3 • • • RX4 CMOS Control/Driver and ESD V1 V2 • • • and TX3 ports for GSM/EDGE Three pin CMOS logic control with integral decoder/driver Exceptional harmonic performance: 2fo = -84 dBc and 3fo = -77 dBc Low TX insertion loss: 0.50 dB at 900 MHz, 0.70 dB at 1900 MHz TX – RX Isolation of 44 dB at 900 MHz, 38 dB at 1900 MHz 1500 V HBM ESD tolerance all ports +68 dBm IIP3 -111 dBm IMD3 No blocking capacitors required V3 Product Description Figure 2. Die Top View* TX1 ANT RX1 GND RX2 1206 µm GND TX2 GND RX3 GND GND RX4 TX3 GND GND GND VDD V3 GN V2 V1 GND 1006 µm * Dimensions shown are drawn die size. Document No. 70-0197-01 │ www.psemi.com Contact [email protected] for full version of datasheet The PE42672 is a HaRP™-enhanced SP7T RF Switch developed on the UltraCMOS™ process technology. It addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market for use in GSM/EDGE/PCS/DCS/WCDMA handsets. The switch is comprised of three TX ports and four RX ports. TX1 is designed for WCDMA and TX2 and TX3 are designed for GSM/ EDGE. The four symmetric RX ports can be used for GSM/EDGE/PCS RX. On-chip CMOS decoder logic facilitates three-pin low voltage CMOS control, while high ESD tolerance of 1500 V at all ports, no blocking capacitor requirements, and on-chip SAW filter overvoltage protection devices make this the ultimate in integration and ruggedness. Peregrine’s HaRP™ technology enhancements deliver high linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOS™ process, providing performance superior to GaAs with the economy and integration of conventional CMOS. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 4 PE42672 Advance Information Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V Parameter Condition Typ Units Insertion loss1 TX - Ant (850 / 900) TX - Ant (1800 / 1900) TX - Ant ( 2200 UMTS ) RX - Ant (850 / 900) RX - Ant (1800 / 1900) 0.5 0.7 0.8 0.8 1.0 dB dB dB dB dB Return Loss Port under test in on state 20 dB Isolation TX - RX (850 / 900) TX - RX (1800 / 1900) TX - TX (850 / 900) TX - TX (1800 / 1900) TX1 - RX (1900 / 2200) 44 38 29 23 37 dB dB dB dB dB 2nd Harmonic TX 850 / 900 MHz, +35 dBm output power, 50 Ω TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω -84 -80 dBc dBc 3rd Harmonic TX 850 / 900 MHz, +35 dBm output power, 50 Ω TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω -77 -73 dBc dBc IMD3 distortion at 2.14 GHz TX1 Measured at 2.14 GHz at Ant port, input +20 dBm CW signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz -111 dBm Note: 1. Insertion loss specified with optimal impedance matching. Table 2. Operating Ranges Parameter Table 3. Absolute Maximum Ratings Symbol Min Temperature range TOP -40 VDD Supply Voltage VDD 2.65 IDD Power Supply Current (VDD = 2.75 V) IDD TX input power2 (VSWR ≤ 3:1) RX input power (VSWR =1:1) Max Units Symbol +85 °C VDD 2.75 2.85 V 13 50 µA Typ Parameter/Conditions Min Max Units Power supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD+ 0.3 V TST Storage temperature range -65 +150 °C PIN(50 Ω) PIN +35 dBm PIN +20 dBm VIH Control Voltage Low VIL 1.4 V 0.4 V Note: 2. Assumes RF input period of 4620 µs and duty cycle of 50%. +38 RX input power (50 Ω) 3,4 +23 dBm PIN (∞:1) TX input power (VSWR = ∞:1) 2 Control Voltage High TX input power (50 Ω) 3,4 3,4 +35 dBm ESD Voltage (HBM, MIL_STD 883 Method 3015.7) 1500 V ESD Voltage at ANT Port (IEC 61000-4-2) 1700 V VESD Note: 3. Assumes RF input period of 4620 µs and duty cycle of 50%. 4. V DD within operating range specified in Table 2. Part performance is not guaranteed under these conditions. Exposure to absolute maximum conditions for extended periods of time may adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 4 Document No. 70-0197-01 │ UltraCMOS™ RFIC Solutions Contact [email protected] for full version of datasheet PE42672 Advance Information Table 4. Pin Descriptions Figure 3. Pad Configuration (Top View) Pin Name Description 1 ANT RF Common – Antenna 6 2 TX1 RF I/O - TX1 35 GND Ground (Requires two bond wires) 46 TX2 RF I/O – TX2 55 GND Ground 65 TX3 RF I/O – TX3 75 GND Ground 85 GND Ground 9 VDD Supply V3 Switch control input, CMOS logic level ANT Pin No. 5 4 19 GND 7 GND 6 8 PE42672 Die 9 15 GND 11 12 13 14 Switch control input, CMOS logic level Table 5. Truth Table 13 V1 Switch control input, CMOS logic level Ground Path RX1 - ANT RX2 - ANT RX3 - ANT RX4 - ANT TX1 - ANT TX2 - ANT TX3 - ANT All Off 5 14 GND Ground 155 GND Ground 166 RX4 RF I/O – RX4 5 GND Ground 6 RX3 RF I/O – RX3 5 GND Ground 6 RX2 RF I/O – RX2 5 21 GND Ground 226 RX1 RF I/O – RX1 20 GND RX4 17 10 V2 GND RX3 16 GND 5 6 18 V2 V1 GND TX3 12 19 GND RX2 20 GND 18 RX1 21 3 11 17 22 V3 GND TX2 1 VDD 10 2 GND TX1 V1 0 1 0 1 0 1 0 1 V2 0 0 1 1 0 0 1 1 V3 0 0 0 0 1 1 1 1 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Notes: 5. Bond wires should be physically short and connected to ground plane for best performance. 6. Blocking capacitors needed only when non-zero DC voltage present. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 6. Ordering Information Order Code Description Package Shipping Method 42672-90 PE42672-DIE-D Film Frame Wafer (Gross Die / Wafer Quantity) 42672-99 PE42672-DIE-400G Waffle Pack 400 Dice / Waffle Pack 42672-00 PE42672-DIE-1H Evaluation Kit 1/ box Document No. 70-0197-01 │ www.psemi.com Contact [email protected] for full version of datasheet ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 4 PE42672 Advance Information Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 4 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Document No. 70-0197-01 │ UltraCMOS™ RFIC Solutions Contact [email protected] for full version of datasheet